JPH056330A - Bus control system for extended unit - Google Patents

Abstract

PURPOSE:To make it possible to use a slow extended board. CONSTITUTION:A programmable logic array(PLA) 10 judges whether an I/O address 3 outputted from a computer 1 is an address included in a range allocated to an extended board 2 followed by signal delay exceeding a reference waiting time corresponding to the specification of the computer 1 or not. When the address 3 is included in the range concerned, an I/O waiting signal 9 is immediately outputted to the computer 1 at the time of outputting an I/O access signal 5 or 6 from the computer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for an expansion unit for expanding the functions of a computer such as a small personal computer.

[0002]

2. Description of the Related Art One of the bus control methods widely used as an I / O expansion bus for personal computers is I.
There is an SA (Industrial Standard Architecture) bus control system. The ISA bus complies with the PC-AT bus system of IBM Corporation and has an open architecture (information disclosure). Therefore, it is currently used in personal computers of many computer manufacturers.

FIG. 2 is a diagram showing a connection state of a conventional expansion unit. As shown, for computer 1,
The I / O expansion board 2 is connected by the ISA bus. That is, this figure shows the signal line names necessary for the read / write of the 16-bit I / O of the I / O expansion board 2 conforming to the above-mentioned ISA bus specification. Address (SA0-SA
9) 3 is a memory address or an input / output address output by the computer 1.

The SYSCLK signal 4 synchronizes the operation of various devices. The IOW signal 5 is set to low level to instruct writing of data to the I / O expansion board 2. The IOR signal 6 is set to a low level to instruct the reading of data from the I / O expansion board 2. The IOCS16 signal 7 is a signal output by the I / O expansion board 2 when the address 3 is input.

FIG. 3 shows the I / O from the computer 1 of FIG.
7 is a time chart for explaining an access operation to the extension board 2. The various control signals shown in the figure are all SYSCLK.
It operates based on signal 4. First, computer 1
Addresses (SA0-S0) to the I / O expansion board 2.
A9) 3 is sent out. If the I / O expansion board 2 has 16 bits at this time, the IOCS16 signal 7 is set to low level (time T2). After that, the computer 1
When reading the expansion board 2, the IOR signal 6 is set to low level, and when writing to the I / O expansion board 2, I
The OW signal 5 is set to low level (time point T2).

The I / O expansion board 2 can confirm that it is being accessed for the first time by receiving the IOR signal 6 or the IOW signal 5. That is, at the time of address transmission, it cannot be confirmed because the memory access or the I / O access cannot be distinguished. Where IS
According to the A bus specification, 1 wait is inserted as standard for 16-bit I / O access. Therefore, IOW
When the I / O expansion board 2 that has received the signal 5 or the IOR signal 6 requires two waits or more, the IOCHRDY signal 8 output to the computer 1 is set to the low level. As a result, an arbitrary weight of 2 weights or more is inserted.

[0007]

However, the above-mentioned conventional techniques have the following problems. That is, in order to expand the ISA bus by connecting an expansion unit in order to expand the functions of a small personal computer that cannot have a standard expansion slot for compactness, it is necessary to add a buffer or the like, Since the connection cable becomes long, the following problems occur.

As shown in FIG. 3, IOR signal 6 or IO
After the W signal 5 is received by the I / O expansion board 2,
When the O expansion board 2 tries to insert two or more waits into the computer 1 of the ISA bus specification, t = tT1−
The IOCHRDY signal 8 must be brought to a low level within the time period from t1 to t2 (time point T2). In other words, when this time t is exceeded, the computer 1 cannot receive the IOCHRDY signal 8 within the standard 1 wait.

However, when the expansion unit is connected, the IOCHRDY signal 8 is delayed by the buffer in the expansion unit and the connecting cable. Therefore, IOCHR
The DY signal 8 does not reach the computer 1 within a time t from the I / O expansion board 2. As a result, the I / O expansion board 2 cannot insert an additional weight, and the computer 1 may read / write incorrect data. For this reason, there is a problem that a low-speed I / O expansion board with signal delay cannot be connected. The present invention has been made in view of the above points, and an object of the present invention is to provide a bus control system for an expansion unit capable of utilizing a low-speed I / O expansion board.

[0010]

According to the bus control method of an expansion unit of the present invention, an input / output address output from a computer is assigned to an expansion board with a signal delay exceeding a standard wait time according to the specifications of the computer. A programmable logic array that immediately determines whether or not the address is within the specified range, and when the address is within the range, immediately outputs the input / output wait signal to the computer when the input / output access signal from the computer is output. Is provided.

[0011]

In the bus control method for the expansion unit of the present invention, the programmable logic array first causes the expansion board with a signal delay in which the input / output address output from the computer exceeds the standard wait time according to the specifications of the computer. It is determined whether the address is within the range assigned to the. When the address is within the range, the input / output wait signal is immediately output to the computer when the input / output access signal is output from the computer.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a bus control system of an expansion unit of the present invention. The expansion unit shown includes an internal HDD (hardware disk device) 1
1 is standardly implemented. Further, the expansion unit is provided with one or two slots (not shown) for mounting the I / O expansion board 2. Built-in HDD11 is ISA
It is a 16-bit I / O device that can operate with one wait, which is the standard for bus specifications.

An arbitrary I / O expansion board can be mounted in the expansion slot for the I / O expansion board. In order to mount a low-speed 16-bit I / O expansion board in this expansion slot, a PLA (Programmable Logic Array) 10 in which a circuit for automatically inserting two waits is programmed is prepared. The PLA 10 receives the bus control signals 3 to 7 as shown in FIG. 1, and the IOCHRDY-A signal 9 is output as follows by the logic programmed in advance.

When 16-bit I / O access is made to the built-in HDD 11 which is standardly mounted in the expansion unit shown in the figure, first, the I / O address of the built-in HDD 11 is SA0-SA0.
It is output to SA9. When the PLA 10 receives SA0 to SA9, it assigns it to the internal HDD 11
/ O address is determined. This decision is
The PLA 10 is implemented by incorporating a logic for determining the magnitude relationship between the addresses SA0 to SA9 and a predetermined address. Here, the I / O output by the computer 1
If the address is the I / O address of the internal HDD 11,
The PLA 10 does not drop the IOCHRDY-A signal 8 to low level. As a result, 16-bit I / O read / write to the built-in HDD unit operates with the standard weight of the ISA bus specification, and the processing speed does not decrease.

If the I / O address output from the computer 1 is the I / O address of the I / O expansion board 2 installed in the I / O expansion slot, the PLA 10
Lowers the IOCHRDY-A signal 9 to add one wait to the standard cycle of the ISA bus specification. As a result, a total of 2 weights are inserted in the 16-bit I / O expansion board 2 mounted in the expansion slot. Therefore, according to the present embodiment, it is possible to insert weights of 2 weights or more in all 16-bit I / O expansion boards other than the built-in HDD 11.

FIG. 4 shows the I / O from the computer 1 of FIG.
7 is a time chart for explaining an access operation to the extension board 2. The various control signals shown in the figure are all SYSCLK.
It operates based on signal 4. First, computer 1
Addresses (SA0-S0) to the I / O expansion board 2.
A9) 3 is transmitted (time point T2). At this point, if the I / O expansion board 2 has 16 bits, the IOCS16 signal 7 is set to low level. After that, the computer 1
When reading the expansion board 2, the IOR signal 6 is set to low level, and when writing to the I / O expansion board 2, I
The OW signal 5 is set to low level (time point T2).

The I / O expansion board 2 can confirm that it is being accessed for the first time by receiving the IOR signal 6 or the IOW signal 5. That is, at the time of address transmission, it cannot be confirmed because the memory access or the I / O access cannot be distinguished. Where IS
According to the A bus specification, 1 wait is inserted as standard for 16-bit I / O access. Therefore, IOW
If the I / O expansion board 2 that receives the signal 5 or the IOR signal 6 requires more than two waits, the PLA 10
Is output to the computer 1 IOCHRDY-
The A signal 9 is set to low level. As a result, another weight is inserted.

That is, as shown in FIG. 4, after the IOR signal 6 or IOW signal 5 is received by the I / O expansion board 2, the I / O expansion board 2 waits for two waits for the computer 1 of the ISA bus specification. If you try to insert more, I
The OCHRDY signal 8 is output (time point T3). In this case, the IOCHRDY signal 8 is delayed by the buffer in the expansion unit and the connecting cable, and the time tW = tT1-t1.
-Reach computer 1 after t2. However, P
The IOCHRDY-A signal 9 output from LA10 is
Because there is no buffer or long cable, the computer 1 has IOCH within the standard 1 wait.
The RDY-A signal 9 can be received. As a result, two waits are made and the memory 3 is guaranteed until time T5 (solid line portion in the figure). If 3 waits are required, the I / O expansion board 2 sends the IOCHRDY signal 8 to the computer 1 by the time T3, so that the memory 3 is guaranteed by the time 6 ( (Dotted line in the figure).

[0019]

As described above, according to the bus control system of the expansion unit of the present invention, the programmable logic array for checking the address output by the computer and outputting the bus control signal for adding the wait time is provided. Since it is provided, a low-speed I / O expansion board with signal delay can be connected. As a result, for example, when a standard 16-bit I / O device is provided in the expansion unit and an expansion slot is provided, this I / O
A low-speed 16-bit I / O expansion board that requires additional weight can be mounted in the expansion slot and used without reducing the access speed of the device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a bus control system of an expansion unit according to the present invention.

FIG. 2 is a diagram showing a connection state of a conventional expansion unit.

FIG. 3 is a time chart for explaining conventional I / O access timing.

FIG. 4 is a time chart for explaining I / O access timing according to the method of the present invention.

[Explanation of symbols]

 1 Computer 2 I / O Expansion Board 10 PLA 11 Built-in HDD

Claims (1)

What is claimed is: 1. An input / output address output from a computer is an address within a range assigned to an expansion board with a signal delay exceeding a standard wait time according to the specifications of the computer. If the address is within the range, a programmable logic array that immediately outputs an input / output wait signal to the computer when the input / output access signal from the computer is output is provided. Unit bus control method.