JPH056367B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to GaAs FET ICs that are created by forming FETs and resistors on a GaAs semiconductor wafer and connecting them, and more specifically, to these ICs.
Of these, it relates to a GaAs FET IC circuit that converts an unbalanced high-frequency signal into a balanced high-frequency signal.

Conventionally, ICs using GaAs wafers have been used for amplifiers,
The main focus is on the development of mixers, and there are few examples of ICs that require balanced signals. Furthermore, it is difficult to create a balanced signal inside a GaAs FET IC, as there are announcements that require a balanced signal for the input signal for prescalers.

On the other hand, it has a silicon bipolar process.
In ICs, differential transistor circuits are generally used to perform unbalanced/balanced conversion, but in this case, the high frequency characteristics are not good and the operation is limited to several hundred MHz.

FIG. 1 shows an example of an unbalance/balance conversion circuit constructed using a silicon bipolar process. In the figure, 40 and 41 are differential transistors, and 42 is a constant current transistor. In this circuit, when a single unbalanced signal is applied to input terminal 1, balanced signals with uniform levels are obtained from output terminals 2 and 3, but the frequency thereof is limited to relatively low frequencies.

Figure 2 shows GaAs based on the same idea as Figure 1.
This is a conventional example of an unbalanced/balanced conversion circuit made on a wafer. In this figure, a power supply voltage is applied to terminal 4, a high frequency signal is input from terminal 1, and high frequency differential signals can be obtained at terminals 2 and 3. The characteristics of this circuit are that the gain is almost constant over high frequencies exceeding 1 GHz, and the phase difference between the two outputs is approximately 180 degrees. However, there is a gain difference between the two outputs. The disadvantage was that the gain of the output in phase with the input signal (output point 3 in the figure) was several dB lower.

An object of the present invention is to provide an unbalanced/balanced conversion IC circuit using GaAs wafer and having good high frequency characteristics and balance characteristics.

GaAs according to the present invention to achieve the above object
In the FET circuit, a FET and a resistor are formed on the same GaAs wafer, the source electrode and gate electrode of the first FET are grounded, the source electrodes of the second and third FET are connected in common, and the common connection is made. point and the drain electrode of the first FET, insert a resistor between each gate electrode of the second and third FET and the common connection point, and connect the second FET to the drain electrode of the first FET.
The gate electrode of the FET is grounded at high frequency, and the third
The gate electrode of the FET is connected to an electrode for inputting a high frequency signal, and the drain electrodes of the second and third FETs are connected to output terminals, respectively.

According to the above structure, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 3 is a circuit diagram showing a reference example of a GaAs FET IC circuit according to the present invention. The unbalanced high frequency signal is applied between the input terminal 5 and the ground, and a signal of opposite phase is outputted to the output terminal 6 by the operation of the third GaAs FET 46 formed on the wafer. Another feature of using GaAs FETs is that when the input signal frequency is changed, the output signal level remains almost constant up to high frequencies. A high frequency current flows through the resistor 24, and as a result, the terminal 6
The same high-frequency current that gave the output to resistor 2
1. Flows through the first GaAs FET 48. This current path and the other second GaAs FET4
Since the gate of the second GaAs FET 47 is grounded at high frequency, as long as the path through which the source current flows in the second GaAs FET 47
The same high frequency current flows through the drain resistor 25 of 47, and the direction of current flow is opposite to that of the resistor 24, so the level between output terminals 6 and 7 is the same with respect to ground, and the polarity is 180. It is possible to obtain balanced signals of different degrees.

The above explanation should also hold true in Figure 2, and according to the above considerations, the level between output terminals 2 and 3 is the same between output terminals 2 and 3, and the polarity is 180°. You should be able to get different balanced signals. However, in reality, the signal level obtained at terminal 3 is several dB lower than the signal level obtained at terminal 2, and this is true even in a sufficiently low frequency band. The cause is GaAs
Current path flowing through the source of FET43 and GaAs
This is believed to be because the path of the current flowing through the source of the FET 44 is not actually the same. FIG. 4 shows an equivalent circuit diagram of the circuit around the sources of GaAs FETs 43 and 44 in the circuit of FIG. 2, and will be discussed. In the figure, a resistor 27 represents a source resistance existing inside the GaAs FET 43, and a FET 49 represents an ideal FET excluding the source resistance. Similarly, the resistor 28 is
This is the internal source resistance of GaAs FET44,
FET50 shows an ideal FET excluding this. GaAs
The circuit consisting of the FET 45 and the resistor 20 is regarded as a resistor whose value is constant at high frequencies, and its equivalent resistance is indicated by 29. Due to the existence of the source resistors 27 and 28 inside the GaAs FET, the paths of the source currents of the ideal FETs 49 and 50 are not exactly the same, and the current applied to the source of the ideal FET of the FET 50 is caused by the resistors 29 and 27. It is reduced to a partial pressure. That is, the source current of the ideal FET 49 passes through the resistor 27 and the resistor 29 and reaches the ground point.

And, R27 and R29 are connected to both ends of the resistor 29.
are the resistance values of resistors 27 and 29, respectively.
A voltage reduced to R27/(R27+R29) is generated,
This voltage is applied between the source and gate of the ideal FET 50 via the resistor 28.

Therefore, a current value reduced by R27/(R27+R29) as compared to the current value flowing through the resistor 18 flows through the resistor 19 connected to the drain of the ideal FET 50.

Based on the above considerations, it is possible to reduce the source resistance existing inside the GaAs FET, or to perfect the operation of the circuit consisting of the GaAs FET 45 and the resistor 20 as a constant current circuit, and to make the value of the equivalent resistance 29 sufficiently large. It is considered that the output levels of output terminals 2 and 3 can be made almost the same. fabricated on GaAs wafer
The source resistance inside the FET is GaAs FET
It is determined by the structure of the circuit and is not affected by changes in the circuit. In addition, constant current circuits using GaAs FETs are
Since the Gm of GaAs FET is not very large, a sufficiently effective constant current circuit cannot be obtained. Furthermore, at high frequencies, the effect of increasing the value of the equivalent resistance 29 is small unless the distributed capacitance is reduced.

In FIG. 3 showing a reference example of the present invention, the second
In order to compensate for the loss of high frequency current flowing into the source of the third GaAs FET 47, a third GaAs FET 4
A resistor 22 is inserted between the gate of FET 6 and the drain of the first GaAs FET 48. Due to the presence of this resistor, the input high frequency signal applied to the terminal 5 is not only applied to the gate of the third GaAs FET 46, but also passes through the resistor 22 to the second GaAs FET 46.
A correction voltage is also applied to the source side of 47, and the second
The high frequency current flowing through the drain of the GaAs FET 47 is increased, and the levels of the output terminals 6 and 7 can be made the same. In FIG. 3, a resistor 23 is inserted in the same way as resistor 22 in order to maintain the symmetry of the circuit, and for this purpose the second and third GaAs FETs 4
6,47 DC operating points are balanced.

FIG. 5 shows an embodiment of the present invention. In this example, 2
The circuit on the GaAs chip surrounded by the dashed dotted line, the power supply 53 externally connected to it, which is applied to terminal 8, the DC cut capacitor 34 of output terminal 5, the bias coil 39, and the common mode bias voltage adjustment to terminals 5 and 9. and a bias differential power source 52 between terminals 5 and 9.
In the circuit on the GaAs chip, the first GaAs FET48
There is a resistor 37 in series with the drain of the resistor 37 and the connection point between the resistor 37 and the sources of the second and third GaAs FETs 46, 47 and the second and third GaAs FETs 46, 47.
Resistors 35 and 36 are connected between the gates of . The high frequency signal applied to terminal 5 is
An opposite phase signal is applied to the gate of the GaAs FET 46 and is applied to the terminal 6 through the drain resistor 24.
Further, the same current also flows to the source and flows toward the source of the second GaAs FET 47 while undergoing some loss. On the other hand, a part of the high frequency signal applied to the terminal 5 passes through the resistor 35 and goes to the source of the GaAs FET 47. This signal causes the second GaAs FET47
The signal level toward the source of the third GaAs FET 46 is increased, and a signal in phase with the gate is input to the source of the third GaAs FET 46, thereby lowering the output level of the terminal 6. To maintain symmetry, a resistor 36 is added between the gate and source of the second GaAs FET 47, and the second and third GaAs FETs 46,
A balance of 47 DC operating points is obtained.

In this embodiment, the second and third GaAs FETs 46,
The source of 47 was directly connected to the resistor 37, but the third
As explained in the reference example of the figure, the source and resistor 3
A resistor can also be inserted between the connection points 5, 36, and 37. Furthermore, as shown in this figure, by adjusting the biases of terminals 5 and 9, the level difference between output terminals 6 and 7 can be further reduced. By adjusting the common mode voltage 51, the output balance can be adjusted while maintaining the DC balance of the second and third GaAs FETs 46 and 47. In addition, the second and third GaAs FETs 46,
47 is corrected by adjusting power supply 52.

In this example, the balanced signal output is output from the chip through terminals 6 and 7, but it is also possible to directly connect this signal to other circuits within the same chip for integration. Further, although the high frequency grounding of the terminal 9 and the DC cut of the terminal 5 are performed outside the chip, they can be placed in the same wafer to further reduce the size. Although we have shown an example in which the input signal is supplied from outside the chip, it is also possible to connect it to another circuit within the same chip to achieve integration.

From the above, according to the present invention, by utilizing the high speed of GaAs FETs, it is possible to realize an unbalanced/balanced conversion circuit with excellent high frequency characteristics and good output level balance on a GaAs wafer.
The circuit according to the present invention exhibits effects such as improved balance characteristics, smaller size, and lower cost.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an unbalance/balance conversion IC circuit using a silicon bipolar process. Figure 2 is a circuit diagram showing an unbalance/balance conversion IC circuit formed on a GaAs wafer based on Figure 1. Figure 3 is a circuit diagram showing a reference example of the present invention, Figure 4 is an equivalent circuit diagram showing the area around the source of the differential circuit in the circuit of Figure 2, and Figure 5 is an example of a GaAs FET circuit according to the present invention. It is a circuit diagram. 1, 5...Input terminal, 2,6...Negative phase output terminal, 3,7...In-phase output terminal, 4,8...Power supply terminal, 10-29, 35-37...Resistor, 30,3
2, 34...Input DC cut capacitor, 31,
33...Capacitor for high frequency grounding, 38...Grounding terminal, 39...Chiyoke coil for bias, 40
~42...Silicon bipolar transistor, 4
3 to 50...GaAs FET, 51, 52...Bias power supply, 53...Power supply.

Claims (1)

[Claims] 1 A FET and a resistor are formed on the same GaAs wafer, the source electrode and gate electrode of the first FET are grounded, the source electrodes of the second and third FET are connected in common, and the common connection point and the 1 of
Connect the drain electrode of the FET and connect the second and third
A resistor is inserted between each gate electrode of the FET and the common connection point, and the second FET
The gate electrode of the third FET is grounded at high frequency.
A GaAs FET circuit characterized in that the gate electrode of the second FET is connected to an electrode for inputting a high frequency signal, and the drain electrodes of the second and third FETs are connected to respective output terminals.