JPH056372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal discrimination circuit, and more specifically, it detects the presence or absence of a television video signal, and detects when there is no video signal or when the video signal is not a regular video signal. In this case, this is to be determined.
The discriminated signal is related to a signal discrimination circuit used, for example, to block audio signals.

Conventional configuration and its problems For example, the easiest way to determine the presence or absence of a video signal is to directly detect the amplitude value of the video signal, but this makes it difficult to distinguish between a normal video signal and noise. Therefore, it is impossible to use it practically. On the other hand, like a television receiver,
In a video device equipped with a flyback pulse, since this flyback pulse has a phase that matches the synchronization signal, it is relatively easy to determine the presence or absence of a video signal by logically multiplying both pulses using an AND circuit or a NAND circuit. A discrimination circuit can be constructed. However, the above-mentioned configuration is not possible in a video device, such as a VTR (video tape recorder), which does not have a flyback pulse.

Furthermore, noise is mixed into the regular video signal,
Even if the image is no longer clear, as long as it is recognizable, it must be determined as a regular video signal. However, if the amount of noise becomes large compared to a regular video signal, a problem arises in that the signal cannot be determined as a regular video signal. In order to eliminate such inconveniences, a circuit function such as a noise removal circuit must be made an essential circuit element of the signal discrimination circuit. Moreover, if a signal discrimination circuit having the above-described function is to be built into an integrated circuit device, for example, it must be accepted that the cost will be relatively high because the number of external pins is limited.

OBJECTS OF THE INVENTION The present invention has been made to overcome the above-mentioned disadvantages, and has a particular object to provide a video signal discrimination circuit suitable for VTRs and the like that do not have flyback pulses.

Another object of the present invention is to provide a signal discriminating circuit which has a very simple circuit configuration and therefore does not require a noise removal circuit or the like and does not malfunction due to noise.

Structure of the Invention The present invention provides a sawtooth wave whose part of the period is selected to be smaller than the pulse width of a reference input signal of an AFC circuit, and which is synchronized with the upper and lower limit values of the sawtooth wave, and which is synchronized with the reference input signal of the AFC circuit. A CR oscillator generates an oscillation pulse selected to be smaller than the pulse width of the signal, and a pair of transistors whose emitters are connected in common receive the sawtooth wave at one base and apply a voltage to the other base to generate the sawtooth wave. a waveform conversion circuit that converts a square wave into a rectangular wave, and a loop that controls the oscillation frequency of the CR oscillator using the output signal of the AFC circuit, the oscillation pulse being one input, and the This is a signal discriminator circuit including an AND circuit which receives a reference input signal as the other input via an integrating circuit.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows an embodiment of the signal discrimination circuit of the present invention, and FIG. 2 shows an operation waveform diagram of the main part of FIG.

The operation will be described in detail below with reference to these figures.

First, to the potential of the horizontal oscillation input terminal 13, a charging potential charged to the horizontal oscillation capacitor 18 from the power supply terminal 20 via the horizontal hold polymer 19 is added. This charging potential is added as the base potential of the transistor 24, and the initial base potential _VH of the transistor 25 whose emitters are commonly connected to the transistor 24 is determined by the resistances _R28 , _R29 and _R30 and the power supply voltage _VCC . It is given by Eq.

V _H = V _CC・(R ₂₉ + R ₃₀ )/(R ₂₈ + R ₂₉ + R ₃₀ )
(1) Here, R ₂₈ , R ₂₉ , and R ₃₀ are the resistance values of the resistors 28, 29, and 30 in FIG. 1, and V _CC is the voltage value applied to the power supply terminal 20. When the base potential of the transistor 24 reaches _VH , the transistor 24 is turned on, the transistor 25 is turned off, and the collector of the transistor 24 is connected to the resistor 2.
7 through which the current I _{26 of the current source 26} flows. As a result, transistor 33 is turned on, transistors 31 and 22 are turned on, and the collector potential of transistor 31 becomes the collector saturation voltage value. If this saturation voltage is considered to be approximately zero volts, the base potential V _L of the transistor 25 at this time is given by the following equation.

V _L = L _CC · R ₂₉ / (R ₂₈ + R ₂₉ ) ...(2) On the other hand, when the transistor 22 is turned on, the electric charge charged in the horizontal oscillation input terminal 13 is transferred to the V Discharged to the potential of _L. When the horizontal oscillation input terminal 13, that is, the base potential of the transistor 24 reaches the V _L ,
The transistor 25 is turned on, the transistor 24 is turned off, the on/off operations of the transistors 33, 31, and 22 are reversed, and the horizontal oscillation capacitor 18 is charged again. By repeating the above operations, a sawtooth wave is generated at the horizontal oscillation input terminal 13. This sawtooth wave is shown in Figure 2a.
Shown below. Incidentally, the charging time t _c and discharging time t _d of this sawtooth wave are given by the following equations.

t _c = R ₁₉・C ₁₈・l _o (V _CC −V _L )/(V _CC −V _H )
...(3) t _d R ₂₁・C ₁₈・_lo (V _H /V _L ) ...(4) Here, R ₁₉ is the resistance value of the horizontal hold volume 19, R ₂₁ is the resistance value of the resistor 21, and C ₁₈ is the capacitance value of the horizontal oscillation capacitor 18.

Correspondingly, an oscillation pulse shown in FIG. 2b is output to the collector of the transistor 24.
This pulse corresponds to the discharge time td of the sawtooth wave.
This discharge period, ie, the pulse width output to the collector of the transistor 24, is proportional to the values of the resistor 21 and capacitor 18, as shown in equation (4) above.
Therefore, when the resistor 21 is constructed of, for example, a semiconductor integrated circuit, a desired horizontal oscillation pulse width can be selected by changing the capacitance of the capacitor 18. FIG. 2c shows a pulse waveform generated at the horizontal oscillation pulse output terminal 41.

Further, the sawtooth wave generated at the horizontal oscillation input terminal 13 is applied to the base of the transistor 34.
At this time, a DC potential V ₃₇ is applied to the base of the transistor 35 whose emitters are commonly connected to the transistor 34.
, the transistor 34 is turned on in the sawtooth wave portion where the base potential of the transistor 34 is higher than the V ₃₇ , and conversely, the transistor 35 is turned on in the portion where the base potential is lower than the V ₃₇ . Therefore, the rectangular wave shown in FIG. 2d is output to the collector of the transistor 35, and this rectangular wave is applied to the base of the transistor 4. At this time, the potential V ₈ of the DC voltage terminal 8 is applied to the bases of the transistors 4 and 5 via the resistors 6 and 7.
When the potential of the rectangular wave applied to the base of transistor 4 becomes lower than the base potential of transistor 5, transistor 5 is turned on. Now, when a positive horizontal synchronization pulse shown in FIG. 2e, which is the reference input signal of the AFC circuit, is applied from the horizontal synchronization signal input terminal 1, transistor 2 turns on and draws current from transistors 4 and 5. transistors 2, 4, 5, 9, 10, 11 and resistor 3,
The AFC circuit consisting of 6 and 7 is activated.

By the way, in the AFC circuit, when the horizontal oscillation pulse and the horizontal synchronizing pulse match in phase, a current ΔI _AFC shown in FIG. 2f is outputted to the AFC output terminal 12. This output current ΔI _AFC is smoothed by smoothing capacitors 14 and 15 and a smoothing resistor 16, and is applied to a horizontal oscillation capacitor 18 via a resistor 17. As shown in FIG. 2 f, when the horizontal oscillation pulse and the horizontal synchronization pulse are in phase, the sum I _AFC of both the positive and negative components of ΔI _AFC in one period becomes zero, and the horizontal oscillation capacitor 18 The charging and discharging time remains unchanged.

Now, if the frequency of the horizontal oscillation pulse becomes higher, the period of the rectangular wave applied to the base of the transistor 4 becomes shorter, and ΔI _AFC becomes larger on the negative side. Here, ΔI _AFC is defined as positive in the direction flowing out from the AFC output terminal 12. Therefore, I _AFC becomes negative and draws the charging current of the horizontal oscillation capacitor 18 through the resistor 17. As a result, the charging time of the horizontal oscillation capacitor 18 becomes longer, and the oscillation frequency becomes lower. On the other hand, when the frequency of the oscillation pulse becomes lower than the frequency of the reference input signal, the period of the rectangular wave applied to the base of the transistor 4 becomes longer, and ΔI _AFC becomes larger on the positive side. Therefore,
Since I _AFC becomes positive and is applied to the oscillation capacitor 18 via the resistor 17, the oscillation frequency becomes higher. In this way, the oscillation pulse of the oscillator can be matched correctly.

Furthermore, the horizontal synchronizing pulse of positive polarity shown in FIG. It is applied as one input signal to circuit 44. The other input of the AND circuit 44 is given the positive oscillation pulse shown in FIG. 2c outputted to the horizontal oscillation output terminal 41, and the two pulses are compared.

Next, the operation of signal discrimination will be explained.

3 to 6 are diagrams used to explain the operation of signal discrimination, and in each of FIGS. 3 to 5, a indicates a horizontal synchronizing pulse state, and b indicates an oscillation pulse.
Further, c indicates the voltage appearing on the output conductor 45 of the AND circuit 44, and d indicates the voltage V ₄₇ held at the peak value by the emitter of the transistor 46, that is, the capacitor 48 and the resistor 49. In the signal discrimination circuit of the present invention, when the video signal is in a normal state, the peak value holding voltage V ₄₇ is set to "L".
Otherwise, it is intended to be "H".

First, FIG. 3 will be explained. FIG. 3 is a diagram for explaining the basic signal discrimination operation when a regular video signal is received. Here, the AND circuit 4
If 4 is configured with an AND circuit, output terminal 45
, a zero volt occurs as shown in FIG. 3c. Therefore, V ₄₇ held at its peak value becomes zero volts.
It should be noted here that the oscillation pulse width τosc is set smaller than the horizontal synchronization pulse width τsync. This is based on the fact that the output conductor 45 is intended to be zero volts in the case of a regular video signal, and if the above setting conditions are deviated from, the output conductor 45 will be ”
This is because pulses are generated, making normal signal discrimination impossible.

FIG. 4 shows a case where the integration function is not performed, for example, when the capacitor 54 is not connected and noise X is superimposed on the horizontal synchronizing pulse. In this case, the amount of noise superimposed on the horizontal synchronization pulse is output as is only during the horizontal oscillation pulse period.
At this time, the voltage at which the peak value is held is shown in Figure 4 d.
As shown in , it is not held until “H”,
The voltage will be between zero volts and "H" as shown at V _47A . This is based on the fact that the peak value is not sufficiently maintained in the noise component.

Figure 5 shows that when the integral function is fully utilized,
That is, a case is shown in which noise is further superimposed on the horizontal synchronizing pulse under the circuit configuration of FIG. 1. As is clear from FIG. 5A, the horizontal synchronizing pulse is integrated by the resistor 56 and the capacitor 54, and at the same time, the noise X is also integrated, and especially those with small pulse widths and amplitudes are attenuated. Therefore, the amount of noise is reduced, and the noise outputted to the output conductor 45 of the AND circuit 44, as shown in FIG. 5c, is smaller than that shown in FIG. 4c. As a result,
The voltage taken out to the output terminal 47 is the above-mentioned V _47A .
For example, in Figure 6,
V _4B will be the specified voltage.

Now, the held voltage is determined by the voltage comparator 51
is applied as one input voltage. Further, as the other input voltage, a reference voltage V ₅₀ is applied from the reference voltage application terminal 50, and both the holding voltage V ₄₇ and the reference voltage V ₅₀ are compared, and a DC voltage is output to the signal discrimination output terminal 52. Ru. At this time, when the holding voltage _{V 47 is} lower than the reference voltage V ₅₀ with respect to the reference voltage V 50, it is determined as a regular signal, and conversely, when it is equal to or higher than the reference voltage V ₅₀ , it is determined as a non-video signal.

Also, as is clear from Fig. 6, the reference voltage V ₅₀
It can be easily seen that the difference between _{the reference voltage V 50 and} the voltage V 47B is greater than the difference between the reference voltage V 50 and the voltage V _47A . This is advantageous for the signal discrimination circuit, as it allows normal discrimination even if the amount of noise increases further.

Note that the voltage output to the signal discrimination output terminal 52 is used, for example, to block audio signals.

Effects of the Invention As described above, the signal discrimination circuit of the present invention uses a horizontal synchronizing pulse as a reference input signal, and when obtaining a sawtooth wave, automatically generates the oscillation pulse, which is the reference input signal of the AFC circuit. By configuring it to match the position of the horizontal synchronizing pulse, and by providing an extremely simple integration circuit sufficient to attenuate the noise mixed in with the horizontal synchronizing pulse, we were able to eliminate the need for a noise removal circuit. Therefore, it is particularly suitable for integrated circuits and the like that are restricted by external terminals, and its utility value is sufficiently high.

[Brief explanation of drawings]

Fig. 1 is a signal discrimination circuit diagram of the present invention, Fig. 2 a~
f is an operation waveform diagram of the main part in FIG. 1, a to d in FIGS. 3 to 5 are operation waveform diagrams for explaining signal discrimination,
FIG. 6 is a characteristic operation diagram of signal discrimination. 1...Horizontal synchronization pulse input terminal, 8, 37...
DC voltage terminal, 12...AFC output terminal, 13...
...Oscillation input terminal, 14, 15... Smoothing capacitor, 16... Smoothing resistor, 17... Resistor, 18...
...Horizontal oscillation capacitor, 19...Hold volume, 20...Power supply terminal, 26, 36...Current source, 41...Horizontal oscillation pulse output terminal, 42...
Inverter, 44...AND circuit, 45...Output conductor, 50...Reference voltage application terminal, 51...Voltage comparator, 52...Signal discrimination output terminal.

Claims (1)

[Claims] 1 A part of the period is a sawtooth wave selected to be smaller than the pulse width of the reference input signal of the AFC circuit, and is synchronized with the upper and lower limit values of the sawtooth wave, and is greater than the pulse width of the reference input signal. A CR oscillator, which generates an oscillation pulse selected to be as small as possible, receives the sawtooth wave at one base of a pair of transistors whose emitters are commonly connected, and applies a voltage to the other base to convert the sawtooth wave into a rectangular wave. a waveform conversion circuit that converts the rectangular wave to the base of one transistor of a differential amplifier constituting the AFC circuit as a comparison input signal; 1. A signal discrimination circuit comprising an AND circuit forming a loop for controlling an oscillation frequency, taking the oscillation pulse as one input and taking the reference input signal as the other input via an integrating circuit.