JPH0564307B2 - - Google Patents

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to a semiconductor integrated circuit testing system, and more specifically, a semiconductor integrated circuit under test using a plurality of test modules having predetermined test functions. The present invention relates to an improvement in a semiconductor integrated circuit test system configured to perform tests on semiconductor integrated circuits.

<Prior Art> One type of semiconductor integrated circuit test system is an analog semiconductor integrated circuit test system that uses an analog semiconductor integrated circuit as a test object.

As shown in Figure 6, one type of conventional analog semiconductor integrated circuit test system consists of one processor CPU and multiple processors connected in parallel to this processor CPU via a bus.
Some test modules are composed of a CPU' and a plurality of test modules MDL connected to each of these processors CPU'. Here, test module
The MDL includes a DC voltage generation module that provides a DC voltage as a test signal to an analog semiconductor integrated circuit under test (not shown), an audio signal generation module that provides an audio signal, and an analog semiconductor integrated circuit under test that responds to each input test signal. A DC signal module that measures DC signals output from a circuit, an audio signal measurement module that measures audio signals, and a relay matrix module that arbitrarily switches the connections between these test modules and the analog semiconductor integrated circuit under test are used. It will be done.

FIG. 7 is an example of a timing chart for test execution in the conventional analog semiconductor integrated circuit test system shown in FIG. An example is shown in which a signal measurement module is used to set the connection relationship between each test module and the analog semiconductor integrated circuit under test to a desired state using a relay matrix module.

(A) shows a specific example of instructions output from the CPU. That is, the CPU first controls the relay matrix module so that the connection relationship between each test module and the analog semiconductor integrated circuit under test is set to a predetermined state according to the DC signal measurement and audio signal measurement. For example, commands for each row and each column (row 1 relay selection, row 2 relay selection, etc.) are sent for selectively turning on and off the relays located at each intersection. Next, CPU′2 controls the DC voltage generation module.
It sends commands (DC output voltage range selection, DC output voltage setting, output relay ON) to output the desired DC output voltage. Next, commands (audio output filter selection, audio output level setting, output relay ON) for outputting a desired audio signal are sent to the CPU'3 that controls the audio signal generation module.
Next, control the DC signal measurement module
A command (DC measurement range selection, DC measurement start) for measuring a DC signal under predetermined conditions is sent to the CPU'4. Thereafter, a command (audio measurement filter selection, audio measurement start) for measuring an audio signal under predetermined conditions is sent to the CPU'5 that controls the audio signal measurement module.

(B) shows the execution status of instructions in CPU′1,
(C) shows the execution status of instructions in CPU'2, (D)
indicates the execution state of instructions in CPU′3, and (E)
Shows the execution status of instructions in CPU'4, (F)
It shows the execution state of instructions in CPU'5.

Sends commands (audio output filter selection, audio output level setting, output relay on) to output the desired audio signal.

<Problems to be Solved by the Invention> Generally, each test module of the conventional analog semiconductor integrated circuit test system shown in FIG.
The configuration data given to MDL is n bytes (n≧
It consists of 1). Depending on the test content, a plurality of i test modules may have to be used as described above.

Further, testing of an analog semiconductor integrated circuit under test is often performed a plurality of K times for one analog semiconductor integrated circuit under test. In other words, in order to execute one type of test with a conventional analog semiconductor integrated circuit test system, n×i×
K bytes of setting data and i×K setting data execution commands must be transmitted from the processor CPU to each CPU' that controls a predetermined test module before receiving measurement data from the analog semiconductor integrated circuit under test. First, it occupies a large proportion of the test execution time. In the actual test, multiple N
It is necessary to test each analog semiconductor integrated circuit under test, and the time required to transmit these setting data and setting data execution commands is a major factor hindering test efficiency.

Furthermore, the conventional analog semiconductor integrated circuit test system shown in FIG. 1 is configured each time according to the processor CPU used.
Expanding the system was extremely difficult.

Possible ways to shorten test execution time include increasing the number of data transfer bits sent from the processor each time or increasing the data transfer speed, but this increases the cost. There are drawbacks.

The present invention solves these conventional drawbacks, and its purpose is to provide flexibility in system configuration and shorten test execution time.

<Means for Solving the Problems> A first invention for solving the problems described above is configured to test a semiconductor integrated circuit under test using a plurality of test modules having predetermined test functions. In a semiconductor integrated circuit test system, there is a high-level processor that has a function of managing the operation of the entire system and a function of managing all test programs that can be performed by the system, a middle-level processor CPU5 that is controlled according to the high-level processor, and Connected to the processor CPU5 by bus in parallel,
It consists of a plurality of lower processor CPUs 6 which have the function of controlling test modules according to the upper processor and middle processor CPU 5 to execute a test on the semiconductor integrated circuit under test, and executes a predetermined test on the semiconductor integrated circuit under test. After the necessary programs are read all at once from the memory of the upper processor, these read programs are transferred to the upper processor as the program number and specification information of the middle processor CPU5, and to the middle processor CPU5 as the program. Logic and execution procedure table, specifying the same single number and the execution contents of the tests that are configured consecutively to that number in order to simultaneously execute different types of tests in parallel for multiple lower processor CPUs 6 Each execution table is divided and downloaded, and when executing the test, the upper processor sends a command to the middle processor CPU5 that stores the program logic to be started, and the middle processor CPU5 reads the execution procedure table. The program logic is executed according to the commands from the upper processor while referring to the
The CPU 6 is characterized in that it searches the execution table in accordance with a single number consisting of a plurality of bits added from the intermediate processor CPU 5, and simultaneously drives predetermined test modules in parallel.

A second invention is a semiconductor integrated circuit test system configured to test a semiconductor integrated circuit under test using a plurality of test modules each having a predetermined test function, which manages the operation of the entire system. A high-level processor having the function of managing all test programs that can be performed by the system; a plurality of medium-level processors CPU5 connected to the high-level processor in parallel by a bus and controlled according to the high-level processor; and each medium-level processor CPU5. The upper processor and each intermediate processor are connected to the bus in parallel to
The CPU 6 comprises a plurality of lower processor CPUs 6 having the function of controlling the test module to execute a test on the semiconductor integrated circuit under test according to 5. are read all at once from the memory of the upper processor, these read programs are stored in the upper processor as the program number and specification information for the middle processor CPU5, and in the middle processor CPU5 as the program logic and execution procedure table. In order to simultaneously execute different types of tests in parallel, each of the plurality of lower processor CPUs 6 is divided into execution tables that specify the same single number and the execution contents of the tests that are arranged consecutively to that number. When executing the test, the upper processor identifies the middle processor CPU 5 that stores the program logic to be started and sends a command.
The middle processor CPU5 executes program logic according to commands from the upper processor while referring to the execution procedure table, and each lower processor CPU6 executes according to a single number made up of multiple bits added from the middle processor CPU5. It is characterized by searching a table and driving predetermined test modules simultaneously and in parallel.

<Operation> In the first invention, each sixth processor searches the execution table according to a single number made up of a plurality of bits added from a higher-order processor, and simultaneously drives a predetermined test module in parallel.

In the second invention, each sixth processor searches the execution table in accordance with a single number consisting of a plurality of bits added from the fifth processor and simultaneously drives a predetermined test module in parallel.

In any of these inventions, a small amount of data representing a single number may be added to each sixth processor during test execution, thereby substantially reducing the time required for test execution.

Furthermore, according to the second invention, since a plurality of fifth processors are used, a plurality of different tests can be performed simultaneously and in parallel using different single numbers.

<Example> Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, in which CPU1 is a first processor, CPU2 is a second processor, CPU3 is a third processor,
CPU4 is a fourth processor, CPU5 is a fifth processor, CPU6 is a sixth processor, and MDL is a test module.

The CPU 1 has the function of managing the operation of the entire semiconductor integrated circuit test system,
CPU3, CPU4 and CPU5 are connected in parallel. The CPU 2 has a function of managing all programs for testing semiconductor integrated circuits that can be executed by the semiconductor integrated circuit test system, and is connected to the CPU 4 as necessary. CPU3 has the function of generating a command to read the program necessary for executing a predetermined test from CPU2 and adding it to CPU1, and CPU4 has the function of generating a command added from CPU3 and adding it to CPU2 via CPU1. It has a function to read programs. These first processor CPU1, second processor CPU2, third processor CPU3, and fourth processor CPU4 manage the operation of the entire semiconductor integrated circuit test system, and
It functions as an upper processor that manages all programs for testing semiconductor integrated circuits that can be performed by this test system. The configuration and functions of such a higher-level processor are disclosed in, for example, Japanese Patent Laid-Open No. 164340/1983. The CPU 5 controls the CPU 6 in accordance with the CPU 1, and the embodiment shown in FIG. 1 shows an example in which two CPUs 5 are connected in parallel via a bus and controlled. The CPU 6 has a function of controlling the MDL according to the CPU 1 and the CPU 5 and executing a test using the MDL. In addition, when there is only one CPU5, the functions of CPU5 may be included in the upper processor; in this case,
The CPU 6 will be connected in parallel to the upper processor via a bus.

The operation of the semiconductor integrated circuit test system configured as described above will be explained.

Prior to execution of the test, a test program number corresponding to the semiconductor integrated circuit to be tested is input from the input terminal of the CPU 3. This results in
The CPU 3 sends a command to read the program, and the CPU 1 receives this command and transmits it to the CPU 4. CPU4 receives this command, transmits it to CPU2, reads a series of programs according to the command from CPU2's memory all at once, and stores it in the memory shared with CPU1.
Temporarily stored without going through CPU1. When the writing of this program is completed, CPU4 will be
Interrupt 1. When the CPU 1 receives this interrupt, it sequentially reads out the programs written in the shared memory and temporarily stores them in the CPU 1's memory. After writing the test program according to the command to CPU1 in this way, write this program to CPU1, CPU5 and
The data is downloaded to the CPU 6 to be divided and temporarily stored according to each function.

First, CPU1 is the program number and CPU
When a plurality of CPUs 5 are connected, information specifying the CPU 5 is selected in a minimum bit-compatible manner and is loaded into the memory. Next, CPU1 selects CPU5,
The program logic to be executed by that CPU5 is
The machine code of CPU5 is written to the memory of CPU5. Note that this machine code is created by the CPU 2 so that the CPU 5 can start test execution according to a fixedly given start address. In addition to the program logic, the CPU 5 also includes a procedure table consisting of an array of single numbers indicating the program execution procedure corresponding to the contents of a series of tests depending on the type of semiconductor integrated circuit under test, and a program execution start A label table indicating addresses is also stored. Here, the program logic stored in the CPU 5 is a collection of other programs that cannot be tabulated. And each
The CPU 6 stores an execution table consisting of a single number consisting of a plurality of bits (for example, 16) and information specifying the execution contents of a test configured in succession to that number. FIG. 2 is a system diagram showing an example of such downloading. FIG. 3 is a conceptual diagram of the execution procedure table stored in the CPU 5. As mentioned above, a single number is used to indicate the execution procedure of a program corresponding to the content of a series of tests depending on the type of semiconductor integrated circuit under test. An array is stored. Furthermore, FIG. 4 is a conceptual diagram of the execution table stored in each CPU 6, in which information specifying the execution contents of the tests configured in a manner that includes a single number and consecutive numbers as described above is stored. ing.

After the download is complete, run the test. When running the test,
It will be controlled by CPU1, CPU5 and CPU6. That is, the CPU 1 only identifies which CPU 5 stores the program logic to be activated and sends a command to the CPU 5. The CPU 5 executes program logic according to commands from the CPU 1 while referring to the procedure table and label table. A single number consisting of a plurality of bits stored in the procedure table is sequentially added to the CPU 6 from the CPU 5. The CPU 6 searches the execution table according to the single number, drives the MDL according to the searched contents, and executes the test. Thereby, a single number added from the CPU 5 can access multiple CPUs 6 at the same time to perform multiple tests. Then, each CPU 6 drives the MDL and executes a predetermined test according to a single number sequentially added from the procedure table stored in the CPU 5, thereby performing a series of tests depending on the type of semiconductor integrated circuit to be tested. is completed.

Furthermore, by using a plurality of CPUs 5, it is also possible to simultaneously access a plurality of CPUs 6 using different single numbers and perform a plurality of tests.

A specific example of performing multiple tests by simultaneously accessing multiple CPUs 6 using a single number will be described using the timing chart shown in FIG. The test contents in Fig. 5 are almost the same as the explanation of the operation of the conventional test system described above, and are shown in steps. The connection relationship with multiple pins of the semiconductor integrated circuit is set using the relay matrix module, and a specified DC voltage is applied from the DC voltage generation module to the specified pin of the analog semiconductor integrated circuit under test via the relay matrix module. An audio signal is applied from the audio signal generation module to a specified pin of the analog semiconductor integrated circuit under test via the relay matrix module, and after a specified time (e.g. 20ms) has elapsed, the audio signal is sent to the analog semiconductor integrated circuit under test via the relay matrix module. The DC output signal (current or voltage) of a given pin of the circuit is measured by the DC voltage measurement module, and at the same time, the audio output signal of the given pin of the analog semiconductor integrated circuit under test is measured by the audio signal measurement module via the relay matrix module. It will be measured by . Note that FIG. 5 shows the specific content of the test operation executed by each CPU 6 based on the single number added from the CPU 5, and does not show each single number shown in FIG. 4. .

In FIG. 5, (A) is a specific example of an instruction output from the CPU 5. That is, prior to test execution, the CPU 5 downloads to each CPU 6 an execution table corresponding to the above-mentioned steps specific to the analog semiconductor integrated circuit to be tested. The execution table downloaded in this way is specific to the analog semiconductor integrated circuit under test, and
There is no need to change it unless the type changes.
When running a test after downloading,
CPU5 sends only a single number to each CPU6.

According to the single number sent out from CPU5,
For example, the first CPU 6 executes processes related to the control of the relay matrix module as shown in (B), and the second CPU 6 executes processes related to the control of the DC voltage generation module as shown in (C). The third CPU 6 executes processing related to the control of the audio signal generation module as shown in (D), and the fourth CPU 6 controls the DC signal measurement module as shown in (E). The fifth CPU 6 executes processing related to the control of the audio signal measurement module as shown in (F). Then, the CPU 5 determines the quality of the analog semiconductor integrated circuit under test based on the measurement results of each measurement module, and ends one test in the series of tests.

In other words, five CPUs 6 from the first to the fifth simultaneously execute different processing operations in one test according to the single number sent out from the CPU 5, and the CPU 5 judges the measurement result at the end. Finish one of the tests.

In addition, in the actual quality test of the analog semiconductor integrated circuit under test, a test similar to the above is carried out over, for example, several hundred items according to a single number that is sequentially added from a procedure table stored in the CPU 5. and evaluate the results comprehensively to determine pass/fail.

Next, a specific example of performing multiple tests simultaneously using different numbers will be described. In this case, for example, the first
CPU5 is the first according to the audio band test.
Run the program to get the first single number on the CPU
The analog semiconductor integrated circuit to be tested is tested for the audio band by sending it to the six groups, accessing a plurality of CPUs 6 and operating the necessary test modules MDL. During this audio band test execution, the second CPU 5 executes a program corresponding to, for example, a DC test, and selects a second single number different from the first single number that is not accessed by the first single number. Send it to the remaining 6 CPU groups.

As a result, the necessary CPUs 6 among the remaining plurality of CPUs 6 are accessed to operate the necessary test modules MDL, and a DC test is performed on the analog semiconductor integrated circuit to be tested.

Note that the CPU 5 proceeds with the test while selecting CPUs 6 that are capable of executing the test based on the execution procedure table and label table shown in FIG. do.

According to such a configuration, each CPU is
All you have to do is change the content downloaded to 6.
When testing the same type of semiconductor integrated circuit continuously, it is only necessary to sequentially give each CPU 6 a single number from the procedure table stored in the CPU 5, so that the test execution time can be significantly reduced.

Furthermore, when changing the system, only the necessary parts need to be changed, making the system configuration more flexible than before.

For example, if you want to add a new signal generator and signal measurement device for the intermediate frequency band, which has a higher frequency than the audio band, you will need to add a CPU6 and a test module that have a test function for the intermediate frequency band to the existing test system. Just add it. When executing a test, it is sufficient to operate each test module in parallel according to a single number as described above, but the test execution time becomes longer due to the addition of the test function in the intermediate frequency band. There isn't.

In contrast, with conventional LSI test systems that consist of a single processor, similar system changes can be handled by modifying and recompiling the system program, but testing in the intermediate frequency band At least branch instructions are inserted into existing system programs that do not have any functions, so it is unavoidable that the test execution time increases accordingly.

In the above embodiment, an example of a system for testing an analog semiconductor integrated circuit has been described, but it goes without saying that the system can also be applied to testing various semiconductor integrated circuits.

<Effects of the Invention> As explained above, according to the present invention, it is possible to realize a semiconductor integrated circuit test system that has flexibility in system configuration and can significantly shorten test execution time, thereby significantly improving test efficiency. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a system diagram showing an example of downloading in the present invention, Fig. 3 is a conceptual diagram of an execution procedure table stored in the CPU 5, Fig. 4 is a conceptual diagram of an execution table stored in each CPU 6, and Fig. 5 1 is a timing chart showing the operation example of FIG. 1, FIG. 6 is a block diagram showing an example of a conventional device, and FIG. 7 is a timing chart showing the operation example of FIG. 6. CPU1...first processor, CPU2...second processor, CPU3...third processor,
CPU4...Fourth processor, CPU5...Fifth processor
CPU6...6th processor (lower processor), MDL...test module.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit test system configured to test a semiconductor integrated circuit under test using a plurality of test modules having predetermined test functions, a function for managing the operation of the entire system. , an upper processor having the function of managing all test programs possible in the system, an intermediate processor CPU5 controlled according to the upper processor, and a bus connected in parallel to the intermediate processor CPU5,
It consists of a plurality of lower processor CPUs 6 which have the function of controlling test modules according to the upper processor and middle processor CPU 5 to execute a test on the semiconductor integrated circuit under test, and executes a predetermined test on the semiconductor integrated circuit under test. After the necessary programs are read all at once from the memory of the upper processor, these read programs are transferred to the upper processor as the program number and specification information of the middle processor CPU5, and to the middle processor CPU5 as the program. Logic and execution procedure table, specifying the same single number and the execution contents of the tests that are configured consecutively to that number in order to simultaneously execute different types of tests in parallel for multiple lower processor CPUs 6 Each execution table is divided and downloaded, and when executing the test, the upper processor sends a command to the middle processor CPU5 that stores the program logic to be started, and the middle processor CPU5 reads the execution procedure table. The program logic is executed according to the commands from the upper processor while referring to the
A semiconductor integrated circuit test system characterized in that a CPU 6 searches an execution table in accordance with a single number consisting of a plurality of bits added from an intermediate processor CPU 5, and simultaneously drives predetermined test modules in parallel. 2. In a semiconductor integrated circuit test system configured to test a semiconductor integrated circuit under test using a plurality of test modules having predetermined test functions, the function to manage the operation of the entire system and the tests possible with the system. a high-level processor having the function of managing all programs of the high-level processor; a plurality of medium-level processors CPU5 connected in parallel to the high-level processor via a bus and controlled according to the high-level processor; Upper processor and each middle processor CPU
The CPU 6 comprises a plurality of lower processor CPUs 6 having the function of controlling the test module to execute a test on the semiconductor integrated circuit under test according to 5. are read all at once from the memory of the upper processor, these read programs are stored in the upper processor as the program number and specification information for the middle processor CPU5, and in the middle processor CPU5 as the program logic and execution procedure table. In order to simultaneously execute different types of tests in parallel, each of the plurality of lower processor CPUs 6 is divided into execution tables that specify the same single number and the execution contents of the tests that are arranged consecutively to that number. When executing the test, the upper processor identifies the middle processor CPU 5 that stores the program logic to be started and sends a command.
The middle processor CPU5 executes program logic according to commands from the upper processor while referring to the execution procedure table, and each lower processor CPU6 executes according to a single number made up of multiple bits added from the middle processor CPU5. A semiconductor integrated circuit test system characterized by searching a table and driving predetermined test modules simultaneously in parallel.