JPH0564367B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus configuration circuit for a data processing device.

(Prior Art) Conventionally, the bus circuit of this type of data processing device is
As shown in FIG. 2, each functional block 11 to 16 has bidirectional elements 110, 120, 130,
40, 150, and 160, and all functional blocks were connected to signal line 1. According to this configuration, when data is transferred from the functional block 11 to the functional block 16, the output side gate 111 of the bidirectional element 110 inside the functional block 11 is transferred.
opens, data is output to signal line 1, and at the same time all bidirectional elements 1 of other functional blocks are
20, 130, 140, 150, 160 input side gates 122, 132, 142, 152, 162
is opened, and data on signal line 1 can be input.

That is, in the prior art, if N function blocks were connected to signal line 1, (N-1) function blocks were in a state in which input was possible and one function block was in a state in which output was possible. .

(Problems to be Solved by the Invention) In the bus circuit of the data processing device according to the prior art described above, the bus data is propagated even to functional blocks that do not need to be inputted with the bus data, and the load thereof becomes a cause of the problem. The disadvantage is that the stabilization of input data for equipment blocks that require data input from the bus is delayed.

Therefore, there is a drawback that it is difficult to improve the data transfer capability between functional blocks that frequently use the bus.

The object of the present invention is to provide output data to (N-1) function blocks out of N function blocks (N: a positive integer) to its own bus or from other function blocks. In addition to selecting whether to output data to the bus, for the remaining one function block, select whether to output data to the bus of this function block itself, or output data from two other function blocks to the bus. The bus circuit of the data processing device is designed to eliminate the above disadvantages and to have a large loop that connects all N functional blocks and a loop that connects the functional blocks that frequently use the bus. It is about providing.

(Means for Solving the Problems) The bus circuit of the data processing device according to the present invention is composed of N (positive integer) functional blocks forming a loop, and is composed of (N-1) functional blocks. Each functional block is equipped with a first type of selection circuit that selects between the output data of its own functional block to the bus and the output data of another functional block to the bus. The function block can choose between output data to its own bus or output data to the bus from two other function blocks.
This is equipped with a second type of selection circuit that selects by.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bus circuit of a data processing device according to the present invention, and shows an embodiment of the bus circuit inside the data processing device composed of six functional blocks 21 to 26. FIG.

FIG. 1 shows selection circuits 31 to 3 for selecting output data to the bus from the function block itself or output data to the bus from another function block.
The output signal lines 41-46 are connected to the selection circuits 31-36, respectively. In addition, the signal line 41
-46, the functional blocks 21-26 constitute a large loop, and the output signal lines 41-43 constitute the functional blocks 21-23, a small loop.

In FIG. 1, when data is transferred from function block 21 to function block 26, the data is transferred via a large loop. Function block 2
In response to a data output command to the bus, the selection circuit 31 selects the bus output data of the functional block itself and outputs it to the signal line 41. At the same time, the selection circuit 34 of the functional block 24 outputs the data on the signal line 41 to the signal line 44, the selection circuit 35 of the functional block 25 outputs the data on the signal line 44 to the signal line 45, and the selection circuit 34 of the functional block 26 outputs the data on the signal line 44 to the signal line 45. 36 is signal line 4
5 is output to the signal line 46. At the same time, the selection circuit 33 of the functional block 23 outputs the data on the signal line 46 to the signal line 43, and the selection circuit 32 of the functional block 22 outputs the data on the signal line 43 to the signal line 42.
Output to.

In this way, data output from functional block 21 propagates through signal lines 41-46. Each of the functional blocks 21-26 has the output signal lines 41-46 of the selection circuits 31-36 provided therein internally as bus inputs, so that it is possible to input data within the large loop. When the function block 26 inputs data on the signal line 46 in response to a data input command from the bus, the function blocks 21,
The data transfer between 26 and 26 is completed.

When data is transferred between the functional blocks 22 and 23, the data is transferred via a small loop. The circuit 32 selects output data of the function block 22 to its own bus in response to a data output command to the bus.
is selected and data is output from the function block 22 to the signal line 42, the selection circuit 31 of the function block 21 outputs the data on the signal line 42 to the signal line 41, and the selection circuit 33 of the function block 23 outputs the data on the signal line 42. 4
1 is output to the signal line 43.

At this point, the data output from the function block 22 is propagating through the signal lines 41 to 43 that make up the small loop, so the function block 23 inputs the data on the signal line 43 in response to the data input command from the bus. Then, the data transfer between the functional blocks 22 and 23 is completed. The selection circuits 34 to 36 inside the functional blocks 24 to 26 are connected to the signal lines 41 and 41, respectively.
44 and 45 are output to signal lines 44-46. However, since the selection circuit 33 inside the functional block 23 does not select the signal line 46, no large loop is formed.

In FIG. 1, data transfer between functional blocks connected by a small loop is performed using part of the data transfer route between functional blocks connected by a large loop, and the time required for the transfer is short.

In this embodiment, the small loop includes only functional blocks that require high-speed performance, and data can be transferred between functional blocks within the small loop in one clock cycle. All other functional blocks that do not require much performance are placed in the large loop, so that data can be transferred between the small loop and the large loop and between each functional block within the large loop in two clock cycles. By doing this, in the case of FIG. 1, function blocks that frequently use the bus are assigned to function blocks 21 to 23, and function blocks that use the bus less frequently are assigned to function blocks 24 to 26. Allocation increases the overall ability to transfer data between functional blocks.

(Effects of the Invention) As explained above, the present invention has a selection circuit inside each functional block that selects whether to output data to the bus of each functional block itself or to output data to the bus from another functional block. The functional blocks are divided into groups that frequently require data transfer via the bus and groups that do not, and are connected to form small loops and large loops corresponding to each group. This has the effect of improving the overall data transfer capability between functional blocks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a bus circuit of a data processing device according to the present invention. FIG. 2 is a block diagram showing an example of a bus circuit of a data processing device according to the prior art. 11-16, 21-26...Function block, 1
10, 120, 130, 140, 150, 16
0, ... bidirectional element, 111, 112, 12
1,122,131,132,141,142,
151, 152, 161, 162...gate, 3
1-36...selection circuit, 1...bus, 41-46
……Signal line.

Claims (1)

[Scope of Claims] 1. A bus circuit of a data processing device composed of N (positive integer) functional blocks forming a loop, which outputs data to the bus of its own functional blocks, or
or (N-1) functional blocks provided with a first type selection circuit for selecting one of the two to select the output data from another functional block to the bus; and one functional block equipped with a second type of selection circuit for selecting one of three options: output data to the bus, or output data from the other two functional blocks to the bus. The loop has a large loop and a small loop,
A bus circuit for a data processing device, characterized in that the large loop is configured to branch from the small loop and return to the small loop via all remaining functional blocks.