JPH0564499B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transmission circuit for a device failure signal of a transmitting side interface conversion circuit in wireless digital transmission.

BACKGROUND ART Conventionally, in a wireless digital transmission system, when a device failure occurs in an interface conversion circuit on the transmitting side, a method of transmitting the device failure to the receiving side is to stop sending frame synchronization signals on the transmitting side and A method was adopted in which failures were communicated by detecting frame synchronization.

FIG. 2 is a diagram showing an example of the block configuration of a conventional equipment failure signal transmission circuit of this type. In FIG. 2, modulation/demodulation and transmission/reception functions are omitted.

The device interface input signal 1 is sent to the sending end interface conversion circuit 101 and the fault detection circuit 10.
2 is input. The sending-end interface conversion circuit 101 is a circuit for converting an interface code format into an NRZ (Non Return to Zero) signal that can be processed by the sending-end synchronous conversion circuit 103 and the sending-end multiplex conversion circuit 104.

On the other hand, the fault detection circuit 102 is a circuit for detecting a fault in the sending-end interface conversion circuit 101, and detects the input signal 1, the output signal 2 of the conversion circuit 101, and the monitor signal 3 inside the sending-end interface conversion circuit 101. is being entered. The sending end synchronous conversion circuit 103 performs synchronous conversion in order to multiplex an auxiliary signal etc. with the output signal 2 of the sending end interface conversion circuit 101 at the previous stage. Synchronous conversion is accomplished by conventionally well-known pulse stuffing or speed conversion techniques. The signal 5 subjected to synchronous conversion is guided to the sending end multiplex conversion circuit 104, where it is multiplexed with the auxiliary signal 7 and the frame synchronization signal for position determination for multiplexing, and output as a multiplexed signal 6.

On the other hand, on the receiving end side, the multiplexed signal 6 is input to a receiving end separation conversion circuit 106 and a frame synchronization circuit 105. The receiving end separation and conversion circuit 106 is a circuit that separates the multiplexed signal 6 multiplexed on the sending end side and outputs an auxiliary signal 13 and an output signal 9.

The frame synchronization circuit 105 establishes frame synchronization for detecting, on the receiving end side, the signal position required for multiplex conversion on the sending end side, and sends out a control signal 12 for controlling the receiving end separation/conversion circuit 106. The receiving end synchronization conversion circuit 107 is a circuit for inputting the output signal 9 of the receiving end separation conversion circuit 106 in the preceding stage and smoothing the signal 9 having a phase gap. Next, the receiving end interface conversion circuit 108 converts the previous stage output signal 10
This is a circuit that inputs the signal and outputs the device interface output signal 11.

In the above circuit configuration, if the output of the sending-end interface conversion circuit 101 is cut off, in particular, a fault accompanied by a cut-off of the clock signal, or an internal logic fault, although the output signal and clock signal are present, the content of the transmitted signal becomes a fault. If the fault detection signal 4 occurs in this case, this fault detection signal 4 controls the sending end multiplex conversion circuit 104 and prohibits multiplexing of the frame synchronization signals generated within this multiplex conversion circuit,
A multiplexed signal 6 without multiplexing the frame synchronization signal is sent to the receiving end.

On the other hand, on the receiving end side, the multiplexed signal 6 is input to the frame synchronization circuit 105 to establish frame synchronization, but because the sending end side prohibits the insertion of frame synchronization signals, frame synchronization is not established, and frame synchronization circuit 1
A frame out-of-sync signal 8 is output from 05. That is, failure of frame synchronization to be established is used to detect equipment failure on the sending end.

Problems to be Solved by the Invention However, since the above conventional method utilizes frame synchronization, equipment failures unrelated to DSC (Digital Service Channel) signal transmission on the transmitting side, such as Even if there is a failure in the sending end interface conversion circuit, there is a drawback that auxiliary signals such as DSC signals cannot be transmitted.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology. Therefore, an object of the present invention is to
It is an object of the present invention to provide a new fault transmission method that does not cause disturbances to auxiliary signals such as signals.

Means for Solving the Problems According to the present invention, in a device fault signal transmission method when a device fault occurs in the sending end interface conversion circuit of a digital conversion circuit, a fault in the sending end interface conversion circuit is detected. a failure detection circuit; and an OR circuit or an AND circuit that fixes an output signal of a sending-end synchronous conversion circuit sub-connected to the sending-end interface conversion circuit to a constant logical value based on the output signal of the failure detection circuit. and a pulse break detection circuit that detects a signal whose logical value is a constant logical value on the receiving end side at the output of the receiving end synchronous conversion circuit.

The present invention is characterized in that, as a means for transmitting a fault in the sending end interface conversion circuit device on the transmitting side to the receiving side, the fault is transmitted to the receiving side in the form of a pulse break without losing frame synchronization. For this purpose,
Frame synchronization in the radio section remains established at all times, and a device failure signal transmission method that does not affect the transmission of auxiliary signals such as DSC signals can be obtained.

Embodiment of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. 2 described as prior art indicate the same elements as in FIG.

Comparing one embodiment of the present invention with the configuration shown in FIG. A fault is detected when an output signal exists but the transmission signal content becomes a fault, and the fault detection signal 4 and the sending end synchronous conversion circuit 1 are used as means for transmitting this device fault.
A logical sum (or AND) circuit 111 with the output signal 5 of 03 is provided, and a pulse break detection circuit 112 is used as a means for detecting this equipment failure signal.
The feature is that it is installed at the output end of 07.

When a fault similar to that explained with reference to FIG. If an AND circuit is used instead of the circuit, the fault detection signal will be a logic value fixed to "0" at the time of a fault). The output signal 5' of this OR circuit 111 becomes a signal with a constant logical value. This is the sending end multiple conversion circuit 1 in the subsequent stage.
Lead to 04. At this time, an OR or AND circuit was used, but since the sending end synchronous conversion circuit 103 is composed of a generally well-known memory circuit,
Even if this control is performed by setting or clearing the memory circuit, the effect remains the same. That is, the output signal 5 itself of the sending end synchronous conversion circuit 103 can be set to a constant logical value. Then, the sending end multiple conversion circuit 10
In step 4, the auxiliary signal 7, the frame synchronization signal, and the output signal 5' having a constant logical value, which is the output of the previous stage, are multiplexed and converted and sent out as a multiplexed signal 6.

On the receiving end side, the multiplexed signal 6 is sent to the receiving end separation conversion circuit 1.
06 and frame synchronization circuit 105 to establish frame synchronization. Next, the receiving end separation conversion circuit 1
At step 06, the auxiliary signal 13 and the output signal 9 are separated, and the output signal 9 is output to the receiving end synchronization conversion circuit 107 at the subsequent stage. The receiving end synchronization conversion circuit 107 is a circuit for smoothing the output signal 9 having a phase cap. Since the output signal 10 of this circuit is a signal with a constant logical value, the pulse break detection circuit 112 outputs the pulse break signal 14. Using this pulse interruption detection, equipment failure on the sending end side can be detected.
Furthermore, since frame synchronization has been established at this time, it is also possible to transmit auxiliary signals.

Effects of the Invention As explained above, the present invention provides synchronous multiplexing of signals with a constant logical value at the sending end regarding the transmission of equipment failure signals when equipment fails in the sending end interface conversion circuit unrelated to auxiliary signal transmission. I am planning to convert and transmit it. Therefore, according to the present invention, it is possible to transmit an equipment failure in the interface conversion circuit on the sending end to the receiving end while enabling auxiliary signal transmission without losing the frame synchronization of the wireless digital transmission system. is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device failure signal transmission circuit in wireless digital transmission according to the present invention, and FIG. 2 is a block diagram of conventional wireless digital transmission. 101... Sending end interface conversion circuit, 1
02... Failure detection circuit, 103... Sending end synchronous conversion circuit, 104... Sending end multiplex conversion circuit, 105...
Frame synchronization circuit, 106... Receiving end separation conversion circuit, 107... Receiving end synchronization conversion circuit, 108... Receiving end interface conversion circuit, 111... OR circuit, 112... Pulse disconnection detection circuit.

Claims (1)

[Scope of Claims] 1. A sending-end interface conversion circuit that converts an input signal into an NRZ signal, a sending-end synchronous conversion circuit that synchronously converts this NRZ signal, and an auxiliary signal and a frame synchronization circuit for the output of this sending-end synchronous conversion circuit. A device failure device comprising: a sending-end multiplex conversion circuit that inserts a signal and outputs a multiplexed signal; and a failure detection circuit that detects a failure in the sending-end interface conversion circuit based on the input signal and the NRZ signal. In the signal transmission system, when the fault detection circuit detects a fault, the output of the sending-end synchronous conversion circuit is fixed to a constant logical value and supplied to the sending-end multiplex conversion circuit; otherwise, the output of the sending-end synchronous conversion circuit is An equipment failure signal transmission system, characterized in that a logic circuit is provided for supplying a conversion circuit output to the sending end multiplex conversion circuit.