JPH056548A - Information signal reproducing device - Google Patents

Abstract

(57) [Abstract] [Purpose] A PLL circuit that receives a pit detection signal as an input to extract a synchronization signal, and the response operation of the PLL circuit is stable even when the input pit detection signal whose period changes. To be able to do. A synchronization signal D is reproduced by receiving an input signal C such as a pit detection signal by a PLL circuit 25, and a synchronization signal D obtained by the PLL circuit 25,
The information signal is reproduced by the data discriminating circuit 26 to which the input signal C is applied. The output from the comparison cycle detection circuit 27, which generates an output according to the cycle of the input signal C and the synchronization signal D, is applied to the phase error correction circuit 28, and the PLL circuit 2
5 to correct the phase of the phase error output from the phase comparator 22. Therefore, the phase error output provided from the phase comparator 22 of the PLL circuit 25 is corrected to the phase error at the time of comparison at the shortest comparison period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal reproducing apparatus, for example, an information signal reproducing apparatus for reproducing read data from a pit detection signal obtained from a recording medium on which information is recorded by optical means. Regarding the device.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a recording medium on which information is recorded by optical means. That is, reference numeral 1 indicates a recording medium, and an information track 1a is formed on the recording medium 1. In the information track 1a, concave or convex pits B are continuously formed along the track 1a. In this example, recording data A composed of a combination array of "1" and "0" is MFM modulation (Modi
fied Frequency Modulatio
n) shows the state of recording.

FIG. 3 is a block diagram showing an example of a conventional information signal reproducing apparatus for detecting the recording pit B of the recording medium 1 shown in FIG. 2 and generating read data from the pit detection signal. is there. In FIG. 3, reference numeral 21 is an input end of a pit detection signal C obtained by detecting the recording pit B of the recording medium 1. The input signal applied to the input end 21, that is, the pit detection signal C is phase-compared. Is applied to one input end of the device 22. A synchronization signal D is applied to the other input terminal of the phase comparator 22, and the phase comparator 22 produces a phase error output F corresponding to the phase difference between the pit detection signal C and the synchronization signal D. .. The phase error output F obtained by the phase comparator 22 is applied to the low-pass filter 23, and the low-pass filter 23 removes the harmonic component contained in the phase error output.

The output G from the low-pass filter 23 from which harmonic components have been removed is applied to a voltage controlled oscillator (VCO) 24 whose oscillation frequency is variable according to the input voltage, and a synchronizing signal D is generated. The output of the VCO 24 is fed back to the other input terminal of the phase comparator 21 to form a PLL circuit 25. As a result, V
The synchronization signal D provided by the CO 24 is synchronized with the basic cycle of the pit detection signal C.

On the other hand, the synchronizing signal D obtained by the VCO 24 is applied to one input end of the data discriminating circuit 26, and the pit detection signal C is applied to the other input end of the data discriminating circuit 26. .. The data discriminating circuit 26 uses the synchronizing signal D as a detection window signal and reproduces read data of "1" or "0" depending on the AND condition of the detection window signal and the pit detection signal C.

FIG. 4 is a waveform diagram for explaining the operation of the information signal reproducing apparatus shown in FIG. That is, (A) in the drawing shows the original recording data recorded on the recording medium 1, and (B) shows the arrangement pattern of the recording pits recorded on the recording medium 1 by MFM modulation.

Further, (C) shows a pit detection signal reproduced from the recording pit, and (D) shows a synchronization signal which is obtained by the PLL circuit 25 and which is synchronized with the basic cycle of the pit detection signal (C). Is shown. As described above, the pit detection signal C and the synchronizing signal D are applied to the data discriminating circuit 26, and the data discriminating circuit 26 uses the synchronizing signal D as a detection window signal, and the detection window signal and the pit detection signal C are ANDed. Depending on the condition, the read data of "1" or "0" is reproduced as shown in (E).

[0008]

By the way, the above-mentioned M
The FM modulation has an algorithm that inverts at the center of data "1" and inverts at the boundary of data "0". Therefore, in the case of the MFM modulation illustrated, pits have data intervals "1T", "1". It will exist at .5T "and" 2T ". Therefore, the phase comparison between the pit detection signal and the synchronization signal in the conventional PLL circuit has to be performed discretely.

Now, let us consider a case where the low-pass filter 23 has an integral element and a proportional element, and the gains are ½. Further, in order to make the description easy to understand, the signal will be described digitally with the number of pulses as a unit. For example, 1
A signal of 0 KHz is 100 when the fundamental frequency is 1 MHz.
The pulses will be counted.

[1T = 110] of the pit detection signal
Then, when the 1T signal is input as the input signal with 1T = 100 of the VCO 24 and the case where the 2T signal is input as the input signal are compared, the results are as shown in Tables 1 and 2. (Note that the numerical values of the calculation results shown in Table 1 and Table 2 are displayed with the decimal places truncated.)

That is, in Tables 1 and 2, the input phase C shows the phase of the input signal C in FIG. 3, the output phase D shows the phase of the output signal D of the VCO 24 in the same figure, and the phase difference F shows in the figure. The output F of the phase error signal obtained by the phase comparator 22 is shown, and the manipulated variable G is the output G of the low-pass filter 23 shown in FIG.

[Table 1]

[Table 2]

FIG. 5 is a graph showing a comparison of output frequencies based on the calculation results shown in Tables 1 and 2. In the graph shown in FIG.
The vertical axis represents the output frequency, and the horizontal axis represents the number of PLL comparisons.

As shown in FIG. 5, the result when the 1T signal is input is shown by the broken line (a), and the result when the 2T signal is input is shown by the broken line (b). )
Can be said to be a substantially ideal response characteristic of the PLL circuit. However, it is hard to say that the broken line (b) is a stable response characteristic of the PLL circuit.

As described above, for the pit detection signal by MFM modulation, when the shortest period is "1T", the comparison period in the phase comparator of the PLL circuit is "1".
Since T "," 1.5T ", and" 2T "are present at random, and the phase error output at the time of comparison is used to form the PLL circuit, the cycle of the pit detection signal is as described above. As described above, there is a problem in that the response of the PLL circuit changes when they are different, and a stable response characteristic of the PLL circuit cannot always be obtained.

The present invention has been made in view of the above points, and detects the period of phase comparison and corrects the phase error output at the time of comparison to the phase error output in the shortest comparison period. By doing so, it is an object to provide an information signal reproducing device which can always obtain a stable PLL circuit response.

[0016]

In the information signal reproducing apparatus of the present invention made to achieve the above object, an input signal is applied to one input terminal and a synchronizing signal is applied to the other input terminal. , A phase comparator that generates a phase error output according to the phase difference between the input signal and the synchronization signal, a phase error output that is output from the phase comparator as an input, a low-pass filter that removes harmonic components from the phase error output, The output of the low-pass filter is input, and a voltage-controlled oscillator that generates a synchronization signal according to the output is provided, and the synchronization signal output from the voltage-controlled oscillator is fed back to the other input terminal of the phase comparator. An information signal reproducing apparatus configured to reproduce an information signal by using a configured PLL circuit, a synchronization signal obtained by the PLL circuit, and an input signal, wherein the cycle of the input signal and the synchronization signal is And a phase error correction circuit for correcting the phase of the phase error output generated by the phase comparator by the output provided by the comparison cycle detection circuit. ..

[0017]

In the information signal reproducing apparatus having the above-described structure, the phase error output output from the phase comparator of the PLL circuit is generated by the output from the comparison cycle detecting circuit that produces an output according to the cycle of the input signal and the synchronizing signal. Since the phase error output from the phase comparator of the PLL circuit is corrected to the phase error at the shortest comparison period, the phase error output from the phase comparator of the PLL circuit is always corrected to a stable P value.
The response characteristic of the LL circuit is obtained.

[0018]

The present invention will be described below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment according to the present invention. In FIG. 1, the parts denoted by the same reference numerals as those of FIG. 3 already described indicate the same target parts, and therefore detailed description thereof will be omitted.

In FIG. 3, reference numeral 27 denotes a comparison cycle detecting circuit having one input end connected to the input end 21 of the pit detection signal C and the other input end connected to the input end of the synchronizing signal D supplied from the VCO 24. Is. Then, the pit detection signal C and the synchronization signal D by the comparison cycle detection circuit 27.
The output corresponding to the cycle of and is the output terminal of the phase comparator 22,
The phase error correction circuit 28 connected between the low-pass filter 23 and the low-pass filter 23 is configured to be applied as a phase error correction control signal for correcting the phase of the phase error output. Then, the phase error output F ′ whose phase has been corrected by the phase error correction circuit 28 is applied to the low-pass filter 23.

In the above structure, the synchronization signal D is applied from the VCO 24 to the comparison cycle detection circuit 27, and this synchronization signal D is used as a detection window signal for the pit detection signal C. Therefore, the comparison cycle detection circuit 2
In FIG. 7, it is possible to detect the cycle (“1T”, “1.5T”, “2T”) of the pit detection signal C input every moment.

When the comparison cycle detection circuit 27 determines that the cycle is "1T", the phase comparator 2
The phase error output F provided by 2 is directly output to the output end of the phase error correction circuit 28 (F '= F).

When the comparison cycle detection circuit 27 determines that the cycle is "2T", the comparison time is doubled even if the frequency shift is the same, so the phase difference obtained by integrating the frequency difference is used. Is twice as large as that in the case of “1T”. Therefore, the phase error correction circuit 28 corrects the phase error, halves the phase error of the input signal, that is, the phase error output F, and outputs it to the output end of the phase error correction circuit 28 (F ′ = 1/2 · F). ).

Further, when the comparison cycle detecting circuit 27 determines that the cycle is "1.5T", the phase error correcting circuit 28 corrects the phase error, and the phase error of the input signal, that is, the phase error output F is set to 1 /1.5 and output to the output end of the phase error correction circuit 28 (F '= 1 /
1.5 ・ F).

As described above, the phase error output F'corrected in phase by the phase error correction circuit 28 locks the phase of the PLL circuit. As a result, similar to the cases shown in Tables 1 and 2, the following table shows the relationship among the input phase C, the output phase D, the phase error F, the corrected phase error F ′, the manipulated variable G, the output frequency, and the like. The results are shown in Fig. 3 (note that the numerical values of the calculation results shown in Table 3 are truncated and displayed).

[Table 3]

As shown in Table 3, according to the information signal reproducing apparatus of the present invention, it is possible to obtain the same characteristic as the response characteristic of the PLL circuit in Table 1 described above, and to obtain a signal in which the cycle of the input signal is discrete. On the other hand, it is possible to always obtain stable response characteristics of the PLL circuit.

[0026]

As is apparent from the above description, according to the information signal reproducing apparatus of the present invention, the PLL circuit receives the input signal such as the pit detection signal and reproduces the synchronizing signal. In an information signal reproducing device adapted to reproduce an information signal by a synchronizing signal obtained by a PLL circuit and an input signal, an output from a comparison cycle detecting circuit for producing an output according to the cycle of the input signal and the synchronizing signal. , The phase error output from the phase comparator of the PLL circuit is corrected.

Therefore, the phase error output provided from the phase comparator of the PLL circuit is corrected to the phase error at the shortest comparison period, and the result is that the response characteristic of the PLL circuit is always stable. Can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an information signal reproducing apparatus of the present invention.

FIG. 2 is a configuration diagram showing a state of a pit signal recorded on a recording medium.

FIG. 3 is a block diagram showing an example of a conventional information signal reproducing device.

FIG. 4 is a signal waveform diagram for explaining the operation of the conventional example shown in FIG.

FIG. 5 is a characteristic diagram for explaining a response action in the conventional example shown in FIG.

[Explanation of symbols]

 21 Input Terminal 22 Phase Comparator 23 Low Pass Filter 24 Voltage Controlled Oscillator 25 PLL Circuit 26 Data Discrimination Circuit 27 Comparison Cycle Detection Circuit 28 Phase Error Correction Circuit

Claims (1)

Claim: What is claimed is: 1. A phase error output according to a phase difference between the input signal and the synchronization signal, wherein an input signal is applied to one input end and a synchronization signal is applied to the other input end. , A phase comparator for generating a phase error output from the phase comparator as an input, a low-pass filter for removing a harmonic component from the phase error output, and an output of the low-pass filter as an input, and synchronizing according to the output. And a voltage controlled oscillator that generates a signal, and a PLL circuit configured to feed back a synchronization signal output from the voltage controlled oscillator to the other input end of the phase comparator, and a PLL circuit. An information signal reproducing device adapted to reproduce an information signal by means of a synchronizing signal and the input signal, wherein the information signal reproducing device produces an output according to the cycle of the input signal and the synchronizing signal. Period detecting circuit and the comparator period detection circuit information signal reproducing apparatus being characterized in that further comprising a phase error correction circuit by an output brought to correct the phase error output of the phase generated by the phase comparator from.