JPH056672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a testing device for integrated circuits, and more particularly to a testing device for logic type integrated circuits.

(Prior art) The test time required for testing a logic type integrated circuit depends on the running time of the test pattern that should actually be applied to the integrated circuit under test and the test conditions for each test (for example, voltage conditions, timing conditions, etc.) ), and the time required to control the process and flow of tests depending on whether each test is good or bad. Generally, the time other than the running time of the test pattern described above is called overhead time, and it is said that the shorter the overhead time, the better the test equipment.
In addition, in order to maximize the processing power of the test equipment during mass production, in order to minimize this time, the test program for quantity calculation is completed when creating the program to operate the test equipment. Various efforts have been made to achieve this goal.

However, in reality, we cannot ignore the fact that it is a program that is easy for anyone to understand and that is easy to deal with problems during mass production, so it is not necessarily the program that has the highest mass production effect as mentioned above. There are many things that are not done. However, of course, such a program also has certain effects from another perspective. One of the reasons for this is that it is not easy to count the overhead time of a test program.

In other words, to count the overhead time in conventional integrated circuit test equipment, for example, the number of test executions is set multiple times, the loop is performed, and the waveform of each test pattern signal is observed, and the total test time is calculated based on the observation. was calculated by subtracting.

(Problems to be Solved by the Invention) The time counting method in the conventional integrated circuit testing equipment described above requires time for observation, requires a measuring instrument, etc. There were problems such as low accuracy.

An object of the present invention is to provide an integrated circuit testing device that eliminates such problems.

(Means for Solving the Problems) The integrated circuit testing apparatus of the present invention includes a test pattern to be applied to the integrated circuit under test, a pattern generating section that generates a pattern end signal at the end of this test pattern, and a test start. a control unit that receives the signal and the pattern end signal and sends a pattern start signal to the pattern generator according to a prestored program to start the test pattern and generate a test end signal when the test ends; and the test start signal. a timer that interrupts counting of the clock at , restarts counting of the clock at the pattern start signal, restarts counting of time at the pattern end signal, and stops counting time at the test end signal. be done.

(Example) Hereinafter, an integrated circuit testing apparatus of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the integrated circuit testing apparatus of the present invention, and FIG. 2 is a timing chart showing this operation.

Execution of the test on the integrated circuit under test starts from the time when the test start signal a is input to the control unit 1 that controls the operation of the test equipment. Timer 2 starts counting time from this point.

When the control section 1 receives the test start signal a, the central processing unit 3 accesses the storage device 5 in which the corresponding test program 4 is stored, decodes the test program 4, and detects the test command, and then starts the pattern generation section 6. pattern start signal b
is sent to instruct the pattern generating section 6 to start running the test pattern. At the same time, the pattern start signal b is input to the timer 2, and time counting is temporarily interrupted. When the pattern generating section 6 finishes running the pattern of the corresponding test, it sends a pattern end signal c to the control section 1 and the timer 2, and the timer 2 resumes counting the time that was interrupted by this signal. The above operation is repeated every time the central processing unit 3 decodes the test program 4 and detects a test command, but when a test end command is detected, the control unit 1
sends a timer stop signal d to timer 2, and timer 2 stops its counting operation.

In other words, as shown in the timing chart of FIG. 2, when the program 4 to be executed is created by four tests, time t ₀ is the test start point, and time t ₁ , t ₃ , t ₅ , t ₇ is the start of the test pattern running of each test, time t ₂ , t ₄ , t ₆ , t ₈ is the end of the test pattern running of each test, and time t ₉ is the end of the test, then timer 2 is set at time t Start counting time at time ₀ , temporarily stop counting at time t ₁ , restart counting at time t ₂ , stop counting at time t ₃ , and so on until time t ₈ . The counting operation is repeated until time t 9, and the counting operation is completely stopped at the end of the test at time t ₉ .

With the above operation, timer 2 has time points t ₀ to t ₁ ,
This means that the cumulative time from _t2 to _t3 , _t4 to _t5 , _t6 to _t7 , and _t8 to _t9 , that is, the overhead time is counted. The values counted in this manner can be instantly provided to the operator by connecting to a display circuit or central processing unit (not shown).

(Effects of the Invention) As explained above, the integrated circuit testing device according to the present invention has the advantage of being able to instantaneously count the overhead time of the executed test program, and is highly effective in mass production while making various changes to the test program.
Effective in creating optimal test programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an integrated circuit testing apparatus according to the present invention, and FIG. 2 is a timing chart showing its operation. In the figure, 1...Control unit, 2...Timer, 3...Central processing unit, 4...Test program, 5...Storage device, 6...Pattern generator, a...Test start signal, b... Pattern start signal, c...pattern end signal, d...test end signal.

Claims (1)

[Claims] 1. A test pattern to be applied to the integrated circuit under test, a pattern generating section that generates a pattern end signal at the end of this test pattern, and a pattern generating section that receives the test start signal and the pattern end signal and generates the pattern end signal according to a pre-stored program. a control unit that sends a pattern start signal to start the test pattern and generates a test end signal when the test ends; and a control unit that starts counting time with the test start signal and interrupts time measurement with the pattern start signal. and a timer that restarts time counting upon the pattern end signal and stops time counting upon the test end signal.