JPH0566735A - Driving method of liquid crystal display device - Google Patents

Abstract

(57) [Abstract] [Purpose] Multi-level gray scale display is performed without using multi-level voltage level drive signals, and the fluctuation of the transmittance due to the influence of image data applied to other pixels is suppressed. By reducing the number, it is possible to obtain the display of the correct gradation according to the image data. [Structure] Between a drive signal input terminal of an active element 2 composed of a diode and a counter electrode 4, during a selection period TS, a voltage value according to image data and a pulse width or a positive or negative polarity of a pulse number are set. In the non-selection period T0 in which the selection voltage is applied and other pixels are selected, the potential changes in a cycle shorter than the selection period and the non-selection of the scanning signal SS supplied to one of the signal line 3 and the counter electrode 4 is stopped. A voltage having a waveform whose areas on the positive side and the negative side are substantially equal to each other with the selection potential VC2 as the center is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an active matrix liquid crystal display device having a non-linear resistance element as an active element.

[0002]

2. Description of the Related Art As an active matrix liquid crystal display element used in a display device such as a television set or a personal computer, there is one using a non-linear resistance element as an active element.

An active matrix liquid crystal display element using this non-linear resistance element as an active element has pixel electrodes arranged in a row direction and a column direction on one of a pair of transparent substrates facing each other with a liquid crystal layer interposed therebetween. And an active element composed of a non-linear resistance element connected to each of these pixel electrodes, and a signal line for supplying a drive signal to the active element, and a counter electrode facing the pixel electrode is provided on the other substrate. In the liquid crystal display element having the configuration provided, by supplying a scanning signal to one of the signal line and the counter electrode and a data signal to the other, the liquid crystal display device between the pixel electrode and the counter electrode and the liquid crystal between them are provided. The plurality of pixels formed by are sequentially selected and driven in time division.

The non-linear resistance element used as the active element of the active matrix liquid crystal display element is MI
An element of M structure (metal-insulating film-metal laminated structure) (hereinafter,
MIM) and an element having a semiconductor such as a thin film diode, and the active element formed of a thin film diode includes one called a diode ring and one called a back-to-back.

However, in the active matrix liquid crystal display element using the MIM as an active element, the inter-electrode voltage of the pixel (the pixel electrode and the counter electrode with respect to the selection voltage applied between the drive signal input end of the MIM and the counter electrode). It has a problem of poor followability.

That is, in the active matrix liquid crystal display element using the MIM as an active element, a current flows through the MIM in response to a drive signal supplied from a signal line, and the current causes a charge to be accumulated between both electrodes of the pixel, A voltage according to the accumulated charges is applied to the liquid crystal, but the MIM
Has a slow current-voltage characteristic, and a sufficient current does not flow, so that the rate of increase in voltage between both electrodes is slow. Therefore, since the inter-electrode voltage of the pixel cannot be increased within the limited selection period, the inter-electrode voltage of the pixel follows the selection voltage applied between the input terminal of the MIM and the counter electrode. It does not change.

This is because the current flowing through the MIM is a tunnel current based on the tunnel effect, and the element area of the MIM used as an active element of the liquid crystal display element is limited, so that it is difficult to increase the tunnel current. Because.

Therefore, it is necessary to drive the liquid crystal display element using the MIM as an active element at a considerably high voltage (especially, in the case of high time division driving, the selection period becomes short, so that a higher voltage is required. Therefore, power consumption is large, and a drive circuit for generating a high-voltage drive signal is required to have a high breakdown voltage, so that it is difficult to integrate the drive circuit.

Further, since the liquid crystal display element using the MIM as an active element has a slow current-voltage characteristic of the MIM as described above, the selection voltage applied between the input terminal of the active element and the counter electrode. The change width of the voltage between the electrodes of the pixel is small with respect to the change of the pixel voltage. Therefore, in order to perform gradation display in which the degree of brightness of the pixel is changed, it is necessary to change the voltage value of the selection voltage with an extremely large width. The key display was also difficult.

On the other hand, a non-linear resistance element having a semiconductor, for example, an active matrix liquid crystal display element having a thin film diode as an active element, has a current-
Since the voltage characteristic is abrupt, it can be driven at a relatively low voltage, and gradation display is also possible. The gradation display of the active matrix liquid crystal display element is conventionally performed by a driving method called voltage modulation.

This driving method by voltage modulation is a method of controlling the voltage value of the selection voltage according to the image data, and a voltage value according to the image data is input between the input terminal of the active element and the counter electrode during the selection period. When the selection voltage is applied, electric charges are accumulated between both electrodes of the pixel during the selection period, and the voltage between the electrodes rises to a voltage value corresponding to the image data, and the liquid crystal of the pixel responds to the image data according to the image data. A voltage is applied.

[0012]

However, since the above-mentioned conventional driving method controls the voltage value of the selection voltage according to the image data to perform gradation display, the number of display gradations is used as the driving signal. Therefore, there is a problem in that as the number of display gray scales increases, a power supply circuit that outputs voltages of multiple voltage levels is required, which complicates the drive circuit.

Moreover, in the conventional driving method, the voltage accumulated in the pixel during the selection period fluctuates due to the influence of the image data for driving the other pixels in the same column during the non-selection period. There is a problem that the light transmittance of the pixel changes.

This is because the active element has a capacitance, and the active element composed of a non-linear resistance element having a semiconductor such as a thin film diode is much smaller than the capacitance of the MIM described above, but it is conductive. There is a certain amount of capacitance between the bodies (between the upper and lower electrodes in a thin film diode).

Therefore, the pixel and the active element in the active matrix liquid crystal display element have a capacitance (hereinafter, referred to as a pixel) which is formed by the pixel electrode and the counter electrode and the liquid crystal between them when the active element is in the ON state. It is represented by an equivalent circuit in which CLC and an active element are connected in series, and when the active element is turned off, the pixel capacity CLC and the capacity of the active element (hereinafter referred to as element capacity)
It is represented by an equivalent circuit in which CD is connected in series.

Therefore, the inter-electrode voltage VLC of the pixel has a current-voltage characteristic of the active element up to the voltage applied between the input terminal of the active element and the counter electrode during the selection period when the active element is on. And rises in a rising curve according to the charging characteristics of the pixel capacitance CLC, but when the selection period elapses into the non-selection period and the applied voltage drops to the non-selection voltage and the active element is turned off, this active element To act as
The voltage drop (voltage difference between the selection voltage and the non-selection voltage) between the input terminal of the active element and the counter electrode is converted into the pixel capacitance CLC and the element capacitance CD of the active element which are connected in series to each other. The voltage is divided at a ratio opposite to the capacity ratio.

Therefore, the voltage held in the pixel capacitor CLC in the non-selection period is changed from the voltage charged in the selection period to the voltage between the input terminal of the active element and the counter electrode in the non-selection period. Is a value reduced by the partial pressure to the pixel capacitance CLC.

Due to its responsiveness, the liquid crystal between both electrodes of the pixel does not operate at the voltage applied in the extremely short selection period, and the inter-electrode voltage of the pixel (the holding voltage of the pixel capacitance CLC in the non-selection period). ), The effective voltage for operating the liquid crystal becomes low if the inter-electrode voltage VLC drops significantly during the non-selection period.

Therefore, in the above active matrix liquid crystal display element, between the input terminal of the active element and the counter electrode,
The pixel is driven by applying a voltage that allows for the decrease in the inter-electrode voltage of the pixel in the non-selection period. If the selection voltage having such a voltage value is applied, the selection period ends and the non-selection is completed. Since the inter-electrode voltage VLC of the pixel at the time becomes the voltage value according to the image data, the transmittance of the pixel can be set to the gradation according to the image data.

However, the active matrix liquid crystal display element is driven in a time division manner by supplying a scanning signal to one of the signal line and the counter electrode for supplying a driving signal to the active element and a data signal to the other. , The image data for driving other pixels in the same column is applied together with the data signal to the counter electrode of the pixel which has entered the non-selection period after the selection period or has entered the non-selection period. The voltage between the input terminal of the active element of the inside pixel and the counter electrode fluctuates.

When the voltage between the input terminal of the active element and the counter electrode changes in this way, the voltage between the electrodes of the pixel, that is, the holding voltage of the pixel capacitance CLC changes. This change in the holding voltage of the pixel capacitance CLC is similar to the change in the voltage when the selection period is changed to the non-selection period, and the variation amount of the voltage between the input terminal of the active element and the counter electrode is changed to the pixel capacitance CLC and the element. Capacity CD
Of the voltage divided by a ratio opposite to the capacitance ratio with
It is the voltage divided by LC.

Since the liquid crystal between both electrodes of the pixel operates according to the voltage between the electrodes of the pixel (the holding voltage of the pixel capacitance CLC) in the non-selection period as described above, during the non-selection period as described above. When the holding voltage of the pixel capacitance CLC of 1 changes due to the influence of image data for driving other pixels, the transmittance of the pixel changes accordingly, and it becomes impossible to obtain a correct gradation display according to the image data.

The present invention is directed to a method of driving an active matrix liquid crystal display device using an active element composed of a non-linear resistance element having a semiconductor.
It is possible to perform multi-gradation gradation display without using multi-level voltage level drive signals, and reduce the fluctuation of transmittance due to the influence of image data for driving other pixels, It is an object of the present invention to provide a driving method capable of obtaining a display with a correct gradation according to image data.

[0024]

According to the driving method of the present invention, a voltage value and a pulse width or a voltage value according to image data are provided between a drive signal input terminal of an active element and a counter electrode during a selection period. In the non-selection period in which the positive or negative polarity selection voltage of the pulse number is applied and other pixels are selected, the potential changes in a cycle shorter than the selection period and the signal line and the counter electrode It is characterized in that a voltage having a waveform in which the areas on the positive side and the negative side are substantially equal to each other with the potential of the scanning signal supplied to one side in the non-selected period as the center is applied.

In this driving method, for example, one of the signal line and the counter electrode is kept at a positive or negative potential during the selection period, and is positive or negative during the non-selection period, and the selection is performed. A scan signal that maintains a potential lower than the potential during the period is supplied, and on the other hand, the potential and pulse width or the potential and the number of pulses according to the image data are provided, and the positive potential is positive with respect to the reference potential in a cycle in which the selection period is divided into a plurality of periods. It can be implemented by supplying a data signal whose potential changes with substantially the same amplitude on the negative side and the negative side.

[0026]

According to the driving method of the present invention, a liquid crystal display element using an active element composed of a non-linear resistance element having a semiconductor is driven by a modulation method in which modulation by voltage and modulation by pulse width or number of pulses are combined. Is.

That is, an active element composed of a non-linear resistance element having a semiconductor has a rapid current-voltage characteristic and high responsiveness, so that charge is rapidly accumulated between the pixel electrode and the counter electrode. Therefore, the rising speed of the voltage between both electrodes with respect to the time when the voltage is applied between both electrodes is fast. Therefore, the voltage applied between the pixel electrode and the counter electrode changes according to the voltage value of the selection voltage applied between the drive signal input terminal of the active element and the counter electrode and the pulse width or the number of pulses. ..

Therefore, if the voltage value of the selection voltage and the pulse width or the number of pulses are controlled according to the image data, the voltage applied between the pixel electrode and the counter electrode is changed to change the transmittance of the pixel. Can be controlled.

In the present invention, the liquid crystal display element using the semiconductor active element is driven not by the conventional voltage modulation method but by the modulation method in which the modulation by the voltage and the modulation by the pulse width or the pulse number are combined. Therefore, even if the number of steps of the voltage value of the selection voltage is small, the voltage applied between the pixel electrode and the counter electrode can be changed in multiple steps by controlling the pulse width or the number of pulses for each voltage value. Therefore, it is possible to cause the liquid crystal display element to perform multi-gray scale display without using a drive signal having a multi-step voltage level unlike the conventional drive method.

Further, in the present invention, between the drive signal input terminal of the active element and the counter electrode, during the selection period, the voltage value according to the image data and the pulse width or the positive or negative polarity of the number of pulses are either positive or negative. In the non-selection period in which the selection voltage is applied and other pixels are selected, the potential changes in a cycle shorter than the selection period, and the area on the positive side and the negative side with respect to the potential of the non-selection period of the scanning signal is the center. Since the voltages having substantially the same waveform are applied, the pixel transmittance hardly changes during the non-selection period.

That is, the inter-electrode voltage of the pixel during the non-selection period fluctuates every moment under the influence of the image data for driving the other pixels. If the voltage applied to the counter electrode is a voltage having the above waveform, the variation in the voltage between the electrodes of the pixel is
The fluctuation of the voltage to the positive side and the fluctuation of the voltage to the negative side around the potential of the scanning signal in the non-selection period are almost equal, so the effective value of the inter-electrode voltage of the pixel in the non-selection period (Holding voltage) hardly changes.

Therefore, since the holding voltage of the pixel does not change during the non-selection period, the transmittance of the pixel becomes the transmittance corresponding to the voltage accumulated between the electrodes of the pixel according to the selection voltage applied during the selection period. To be kept. Therefore, it is possible to obtain a display with a correct gradation according to the image data.

[0033]

【Example】

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

First, the structure of an active matrix liquid crystal display element driven by the driving method of this embodiment will be described. FIG. 9 is a plan view of a part of the liquid crystal display element. Here, a nonlinear resistance element having a semiconductor is shown. The active element composed of a diode ring composed of a thin film diode is shown.

This liquid crystal display element includes a pair of transparent substrates (both not shown) facing each other with a liquid crystal layer interposed therebetween, and a plurality of pixel electrodes 1 arranged in a row direction and a column direction on one substrate. , An active element 2 connected to each of these pixel electrodes, and a signal line 3 for supplying a drive signal to the active element 2.
And the counter electrode 4 facing the pixel electrode 1 is provided on the other substrate.

The active element 2 is a so-called diode ring in which the same number of thin film diodes 5 and 6 are connected in parallel in opposite directions, one end of which is connected to the pixel electrode 1 and the other end is connected to the signal line 3. Has been done.

Although FIG. 9 shows one thin film diode 5 and one thin film diode 6 which form a diode ring, the forward circuit and the reverse circuit of the diode ring generally include a plurality of thin film diodes. It is configured by connecting in series.

The signal line 3 is provided for each active element group arranged in the row direction (horizontal direction in the drawing), and the semiconductor active element 2 is connected to the signal line 3 for each row. Further, the counter electrode 4 is provided for each pixel electrode group arranged in the column direction (vertical direction in the drawing), and each counter electrode 4 is opposed to the pixel electrode 1 of each column via a liquid crystal (not shown). .. Each pixel of this liquid crystal display element is formed by the pixel electrode 1, the counter electrode 4 and the liquid crystal between them.

FIG. 10 is an equivalent circuit diagram of one pixel display element of the above liquid crystal display element. The pixel electrode 1 and the counter electrode 4 are shown in FIG.
Since the pixel formed by the liquid crystal and the liquid crystal therebetween is equivalent to the capacitor, the pixel display element including the pixel and the active element 2 has a capacitance (hereinafter, referred to as a capacitance) of the pixel as shown in FIG. , Pixel capacitance) and an active element 2 composed of a diode ring connected in series.

Further, the thin film diodes 5 and 6 forming the diode ring which is the active element 2 have a pair of electrodes facing each other with the semiconductor layer having the P-I-N junction structure sandwiched therebetween. 5 and 6 have a capacitance, and therefore the active element 2 also has the above-mentioned thin film diode 5,
It has a capacity equivalent to the sum of 6 capacities.

Therefore, in the above equivalent circuit, when the diode ring is off, the pixel capacitance CLC and the capacitance of the active element 2 (hereinafter referred to as the element capacitance) CD are connected in series as shown in FIG. 10B. It is represented by a connection circuit.

This liquid crystal display element is driven for display by supplying a drive signal to each signal line 3 and each counter electrode 4. In this display drive, for example, a scanning signal is sequentially applied to each signal line 3. The counter electrodes 4 are supplied and synchronized with this.
Is performed by time-division driving to sequentially select each pixel.

This drive method will be described. FIG. 1 is a waveform diagram of the drive signal. FIG. 1A shows the waveform of the scanning signal SS supplied to the signal line 3 of the first row, and FIG. The waveform of the data signal SD supplied to the counter electrode 4 is shown, and (c) shows between the drive signal input end of the active element 2 (connection end with the signal line 3) and the counter electrode 4 (point a in FIG. 10). Between point c)
The waveform of the voltage Va-c applied to is shown. In FIG. 1, TS is a selection period in which one field TF is divided according to the number of pixel rows (the number of signal lines).

The scanning signal SS becomes the selection potential VC1 during the selection period TS and the non-selection potential VC2 during the non-selection period TO.
And the polarity is inverted between the positive side and the negative side around the reference potential VG in the cycle corresponding to one field TF.

The selection potential VC1 is a potential whose potential difference from the reference potential VG is higher than the threshold voltage of the active element (diode ring) 2, and the non-selection potential VC2 is the active element whose potential difference from the reference potential VG is active. The potential is lower than the threshold voltage of 2.

The data signal SD is a signal having a data pulse having a potential and a pulse width according to image data supplied from the outside in synchronization with the selection periods TS1, TS2, TS3 ... Of the pixels in each row, This data signal SD is supplied to the selection period TS for each selection period TS1, TS2, TS3 ... Of the pixels in each row.
Is evenly divided, for example, in a cycle in which the selection period TS is equally divided into two, the potential changes to the positive side and the negative side with respect to the reference potential VG.

That is, the data signal SD is a signal having a data pulse having a potential and a pulse width corresponding to the image data for each 1/2 period TS of 1/2 of the selection period TS. The data pulse in the first half and the data pulse in the latter half of the selection period TS are pulses having polarities opposite to each other with respect to the reference potential VG. Further, the data pulses in the first half and the latter half of one selection period TS are pulses according to the same image data. Therefore, the positive side pulse and the negative side pulse have the same width and the absolute value of the potential is also the same. equal.

That is, in the data signal SD, the waveform for each selection period TS has the area of the waveform on the positive side with respect to the reference potential VG (the area of the hatched region in the figure) A1 and the negative The signal has a waveform whose waveform area on the side (area of the region shaded in the lower right in the figure) B1 is substantially equal.

In this embodiment, the potential (absolute value) of the data pulse on the positive and negative sides of the data signal SD is set to the low level potential VS1 and the high level potential VS2 (VS2) which is twice the potential.
= 2 · VS1), and one of the two levels of potentials VS1 and VS2 is selected according to the image data.

In the data signal SD shown in FIG. 1, the pulse width of the selection period TS1 of the pixels in the first row is 1/10 of the selection period.
(The potential is VS1), the pulse width of the selection period TS2 of the pixels in the second row is 4/10 of the selection period (the potential is VS2), and the pulse width of the selection period TS3 of the pixels of the third row is 3/10 of the selection period. (Potential is VS1)
Of the data signal SD, each selection period TS
The pulse width for each 1, TS2, TS3 ... Depends on the image data and the pulse potential VS1 or VS2 selected according to this image data, from 0/10 (no pulse) to 5/10 (no pulse) of the selection period TS. It is controlled within the range of 1/2 of the selection period TS).

When the scanning signal SS and the data signal SD having such waveforms are supplied to the signal line 3 and the counter electrode 4, the drive signal input end of the active element 2 connected to the signal line 3 (hereinafter, simply input). A voltage having a waveform obtained by combining the scanning signal SS and the data signal SD as shown in FIG. 1C between the opposite electrode 4 and the counter electrode 4 (corresponding to the potential difference between the scanning signal SS and the data signal SD). Voltage) Va-c is applied.

During the selection period TS, the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 has either a positive or negative polarity of the voltage value and the pulse width according to the image data. Is a voltage of which the potential changes in a half cycle of the selection period TS during the non-selection period TO in which another pixel in the same column is selected.

That is, of the voltages Va-c, the selection voltage applied during the selection period TS is the data signal SD.
Is the same as the selection potential VC1 of the scanning signal SS when the potential of is the reference potential VG, and when the potential of the data signal SD becomes the potential of the data pulse, the selection potential VC1 of the scanning signal SS becomes the potential VS1 of the data pulse, -VS1 or VS2, -V
S1 superposed voltage VC1 + VS1, VC1-VS1 or VC1 +
VS2, VC1-VS2.

The potential of the data signal SD is the reference potential V
Selection voltage when G (hereinafter referred to as reference selection voltage)
VC1 is a voltage higher than the threshold voltage of each thin film diode 5, 6 of the diode ring which is the active element 2. Further, the selection voltages VC1 + VS1 and VC1 + VS2 when the potential of the data signal SD becomes the potentials VS1 and VS2 of the data pulse on the positive side with respect to the reference potential VG are higher than the reference selection voltage VC1 and the data signal The potential of SD is the potential of the data pulse on the negative side with respect to the reference potential VG -VS1,-
The selection voltages VC1-VS1 and VC1-VS2 when reaching VS2 are higher than the reference selection voltage VC1.

The voltage applied between the input terminal of the active element 2 and the counter electrode 4 (hereinafter referred to as the non-selection voltage) during the non-selection period TO is for driving other pixels in the same column. A data pulse corresponding to image data is a voltage superimposed on the scanning signal SS, and this non-selection voltage is the same as the non-selection potential VC2 of the scanning signal SS when the potential of the data signal SD is the reference potential VG. , When the potential of the data signal SD becomes the potential of the data pulse, the non-selection potential V of the scanning signal SS
C2 data pulse potential VS1, -VS1 or VS2, -V
S2 superposed voltage VC2 + VS1, VC2-VS1 or VC2 +
VS2, VC2-VS2.

The voltages VC2 + VS1, VC2-VS1,
VC2 + VS2 and VC2-VS2 are both lower than the reference selection voltage VC1 of the selection voltage applied in the selection period TS, and the positive data pulse potentials VS1 and VS2 are superposed on the non-selection potential VC2 of the scanning signal SS. Voltage VC2 + VS1, VC2
+ VS2 is a voltage VC1-VS1, in which the negative side data pulse potentials -VS1 and -VS2 are superimposed on the selection potential VC1 of the scanning signal SS.
It is a voltage lower than VC1-VS2.

That is, the non-selection voltage is a voltage obtained by superimposing a positive side data pulse and a negative side data pulse according to image data for driving other pixels in the same column. SD is the area A1 of the waveform on the positive side with respect to the reference potential VG as the center for the waveform for each selection period TS.
And the area B1 of the waveform on the negative side are substantially equal to each other, this non-selection voltage is the area A2 of the waveform on the positive side and the waveform on the side of the negative side centering on the non-selection potential VC2 of the scanning signal SS. The area B2 of is approximately equal to the voltage.

Then, the input end of the active element 2 and the counter electrode 4
When the above selection voltage is applied between and, the voltage is applied between the pixel electrode 1 connected to the active element 2 and the counter electrode 4. That is, in FIG. 10, when a selection voltage is applied between a and c, the active element 2 including a diode ring is formed.
Potential difference between both ends of the active element 2 becomes higher than its threshold voltage, the active element 2 is turned on, a current flows through the pixel electrode 1, and bc
A voltage is applied between them (between the pixel electrode 1 and the counter electrode 4).

As described above, when the voltage is applied between b and c, the charging of the pixel capacitance CLC formed by the pixel electrode 1, the counter electrode 4 and the liquid crystal between them is started. The charging of the pixel capacitance CLC is continued during the selection period TS.

When the selection period TS has passed and the non-selection period TO has come, at this time, the charging of the pixel capacitance CLC progresses and the charging voltage becomes high, and the non-selection period T
Since the voltage applied to the input terminal of the active element 2 from the signal line 3 becomes low at O, the potential difference between both ends of the active element 2 becomes small, the active element 2 is turned off, and the charging to the pixel capacitance CLC is stopped. ..

In this case, when the active element 2 is turned off, this active element 2 acts as a capacitor,
When the voltage between a and c at 0 (the voltage between the input terminal of the active element 2 and the counter electrode 4) Va-c decreases (the difference between the voltage during the selection period TS and the voltage during the non-selection period TO), , The pixel capacitance CLC and the element capacitance CD of the active element 2 which are connected in series are divided at a ratio opposite to the capacitance ratio.

Therefore, the voltage held in the pixel capacitance CLC during the non-selection period TO changes from the voltage charged during the selection period TS to the pixel capacitance CLC in the amount of decrease in the voltage a-c between a and c. The voltage is reduced by the divided voltage value.

The liquid crystal is composed of the pixel electrode 1 and the counter electrode 4
It operates by the voltage between and. Due to its responsiveness, the liquid crystal does not operate even when a high electric field is applied during the extremely short selection period TS, but operates in response to the holding voltage of the pixel capacitance CLC during the non-selection period TO.

The pixel capacitance CLC is in a voltage holding state during the non-selection period To, and therefore the voltage between the pixel electrode 1 and the counter electrode 4 is held at the holding voltage of the pixel capacitance CLC, so that the liquid crystal is The operating state is maintained during the non-selection period TO.

However, since the counter electrode 4 is supplied with the data signal SD having a waveform as shown in FIG. 1B having image data for driving the pixels of each row, the selection period T
The image data for driving the other pixels in the same column is applied together with the data signal SD to the counter electrode 4 of the pixel which is in the non-selected state after passing S, and the potential of the counter electrode 4 changes. Therefore, the voltage Va-c between a and c changes, and the voltage between the electrodes of the pixel changes.

The change in the inter-electrode voltage of the pixel due to the change in the a-c voltage Va-c is similar to the voltage change when the selection period TS is changed to the non-selection period TO as described above. It is the voltage divided into the pixel capacitance CLC among the voltages obtained by dividing the variation of -c by a ratio opposite to the capacitance ratio of the pixel capacitance CLC and the element capacitance CD.

However, in this driving method, the non-selection period T
The non-selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 in O is almost equal to the area A2 of the waveform on the positive side and the area B2 of the waveform on the negative side with respect to the reference potential VG. Since the voltages are the same, the fluctuation of the voltage Va-c between a and c due to the influence of the image data for driving the other pixels is
The fluctuation amount to the positive side and the fluctuation amount to the negative side with the non-selection potential VC2 of S as the center are almost equal. Therefore, the holding voltage of the pixel, which is the effective value during the non-selected period, does not change.

Further, when the next selection period TS comes, at this time, the selection voltage of the opposite polarity to the previous selection period TS is shown in FIG.
Since it is applied between a and c of 0, the potential difference between both ends of the active element 2 becomes higher than its threshold voltage, the active element 2 is turned on, and the pixel capacitance CLC is charged to the opposite polarity. The following is the same as the above operation. Next, gradation display by the above driving method will be described.

FIG. 2 is a waveform diagram of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period TS. (1) to (14) represent image data of each gradation. It is a selected voltage according to the above.

Among the selection voltages of (1) to (14), (1) to (14)
As for the selection voltage of (7), the voltage value is the scanning signal S
Low-level data pulse potential VS1 to select potential VC1 of S,
-VS1 is the superimposed voltage (VC1 + VS1, VC1-VS1), and only the pulse widths are different. The selection voltages of (8) to (14) are all voltage values (VC1 + VS2, VC1-VS2) in which the high level data pulse potentials VS2, -VS2 are superimposed on the selection potential VC1 of the scanning signal SS. Yes, only the pulse width is different. The pulse widths of the selection voltages in (8) to (14) are the same as the pulse widths of the selection voltages in (1) to (7), respectively, and the pulse widths of the selection voltages in (7) and (14) are The maximum pulse width is the same as 1/2 of the selection period TS.

FIG. 3 shows the input terminal of the active element 2 and the counter electrode 4.
Shows the voltage applied between the pixel electrode 1 and the counter electrode 4 when the selection voltages of (1) to (14) are applied between When the selection voltage is applied,
The voltage applied between the electrodes rises for the time corresponding to the pulse width of the selected voltage on the rising curve in (b), (8) to (14)
When the selection voltage of is applied,
The rising curve of (a) rises for a time corresponding to the pulse width of the selected voltage.

In FIG. 3, (1) to (14) are the above (1) to (14).
It shows the rising value of the applied voltage between electrodes when the selection voltage in (14) is applied.The selection voltages in (1) to (7) have the same voltage value but different pulse widths.
The rising value of the inter-electrode applied voltage when the selection voltages of (1) to (7) are applied is different for each selection voltage. This is (8)
The same applies when the selection voltage of (14) is applied.
The selection voltages of (8) to (14) also have the same voltage value,
Since the pulse widths are different, the rising value of the inter-electrode applied voltage when these selection voltages (8) to (14) are applied also differs for each selection voltage.

The pulse widths of the selection voltages of (8) to (14) are the same as the pulse widths of the selection voltages of (2) to (7), respectively. Since the voltage value is different from the selected voltage in (2) to (7), the rising value of the applied voltage between electrodes when the selected voltage in (8) to (14) is applied is (2)
~ It becomes a value different from the rising value of the applied voltage between electrodes when the selection voltage of (7) is applied. However, the rising values of the inter-electrode applied voltage when the selection voltage of (7) is applied and when the selection voltage of (8) is applied are almost the same.

4 to 8 show the waveform of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 and the voltage Vb applied between the pixel electrode 1 and the counter electrode 4. Shows the relationship with -c.

In FIG. 4, the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to the selection period TS.
Is 0/10 (no pulse), and at this time, between the input end of the active element 2 and the counter electrode 4, (a)
A selection voltage having a waveform like the above is applied.

When the selection voltage having such a waveform is applied between the input end of the active element 2 and the counter electrode 4, the pixel electrode 1
The inter-electrode voltage Vb-c applied between the counter electrode 4 and the counter electrode 4 is
As shown in (b), it rises with a rising curve corresponding to the reference selection voltage VC1 throughout the entire selection period TS.

When the active period 2 is turned off after the selection period TS has passed and the non-selection period TO has passed, the pixel capacitance CLC
Of the voltage charged during the selection period TS from the voltage a-
Of the decrease in the inter-c voltage Va-c, the voltage V0 is reduced by the voltage divided by the pixel capacitance CLC at a ratio opposite to the capacitance ratio of the pixel capacitance CLC and the element capacitance CD, and this voltage V0 is generated. It becomes a holding voltage between 1 and the counter electrode 4.

In FIG. 5, the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to the selection period TS.
1/10 and the potential is set to the low level potentials VS1 and -VS1. At this time, a waveform of (a) is formed between the input terminal of the active element 2 and the counter electrode 4. A selection voltage is applied. This selection voltage is the voltage (1) shown in FIG.

The waveform of this selection voltage is such that the data signal SD supplied to the counter electrode has a data pulse of the potential VS1 of the same polarity as the scanning signal SS at the end of the first half of the selection period TS, This waveform has a data pulse of the potential -VS1 having a polarity opposite to that of the scanning signal SS at the end of the latter half, and therefore is applied between the input terminal of the active element 2 and the counter electrode 4 in the first half of the selection period TS. The selection voltage is the reference selection voltage VC1 from the beginning to the end of the first half period, and becomes the pulse superposition voltage VC1-VS1 lower than the reference selection voltage VC1 at the end of the first half period. Further, the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 in the latter half of the selection period TS is the reference selection voltage VC1 from the beginning to the end of this latter half period, and at the end of the latter half period. , The pulse superposition voltage VC1 + VS1 which is higher than the reference selection voltage VC1.

When the selection voltage having such a waveform is applied between the input end of the active element 2 and the counter electrode 4, the pixel electrode 1
The inter-electrode voltage Vb-c applied between the counter electrode 4 and the counter electrode 4 is
As shown in (b), from the beginning to the end of the first half of the selection period TS, a rising curve rises according to the reference selection voltage VC1, and at the end of this first half, the low-voltage pulse superposition voltage V
It rises with a gentle rising curve according to C1-VS1 and rises again with a rising curve according to the reference selection voltage VC1 from the beginning to the end of the latter half of the selection period TS, and at the end of this latter half the high voltage pulse superposition voltage VC1 + V
By applying S1, the voltage rises rapidly and reaches the voltage value of (1) in FIG.

In addition, when the selection period TS has passed and the non-selection period TO has come, the voltage of the pixel capacitance CLC becomes the voltage V1 lowered at a constant rate, and this voltage V1 is generated between the pixel electrode 1 and the counter electrode 4. It becomes the holding voltage between.

FIG. 6 shows a state in which the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is the same as that in FIG. 5 and the potentials thereof are set to the high level potentials VS2 and -VS2. At this time, a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. This selection voltage is the voltage (8) in FIG.

In this case, since the data pulse width of the selection voltage is the same as the data pulse width of the selection voltage of FIG. 5A, the inter-electrode voltage Vb applied between the pixel electrode 1 and the counter electrode 4 is applied. As shown in FIG. 5B, -c rises rapidly at the same time as in FIG. 5B (the latter half of the selection period TS) for the same time, but the voltage value VC1 + VS2 of the selection voltage at this time is shown in FIG. Since it is higher than the voltage value VC1 + VS1 of the selection voltage of a), the rise of the inter-electrode voltage Vb-c is more rapid than that of FIG. 5B, and therefore the inter-electrode voltage Vb-c is
It rises up to the voltage value of (8) in Fig. 3.

Also in this case, when the selection period TS has passed and the non-selection period TO has come, the voltage of the pixel capacitor CLC becomes the voltage V8 lowered at a constant ratio, and this voltage V8 becomes the pixel electrode 1 and the counter electrode. The holding voltage is between 4 and 4.

Further, in FIG. 7, the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 2.5 / 10 of the selection period TS, and the potential thereof is set to the high level potential VS2,-.
This is the state when VS2 is set, and at this time, a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. This selection voltage is the voltage (10) shown in FIG.

When the selection voltage having such a waveform is applied between the input end of the active element 2 and the counter electrode 4, the pixel electrode 1
The inter-electrode voltage Vb-c applied between the counter electrode 4 and the counter electrode 4 is
As shown in (b), in the first half of the selection period TS, a rising curve corresponding to the reference selection voltage VC1 and the reference selection voltage VC1
It rises with a rising curve corresponding to the lower pulse superimposed voltage VC1−VS2, and also rises with a rising curve corresponding to the reference selection voltage VC1 and a rising curve corresponding to the high voltage pulse superimposed voltage VC1 + VS2 in the latter half of the selection period TS. At this time, since the voltage value of the selection voltage is the same as that in FIG. 6A, the selection voltage is the high voltage pulse superposition voltage VC1.
The rising curve of the inter-electrode voltage Vb-c at the time of + VS2 is the same as that of FIG. 6B, but the data pulse width of the selection voltage is wider than that of FIG. Since it is long, the inter-electrode voltage Vb-c is (10) in FIG.
Rises to the voltage value of.

When the non-selection period TO has passed after the selection period TS has passed, the voltage of the pixel capacitance CLC becomes the voltage V10 which is lowered at a constant rate, and this voltage V10 is between the pixel electrode 1 and the counter electrode 4. Becomes the holding voltage.

Further, in FIG. 8, the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 5/10 of the selection period TS (the maximum pulse width equal to 1/2 of the selection period TS). , Where the potentials are high level potentials VS2 and -VS2. At this time, a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. To be done. This selection voltage is the voltage (14) in FIG.

When the selection voltage having such a waveform is applied between the input end of the active element 2 and the counter electrode 4, the pixel electrode 1
The voltage Vb-c applied between the counter electrode 4 and the counter electrode 4 is (b)
As described above, the first half of the selection period TS rises with the rising curve corresponding to the pulse superposition voltage VC1-VS2 lower than the reference selection voltage VC1, and rises with the rising curve corresponding to the high voltage pulse superposition voltage VC1 + VS2 in the latter half of the selection period TS. .. At this time, since the voltage value of the selection voltage is the same as that in FIGS. 6A and 7A, the rising curve of the inter-electrode voltage Vb-c when the selection voltage becomes the high voltage pulse superposition voltage VC1 + VS2 However, the data pulse width of the selection voltage is wider than that of FIG. 7A, and therefore the application time of the pulse superposition voltage is longer,
The inter-electrode voltage Vb-c rises to the voltage value of (14) in FIG.

When the non-selection period TO has passed after the selection period TS has passed, the voltage of the pixel capacitance CLC becomes the voltage V14 which is lowered at a constant ratio, and this voltage V14 is between the pixel electrode 1 and the counter electrode 4. Becomes the holding voltage.

4 to 8, the voltage Vb- applied between the pixel electrode 1 and the counter electrode 4 during the selection period TS.
The peak value of c (the voltage value at the end of the selection period TS) is the waveform of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and the current-voltage of the diode ring which is the active element 2. Characteristics and time for which the selection voltage is applied (selection period T
S) and

That is, the inter-electrode voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 during the selection period TS is the voltage applied between the input end of the active element 2 and the counter electrode 4. In accordance with the voltage value of Va-c, the active element 2 rises with a rising curve determined by the current-voltage characteristic, and when the selection period TS elapses and the selection voltage is no longer applied,
The rise stops.

Therefore, the voltage held in the pixel capacitor CCL when the selection period TS has elapsed and the non-selection period TO has elapsed (from the voltage charged during the selection period TS, the amount of decrease in the voltage between a and c) Of these, the voltage Vb-c reduced by the divided voltage value to the pixel capacitance CLC) varies depending on the voltage value of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 and its data pulse width.

For example, when the selection voltage is a voltage with a data pulse width of 0 (no pulse), the pixel capacitance C
The voltage Vb-c held in CL becomes the lowest voltage V0 in the voltage control range as shown in FIG. Also, the selection voltage is
Maximum pulse width as shown in (14) of Fig. 2 (1 / the selection period TS
When the data pulse of 2) is provided and the pulse voltage is the high voltage VS2, the voltage V held in the pixel capacitor CCL
bc becomes the highest voltage in the voltage control range as shown in FIG.

Further, even if the selection voltage is a voltage having a data pulse of maximum pulse width as shown in (7) of FIG.
If the pulse voltage is a low voltage VS1, or if the selected voltage is a voltage having a data pulse with a width narrower than the maximum pulse width as shown in (1) to (6) and (8) to (13) of FIG. In some cases, the voltage Vb-c held in the pixel capacitance CCL becomes a voltage between the minimum value and the maximum value of the voltage control range, and this voltage depends on the data pulse width of the selection voltage and its pulse voltage. Change.

Incidentally, (1)-(6) and (8) -shown in FIG.
The selection voltage of (13) is the voltage of the waveform in which the data pulse is superimposed at the end of the first half and the end of the second half of the selection period TS.
This selection voltage may be a voltage of a waveform in which a data pulse is superimposed in the initial or middle period of the first half of the selection period TS and in the initial or middle period of the latter half thereof, and in that case also, the inter-electrode voltage Vb-c held in the pixel capacitance CCL. Becomes a value according to the voltage value of the selection voltage and the pulse width.

On the other hand, the rising angle of the liquid crystal depends on the pixel electrode 1
And a counter electrode 4 are applied between the counter electrode 4 and the counter electrode 4 (holding voltage of the pixel capacitance CCL) Vb-c, and the light transmittance of the pixel changes according to the rising angle of the liquid crystal.

Therefore, as described above, the selection period TS
A pixel voltage 1 and a counter electrode 4 connected to the active element 2 are applied by applying a selection voltage having a voltage value and a pulse width according to image data between the input terminal of the active element 2 and the counter electrode 4. By applying a voltage having a value corresponding to the voltage value of the selection voltage and the data pulse width in between, it is possible to realize gradation display by controlling the transmittance of the pixel.

Next, the number of gradations in the gradation display will be described. For this number of gradations, how many steps can be selected for the value of the voltage Vb-c for charging the pixel capacitance CCL during the limited selection period TS. Depends on

Then, as described above, the voltage value and the pulse width of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 are changed to apply the voltage applied between the pixel electrode 1 and the counter electrode 4. In the gradation display by the modulation method that combines the voltage modulation and the pulse width modulation for controlling the change of the applied voltage between the pixel electrode 1 and the counter electrode 4 corresponding to the voltage value of the selection voltage and the pulse width. , The liquid crystal display element using the active element 2 formed of a diode ring is determined by the current-voltage characteristic of the active element. The applied voltage between the electrode 1 and the counter electrode 4 can be greatly changed.

FIG. 11 shows the active element 2 of the liquid crystal display element.
The current-voltage characteristics of the diode ring are shown in comparison with the current-voltage characteristics of the MIM utilizing the tunnel effect. As shown in FIG.
Compared to IM, the current-voltage characteristics are rapid and the response is high.

Therefore, the above-mentioned liquid crystal display element using the diode ring as the active element 2 does not need to have a high applied voltage unlike the liquid crystal display element having the MIM as the active element, and the gradation display by the high time division driving is performed. Is possible.

The current-voltage characteristics of the diode ring can be arbitrarily selected by changing the film thickness of the I-type semiconductor layer of the thin film diodes 5 and 6, and between a and b in FIG. 10 (a). The current-voltage characteristics can be arbitrarily selected also by changing the number of the thin film diodes 5 and 6.

That is, the current-voltage characteristics of the diode ring become steeper as the film thickness of the I-type semiconductor layer of the thin film diodes 5 and 6 becomes thinner, and the thin film diodes of the forward circuit and the reverse circuit of the diode ring are formed. The smaller the number, the faster it becomes.

In FIG. 12, the diode ring is used as the active element 2.
Of the liquid crystal display element, the pixel capacitance CLC for the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4.
FIG. 5A is a charging characteristic diagram of a liquid crystal display device using a diode ring having a general current-voltage characteristic, and FIG. 6B is a diode ring having a more rapid current-voltage characteristic. 7 shows a pixel capacitance charging characteristic of a liquid crystal display element using.

The pixel capacitance charging characteristic shown in FIG. 12A is a characteristic in which the charging voltage of the pixel capacitance CLC reaches its peak in a charging time of about 40 μsec, and a liquid crystal display element having this pixel capacitance charging characteristic is Approximately 40 hours when the selection period TS is divided into two
μsec (suitable for high time-division driving with a time-division number of selection period TS of about 80 μsec.

Therefore, gradation display of this liquid crystal display element may be performed by controlling the pulse width of the selection voltage within the range of 0 to about 40 μsec. For example, between the pixel electrode 1 and the counter electrode 4. In the case of a negative display type liquid crystal display element in which a pixel transmits light when a voltage is applied, the gradation of the display pixel becomes darkest when a selection voltage with a pulse width of 0 (no pulse) is applied. When a selection voltage with a pulse width of about 40 μsec is applied, the brightness becomes the maximum, and when a selection voltage with a pulse width within the range of 0 to about 40 μsec is applied, the brightness becomes according to this pulse width.

As described above, the number of display gradations depends on how many levels the voltage Vb-c that charges the pixel capacitor CCL can be selected during the selection period TS, but the gradation difference is clear. In order to obtain a gray scale display, it is necessary to make the difference in the charging voltage Vb-c of the pixel capacitance CCL, that is, the difference in the voltage applied between the pixel electrode 1 and the counter electrode 4 large to some extent.

For this reason, the pulse width of the selection voltage is the voltage V of the voltage difference that produces a clear gradation difference in the pixel capacitance CLC.
Although it is necessary to control the width difference so that bc can be charged, the rising curve of the voltage Vb-c charged in the pixel capacitance CLC is assumed to have a constant current-voltage characteristic of the active element 2. Since it is determined by the voltage Va-c applied between the input end of the active element 2 and the counter electrode 4, the applied voltage Va-c should be increased to some extent to make the rising curve of the charging voltage Vb-c steep. For example, even if the difference between the pulse widths of the selection voltages is relatively small, the pixel capacitance CLC can be charged with the voltage Vb-c having a sufficient voltage difference.

When the applied voltage Va-c is increased,
During the selection period TS, the range of the voltage Vb-c charged in the pixel capacitor CCL increases according to the pulse width of the selection voltage. If the range of the charged voltage Vb-c is large, the pixel electrode 1
The number of steps of the voltage applied between the counter electrode 4 and the counter electrode 4 can be increased.

Therefore, if the value of the reference selection voltage VC1 of the selection voltage is set to be high to some extent, the number of pulse widths of the selection voltage can be increased and multi-step gradation display can be performed. The reference selection voltage VC1 of the above selection voltage is
The voltage may be considerably lower than the voltage required to cause the liquid crystal display element using the MIM as an active element to perform gradation display.
This also applies to the liquid crystal display element having the pixel capacitance charging characteristic shown in FIG.

Further, the pixel capacitance charging characteristic shown in FIG. 12B is a characteristic that the charging voltage of the pixel capacitance CLC reaches a peak in a charging time of 10 to 15 μsec, and a liquid crystal display having this pixel capacitance charging characteristic is obtained. Since the time required for the element to divide the selection period TS into two equal parts is very short, 10 to 15 μsec (selection period TS is 20 to 30 μsec), the number of display gradations is the same as the pixel capacitance charging shown in FIG. Even if the liquid crystal display element has the same characteristics, it can be time-divisionally driven by a much larger number of time divisions.

The above-mentioned driving method drives the liquid crystal display element using the active element 2 composed of the diode ring by the modulation method in which the voltage value of the selection voltage and the data pulse width are changed according to the image data. Therefore, even if the number of steps of the voltage value of the selection voltage is small, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be changed in multiple steps by controlling the pulse width for each voltage value. Therefore, since it is not necessary to use a drive signal of multi-step voltage level unlike the voltage modulation method that has been conventionally adopted as a driving method of the liquid crystal display element, the above-mentioned liquid crystal display can be realized by a driving circuit having a simple structure. The element can be made to perform multi-tone gradation display.

On the other hand, in the non-selection period TO, the scanning signal SS supplied to the signal line 3 becomes the non-selection potential VC2, but in the counter electrode 4, according to the image data in each selection period of the pixels in each row. Since the data signal SD whose pulse width changes is supplied, the voltage Va- between the input terminal of the active element 2 and the counter electrode 4 is
c also fluctuates in the non-selection period To according to the image data for driving the other pixels in the same column.

For this reason, the inter-electrode voltage of the pixel during the non-selection period TO is the same as the voltage variation between the a-c voltage Va when the selection period TS is changed to the non-selection period TO. Among them, the divided value to the pixel capacitance CLC (the voltage divided to the pixel capacitance CLC among the voltages divided to the pixel capacitance CLC and the element capacitance CD at a ratio opposite to the capacitance ratio) is changed.

That is, the pixels in the non-selection period To are
The voltage value of the inter-electrode voltage VLC at the end of the selection period TS, such as the waveform of the non-selection period TO in FIGS. 2 to 8B (from the voltage applied during the selection period TS to the non-selection period) Of the decrease in the voltage Va between a and c when it becomes TO, the voltage value decreased by the divided value to the pixel capacitance CLC) V0-
A non-selection voltage is applied to V14 in which a variation (a variation divided by the pixel capacitance CLC) due to the influence of image data for driving another pixel is superimposed.

However, in the above driving method, as shown in FIG. 1, the scanning signal SS supplied to the signal line 3 is kept at the selection potential VC1 of either positive or negative polarity during the selection period TS, and the non-selection period is maintained. A signal having a positive or negative polarity in TO and a non-selection potential VC2 lower than the selection potential VC1 in the selection period TS is used as a signal, and the data signal SD supplied to the counter electrode 4 is pulsed with a width corresponding to the image data. And a potential change with an amplitude substantially equal to the positive side and the negative side with respect to the reference potential VG in a cycle in which the selection period TS is divided into two, that is, the area of the waveform on the positive side around the reference potential VG. Since A1 and the area B1 of the waveform on the negative side have substantially the same waveform signal, the voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period To is as described above. Moderates non-selection potential VC2 of scanning signal SS As the core, the area A2 of the waveform on the positive side and the area B2 of the waveform on the negative side are substantially equal to each other.

Therefore, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is, as shown in FIGS. The voltage value of the inter-electrode voltage VLC (hereinafter referred to as a reference holding voltage) V0 to V14 at the end of the selection period TS is approximately the same amplitude on the positive side and the negative side (images for driving other pixels). This is the voltage whose voltage value changes due to the amplitude of fluctuation due to the influence of data). That is, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is the reference holding voltage V0 to
The area A3 on the positive side and the area B3 on the negative side of V14 are substantially equal to each other.

Therefore, the amount of change in the non-selection voltage applied between the electrodes of the pixels during the non-selection period TO is approximately equal to the amount of change in the negative side, and therefore the change in the voltage to the positive side is substantially the same. Minute and negative voltage fluctuations cancel each other out,
The effective value of the inter-electrode voltage of the pixel in the non-selection period To, that is, the holding voltage is maintained at the reference holding voltages V1 to V14 and hardly changes.

If the effective value of the inter-electrode voltage during the non-selection period TO hardly changes, the voltage-transmittance characteristic of the pixel during the non-selection period TO hardly changes. The voltage values V0 to V accumulated in the pixel capacitance CLC according to the pulse width of the selection voltage applied in the period TS.
Since the transmissivity corresponding to 14 is maintained, the transmissivity of the pixel hardly changes during the non-selection period To, and therefore, it is possible to obtain the display of the correct gradation according to the image data.

That is, FIG. 13 shows the pulse width-transmittance characteristics of one pixel when the active matrix liquid crystal display element having the above-mentioned structure is time-division driven by the driving method of the above-mentioned embodiment, and the solid line shows Of the pixels in one column corresponding to one counter electrode 4, all the other pixels except one measuring pixel are in a transmissive state (state in which no selection voltage is applied).
When the control is performed in the following manner, the broken line shows that all of the pixels in the above-mentioned one column except one measuring pixel are in the non-transmissive state (the voltage value is high and the full width of 1/2 of the selection period TS). (A state in which a selection voltage having a maximum pulse width corresponding to is applied) is controlled.

Further, in FIG. 13, the lower curve is the characteristic when a low selection voltage (the voltage of the waveforms (1) to (7) in FIG. 2) is applied to the measuring pixel, and the upper curve is 2 is a characteristic when a high voltage selection voltage (voltages having waveforms (8) to (14) in FIG. 2) is applied to the measurement pixel.

As is apparent from FIG. 13, the pulse width-transmittance characteristic (characteristic of the solid line) when all the other pixels are controlled to be in the transmissive state and all the other pixels are controlled to be in the non-transmissive state. The pulse width-transmittance characteristic (characteristic of the broken line) at this time is very similar, and even when a low voltage selection voltage is applied to the measurement pixel and when a high voltage selection voltage is applied to the measurement pixel. However, the fluctuation range of the transmittance of the measurement pixel, which varies depending on the driving state of other pixels in the same column, is within about 5%.

Therefore, the pulse width-transmittance characteristic is hardly influenced by the driving states of other pixels, and therefore the transmittance of the pixel is properly set in accordance with the pulse width of the selection voltage applied in the selection period TS. Can be controlled.

In addition, in the driving method of the above embodiment, the data signal SD is a signal whose waveform in each selection period has positive and negative data pulses with respect to the reference potential VG, but is active during the selection period TS. The selection voltage applied between the input terminal of the element 2 and the counter electrode 4 is either the positive or negative voltage with respect to the non-selection potential VC2 of the scanning signal SS, which is the voltage on which the positive or negative data pulse is superimposed. Therefore, the electric charge of one polarity is accumulated between the pixel electrode 1 and the counter electrode 4 during the selection period TS.

That is, the charge between the electrodes of the pixel is carried out by making full use of the selection period, so that the charge time between the electrodes of the pixel can be sufficiently taken.
The voltage applied between the electrodes of the pixel can be made sufficiently high without being affected by the ability of the active element (ability to pass current).

Further, in the conventional driving method, the voltage of the pixel −
Since the driving characteristics of other pixels have a great influence on the transmittance characteristics, in order to reduce the fluctuation of the voltage-transmittance characteristics, the element capacitance of the active element relative to the pixel capacitance is made considerably small to drive the other pixels. Among the fluctuations of the applied voltage between the input terminal of the active element and the counter electrode due to the image data, the voltage divided by the pixel capacitance needs to be extremely small.

Therefore, in the conventional liquid crystal display element using the diode ring as an active element, the diodes forming the diode ring are formed in the smallest possible element area to reduce the capacitance, or the forward direction of the diode ring is used. The circuit and the reverse circuit are each configured by connecting a plurality of diodes in series to reduce the capacitance of the diode ring.

However, in order to reduce the device area of the diode as described above, highly precise patterning is required in the manufacturing thereof, and the number of diodes constituting the forward and reverse circuits of the diode ring is increased. Therefore, the area occupied by the diode ring becomes large, and the area of the pixel electrode is restricted accordingly.

On the other hand, in the driving method of the above-described embodiment, as described above, since the fluctuation amount of the non-selection voltage to the positive side and the fluctuation amount to the negative side are canceled each other, the non-selection voltage is not selected. The fluctuations in voltage may be large to some extent, so
Of the variation of the applied voltage between the input terminal of the active element 2 and the counter electrode 4, it is not necessary to extremely reduce the voltage divided by the pixel capacitance CLC.

Therefore, the ratio of the element capacitance CD to the pixel capacitance CLC is such that the voltage drop due to the capacitance ratio partial pressure when the selection period TS changes to the non-selection period TO can be suppressed within a certain range (for example, 1/10). Degree).

Therefore, according to the driving method of the above-described embodiment, the diodes constituting the diode ring can be formed in a relatively large element area, so that the diode ring can be easily manufactured without the need for highly precise patterning. In addition, the number of diodes forming the forward and reverse circuits of the diode ring is reduced, the area occupied by the diode ring is reduced, and the area of the pixel electrode is correspondingly increased to increase the aperture ratio of the liquid crystal display element. Can be higher.

In the above embodiment, the data signal is a signal whose potential changes to the positive side and the negative side with respect to the reference potential VG in a cycle that divides the selection period TS into two equal parts, but this data signal is selected. If the signal whose potential changes to the positive side and the negative side with respect to the reference potential VG in a cycle in which the period TS is divided into a plurality of
The signal may have any waveform, in short, between the input end of the active element 2 and the counter electrode 4, during the selection period TS, either the voltage value according to the image data or the polarity of either positive or negative pulse width is used. A voltage of a waveform whose potential changes in a cycle shorter than the selection period TS and whose positive and negative areas are substantially equal to each other with the non-selection potential VC2 of the scanning signal SS as the center. Can be applied.

In the above embodiment, the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period TS has the waveforms (1) to (14) shown in FIG. The selected voltage is, for example, (1) to (1
The voltage having the waveform of 1) may be used, and in that case, the 11-step voltage of (1) to (11) shown in FIG. 15 is applied between the pixel electrode 1 and the counter electrode 4 to obtain the 11-step voltage. It is possible to perform gray scale display of the number of gray scales (12 stages when the gray scale when a pulseless selection voltage is applied is added).

The reference selection voltage VC1 of the selection voltages shown in FIG. 15 and the data pulse superimposed voltages VC1 + VS1 and VC1-VS.
High-level potential VS of 1, VC1 + VS2, VC1-VS2
Voltage VC1 + VS with data pulse of -VS2 superimposed
2, VC1-VS2 are the same as the voltages VC1 + VS2, VC1-VS2 in FIG. In addition, the potential VS of the low-level data pulse
1 and -VS1 are almost 2/3 of the high level potentials VS2 and -VS2. Therefore, the voltages VC1 + VS1 and VC1-VS1 on which the data pulses of the low level potentials VS1 and -VS1 are superimposed are the voltages VC1 + VS1 in FIG. , VC1-VS1 has a slightly higher absolute value.

Even when the voltages having the waveforms (1) to (11) in FIG. 15 are selected voltages, the voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period TO is , In the cycle of 1/2 of the selection period TS, the positive and negative sides have substantially the same amplitude centering on the voltage value (reference holding voltage) of the inter-electrode voltage VLC at the end of the selection period TS (other pixels Is a voltage whose voltage value changes with the amplitude of the fluctuation due to the influence of the image data for driving the pixel voltage. Therefore, the effective value of the inter-electrode voltage of the pixel in the non-selection period To, that is, the holding voltage, is maintained Since there is almost no fluctuation due to dripping, it is possible to obtain a display with a correct gradation according to the image data. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.
~ It demonstrates with reference to FIG. It should be noted that description of items that are the same as those of the first embodiment described above will be omitted.

The driving method of this embodiment will be described with reference to FIG.
6 is a waveform diagram of the drive signal, and FIG. 6A is a scanning signal S supplied to the signal line 3 of the first row of the liquid crystal display element shown in FIG.
The waveform of S, (b) is the waveform of the data signal SD supplied to one counter electrode 4, (c) is the drive signal input end (connection end with the signal line 3) of the active element 2 and the counter electrode 4. The waveform of the voltage Va-c applied between the points (between points a and c in FIG. 10) is shown.

The scanning signal SS is the same signal as in the first embodiment, and becomes the selection potential VC1 during the selection period TS and the non-selection potential VC2 during the non-selection period TO, and its polarity is inverted every field TF. To do.

On the other hand, the data signal SD is a signal of a voltage value and a pulse number corresponding to image data supplied from the outside in synchronization with the selection period of the pixels of each row, and the data signal SD is the pixel of each row. Is a signal in which the potential changes with an amplitude substantially equal to the positive side and the negative side with respect to the reference potential VG in a cycle in which the selection period TS is evenly divided for each of the selection periods TS1, TS2, TS3.

In the figure, the number of divisions of the selection period TS is divided into ten equal parts in order to make the waveform easy to see, but the number of divisions of the selection period TS is, for example, several tenths, and the width of the data pulse is Is the same as the width of one divided period of the selection period TS.

The number of data pulses of the positive side potential VS and the number of data pulses of the negative side potential −VS in each selection period of the data signal SD are the numbers corresponding to the same image data. The number of data pulses on the positive side and the number of data pulses on the negative side for each of the selection periods TS1, TS2, TS3 ... Are the same, and the absolute value of the potential is also the same.

That is, the data signal SD is a signal whose waveform in each selection period TS is a waveform in which the area of the waveform on the positive side and the area of the waveform on the negative side about the reference potential VG are substantially equal.

In this embodiment, the potentials (absolute values) of the positive and negative data pulses of the data signal SD are set to the low level potential VS1 and the high level potential VS2 (VS2
= 2 · VS1), and one of the two levels of potentials VS1 and VS2 is selected according to the image data.

Further, the data signal SD shown in FIG.
The number of pulses on the positive side and the negative side in the selection period TS1 of the pixels in the first row is 1, respectively, the number of pulses on the positive side and the negative side in the selection period TS2 of the pixels in the second row are 4, respectively, and The number of pulses on the positive side and the number of pulses on the negative side in the selection period TS3 are two, respectively. Each selection period T of the data signal SD
The number of positive and negative data pulses for each S1, TS2, TS3 ...
Depending on the image data, it varies in the range of 0 (no pulse) to n (the maximum allowable number of pulses that can be applied during the selection period TS determined by the pulse width).

When the scanning signal SS and the data signal SD having such waveforms are supplied to the signal line 3 and the counter electrode 4, the input end of the active element 2 connected to the signal line 3 and the counter electrode 4 are connected.
16A and 16B, a voltage Va-c having a waveform obtained by combining the scanning signal SS and the data signal SD as shown in FIG. 16C is applied.

Of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4, the selection voltage applied during the selection period TS is the reference potential VG which is the potential of the data signal SD. Is the same as the selection potential VC1 of the scanning signal SS, and when the potential of the data signal SD becomes the potential of the data pulse, the selection potential VC1 of the scanning signal SS becomes the potentials VS1, -VS1 or VS2, -2 of the data pulse. Voltage VC1 + VS1, VC1-VS1 or VS1 + VS2, VC1-
It becomes VS2. In addition, each of these voltages VC1 + VS1, VC1-VS
The values of 1, VC1 + VS2 and VC1-VS2 are the same as those in the first embodiment.

Further, the non-selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period TO is the data corresponding to the image data for driving the other pixels in the same column. The pulse is a voltage superimposed on the scanning signal SS, and this non-selection voltage is the same as the non-selection potential VC2 of the scanning signal SS when the potential of the data signal SD is the reference potential VG, but it is the potential of the data signal SD. Becomes the potential of the data pulse, the voltage VC2 is obtained by superimposing the data pulse potentials VS1, -VS1 or VS2, -VS2 on the non-selection potential VC2 of the scanning signal SS.
+ VS1, VC2-VS1 or VC2 + VS2, VC2-VS2. These voltages VC2 + VS1, VC2-VS1, VC2 + VS2,
The value of VC2-VS2 is also the same as in the first embodiment.

That is, the non-selection voltage is a voltage in which the positive side data pulse and the negative side data pulse corresponding to the image data for driving the other pixels in the same column are superposed. The voltage is the non-selection potential VC2 of the scanning signal SS.
The area of the waveform on the positive side and the area of the waveform on the negative side are substantially equal to each other.

Then, the input end of the active element 2 and the counter electrode 4
When a selection voltage is applied between the pixel electrode 1 and the counter electrode 4, the voltage is applied between the pixel electrode 1 connected to the active element 2 and the counter electrode 4.
The charging of the pixel capacitance CLC formed by the pixel electrode 1, the counter electrode 4 and the liquid crystal between them is started.

Further, after the selection period TS has passed and the non-selection period TO has come, the voltage between the input terminal of the active element 2 and the counter electrode 4, that is, the voltage Va-c between a and c in FIG. Then, the active element 2 is turned off and the charging of the pixel capacitance CLC is stopped, and the voltage of the pixel capacitance CLC is reduced from the voltage during the selection period TS by the amount of decrease in the a-c voltage Va-c.
Divided value to LC (pixel capacitance C LC and element capacitance C of active element 2
The voltage divided by D is the voltage divided by the pixel capacitance CLC among the voltages divided by the ratio opposite to the capacitance ratio. The gradation display by the driving method of this embodiment is also basically performed in the same manner as in the first embodiment described above.

That is, FIG. 17 to FIG.
3 shows the relationship between the waveform of the voltage Va-c applied between the input terminal of the pixel electrode 1 and the counter electrode 4 and the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.

In FIG. 17, the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is 0 respectively.
This is a state in which there is no pulse, (a) is the waveform of the selection voltage applied between the input end of the active element 2 and the counter electrode 4, and (b) is the pixel electrode 1 and the counter electrode 4. It is a waveform of the voltage Vb-c applied during the period.

In FIG. 18, the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is 1 respectively.
And (a) is a waveform of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is This is the waveform of the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.

FIG. 19 shows a state in which the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is the same as in FIG. 18, and the potentials thereof are set to the high level potentials VS2 and -VS2. Yes, (a) is the waveform of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4. Is the waveform of.

In FIG. 20, the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is set to the maximum allowable number n of pulses, and the potential thereof is set to the low level potential VS1,
-VS1, where (a) is the waveform of the selection voltage applied between the input end of the active element 2 and the counter electrode 4, and (b) is between the pixel electrode 1 and the counter electrode 4. It is the waveform of the voltage Vb-c applied to.

In FIG. 21, the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is set to the maximum allowable pulse number n as in FIG. 20, and the potential thereof is set to the high level potential V.
S2 and -VS2, where (a) is the waveform of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is the pixel electrode 1 and the counter electrode 4. It is a waveform of the voltage Vb-c applied during the period.

Also in the driving method of this embodiment, the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 is selected between the input terminal of the active element 2 and the counter electrode 4. When the voltage is the reference selection voltage VC1, it rises with a rising curve corresponding to this voltage VC1, and when the selection voltage becomes the pulse superposition voltage VC1-VS1 or VC1-VS2 which is a voltage lower than the reference selection voltage VC1, the reference selection voltage Pulse superposition voltage VC1 + V that rises with a rising curve that is gentler than that when VC1 is applied and the selection voltage is higher than the reference selection voltage VC1.
When it becomes S1 or VC1 + VS2, it rises with a steep rising curve. Since the selection voltage is a voltage whose voltage value and the number of data pulses are different depending on the image data, the voltage V applied between the pixel electrode 1 and the counter electrode 4 is
bc corresponds to the number of data pulses of the selection voltage and is shown in FIG.
As shown in FIG. 21 (b), it rises in a stepwise manner.

Therefore, the voltage held in the pixel capacitor CCL when the selection period TS has passed and the non-selection period TO has passed (from the voltage charged during the selection period TS, the amount of decrease in the voltage between a and c) Of these, the voltage Vb-c reduced by the divided voltage value to the pixel capacitance CCL varies depending on the voltage value of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 and the number of data pulses.

For example, when the selection voltage is a voltage in which the number of data pulses is 0 (no pulse) as shown in FIG. 17,
The voltage Vb-c held in the pixel capacitor CCL becomes the lowest voltage V0 in the control range, and the selection voltage is as shown in FIG.
When the voltage is a high level voltage VC1 + VS2 such as 1 and has a data pulse of the maximum allowable pulse number n, the voltage Vb-c held in the pixel capacitance CCL is the highest voltage VnH in the control range. become.

Even if the selected voltage is the voltage having the data pulse of the maximum allowable pulse number n, the voltage value is as shown in FIG.
In the case of the low level voltage VC1 + VS1 such as, the voltage Vb-c held in the pixel capacitor CCL becomes the voltage VnL between the minimum value and the maximum value of the control range.

Also, when the selection voltage is a voltage having a data pulse in a part of the selection period TS, the voltage Vb-c held in the pixel capacitor CCL is between the lowest value and the highest value of its control range. Voltage, and this voltage changes according to the voltage value of the selection voltage and the number of data pulses. That is, for example, in FIG.
When the number of data pulses is 1 as shown in FIG. 19, the voltage Vb-c held in the pixel capacitor CCL is V1L, V1H which is the voltage between the minimum value and the maximum value of the control range. .. Since the voltage value VC1 + VS2 of the selection voltage in FIG. 19 is higher than the voltage value VC1 + VS1 of the selection voltage in FIG.
8 and the pixel capacitance C when the selection voltage of FIG. 19 is applied.
The voltage held in CL is based on the holding voltage V1L in FIG.
The holding voltage V1H of 9 is higher.

The selection voltage (voltage during the selection period TS of Va-c) shown in (a) of FIG. 18 and FIG. 19 is a waveform in which a data pulse is superimposed at the end of the selection period TS. The superimposition timing of the data pulse of the selection voltage may be the initial period or the middle period of the selection period TS.

The rising angle of the liquid crystal is determined by the voltage applied between the pixel electrode 1 and the counter electrode 4 (pixel capacitance CLC
Holding voltage) Vb-c, and the pixel transmittance changes according to the rising angle of the liquid crystal.

Therefore, as described above, the selection period TS
A pixel voltage 1 and a counter electrode 4 connected to the active element 2 are applied by applying a selection voltage having a voltage value and a pulse number corresponding to image data between the input terminal of the active element 2 and the counter electrode 4. By applying a voltage having a value corresponding to the voltage value of the selection voltage and the number of data pulses in between, it is possible to realize gradation display by controlling the transmittance of the pixel.

The number of gradations of this gradation display is determined by how many steps the value of the voltage Vb-c charged to the pixel capacitance CCL can be selected during the limited selection period TS, but it is a semiconductor active element consisting of a diode ring. As described in the first embodiment, the liquid crystal display element using No. 2 has a steep current-voltage characteristic and a high responsiveness of the active element 2, so that the input terminal of the active element 2 and the counter electrode are By controlling the number of pulses of the selection voltage applied between the pixel electrode 1 and the counter electrode 4, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be greatly changed.

The above-mentioned driving method drives the liquid crystal display element using the active element 2 composed of the diode ring by the modulation method in which the voltage value of the selection voltage and the number of data pulses are changed according to the image data. Therefore, even if the number of steps of the voltage value of the selection voltage is small, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be changed in multiple steps by controlling the number of pulses for each voltage value. Therefore, since it is not necessary to use a drive signal of multi-step voltage level unlike the voltage modulation method that has been conventionally adopted as a driving method of the liquid crystal display element, the above-mentioned liquid crystal display can be realized by a driving circuit having a simple structure. The element can be made to perform multi-tone gradation display.

Also in this embodiment, the current of the diode ring, which is the active element 2, is used as the liquid crystal display element.
If the one having abrupt voltage characteristics (thin film diode 5, 6 having a thin I-type semiconductor layer or having a small number of thin film diodes 5, 6) is used, the selection period T
By making S short, it is possible to perform time division driving with a larger number of time divisions.

In addition, in the driving method of this embodiment, as shown in FIG.
As shown in, the scanning signal SS supplied to the signal line 3 is
Either the positive or negative polarity selection potential V during the selection period TS
The data signal SD supplied to the counter electrode 4 is used as a signal for maintaining the C1 and maintaining the non-selection potential VC2 which is either positive or negative polarity during the non-selection period TO and is lower than the selection potential VC1 potential during the selection period TS. Has a number of pulses according to the data,
In addition, a signal in which the potential changes with an amplitude substantially equal to the positive side and the negative side with respect to the reference potential VG in a cycle that divides the selection period TS into two, that is, the area of the waveform on the positive side and the negative side with the reference potential VG as the center. The signal applied to the active element 2 between the input terminal and the counter electrode 4 during the non-selection period To has the same waveform area as that of the scanning signal SS as described above. The voltage of the waveform is such that the area of the waveform on the positive side and the area of the waveform on the negative side are substantially equal to each other around the selection potential VC2.

Therefore, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is, as shown in FIG. 17 to FIG. , A voltage value of the inter-electrode voltage VLC (hereinafter referred to as a reference holding voltage) V0 when the selection period TS ends,
V1L, V1H ... VnH is a voltage whose voltage value changes on the positive side and the negative side with substantially the same amplitude (amplitude of fluctuation due to the influence of image data applied to other pixels). That is, the non-selection voltage applied between the electrodes of the pixels during the non-selection period TO is the above-mentioned reference holding voltages V0, V1L, V1H ... VnH.
The area of the waveform on the positive side and the area of the waveform on the negative side are substantially equal to each other.

Therefore, the amount of change in the non-selection voltage applied between the electrodes of the pixels during the non-selection period TO is approximately equal to the amount of change in the negative side. Since the fluctuations of the voltages cancel each other out, the effective value of the inter-electrode voltage of the pixel in the non-selection period To is the above-mentioned reference holding voltage V0, V.
It is kept at 1L, V1H ... VnH and hardly changes.

Therefore, also in the driving method of this embodiment, the pixel transmittance is the voltage value V0 accumulated in the pixel capacitance CLC according to the number of pulses of the selection voltage applied in the selection period TS.
, V1L, V1H ... VnH are maintained, the pixel transmittance hardly changes during the non-selection period T0, and a correct gradation display according to the image data can be obtained. .. (Other application examples of the present invention)

In the first and second embodiments, the voltage value of the selection voltage has two levels, but the voltage value of the selection voltage may be selected in three or more levels. By increasing the number of stages of the voltage value and controlling the pulse width or the number of pulses for each voltage value, it is possible to perform gray scale display with more gray scales. However, even in this case, the number of steps of the voltage value of the selection voltage may be far smaller than that in the case of performing multi-tone gradation display only by voltage modulation.

Further, although the above-mentioned embodiments are intended for the liquid crystal display element using the diode ring as the active element 2, the driving method of the present invention is applied to the liquid crystal display element using the diode ring as the active element. The present invention is not limited to this, and can be widely applied to active matrix liquid crystal display elements using active elements made of nonlinear resistance elements having semiconductors, such as active elements having a back-to-back structure made of thin film diodes.

[0174]

According to the present invention, a liquid crystal display element using an active element composed of a non-linear resistance element having a semiconductor is driven by a modulation method in which modulation by voltage and modulation by pulse width or number of pulses are combined. Therefore, it is possible to cause the liquid crystal display element to perform gray scale display of multiple gray scales without using a drive signal having multiple voltage levels as in the conventional drive method.

Moreover, in the present invention, a selection voltage having either a positive or negative polarity of the pulse width or the number of pulses corresponding to the image data is provided between the drive signal input terminal of the active element and the counter electrode during the selection period. A waveform in which the potential changes in a cycle shorter than the selection period during the non-selection period during which the voltage is applied and other pixels are selected and the areas on the positive side and the negative side are approximately equal to each other with the potential of the scanning signal in the non-selection period as the center The voltage between the electrodes of the pixel due to the influence of the image data for driving other pixels during the non-selection period changes to the positive side with the potential of the scanning signal in the non-selection period as the center. The fluctuation of the voltage on the negative side and the fluctuation of the voltage on the negative side are almost equal to each other. Therefore, the effective value of the inter-electrode voltage of the pixel during the non-selection period, that is, the holding voltage of the pixel hardly changes. For driving With less variation in transmittance due to the influence of the image data, it is possible to obtain a display of the correct gradation corresponding to the image data.

[Brief description of drawings]

FIG. 1 is a waveform diagram of a voltage applied between a signal input terminal of an active element and a scanning signal, a data signal, and a counter electrode according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of various selection voltages applied between the input terminal of the active element and the counter electrode.

3 is a diagram showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage of FIG. 2 is applied.

FIG. 4 is a diagram illustrating a voltage applied between an input terminal of an active element and a counter electrode and a voltage applied between a pixel electrode and a counter electrode when a data signal applied during a selection period is a non-pulse signal. Waveform diagram of voltage.

FIG. 5 shows a voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied during the selection period is 1/10 of the selection period and the potential is at a low level. FIG. 3 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 6 shows a voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied in the selection period is 1/10 of the selection period and the potential thereof is at a high level. FIG. 3 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 7 shows the voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied during the selection period is 2.5 / 10 of the selection period and the potential is at a high level.
FIG. 3 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 8 shows a voltage applied between an input terminal of an active element and a counter electrode when a pulse width of a data signal applied in a selection period is a maximum width and its potential is at a high level, and a pixel electrode The wave form diagram of the voltage applied between the counter electrodes.

FIG. 9 is a plan view of a part of the liquid crystal display element.

FIG. 10 is an equivalent circuit diagram of one pixel display element of a liquid crystal display element.

FIG. 11 is a current-voltage characteristic diagram of a diode ring which is an active element and MIM.

FIG. 12 is a charge characteristic diagram of a pixel capacitance with respect to an applied voltage of a liquid crystal display element having a diode ring as an active element.

FIG. 13 is a pulse width-transmittance characteristic diagram of one pixel of the liquid crystal display element when driven by the driving method according to the first embodiment of the present invention.

FIG. 14 is a waveform chart showing another example of various selection voltages applied between the input terminal of the active element and the counter electrode.

15 is a diagram showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage of FIG. 14 is applied.

FIG. 16 is a waveform diagram of a voltage applied between a signal input terminal of an active element and a scanning signal, a data signal, and a counter electrode according to a second embodiment of the present invention.

FIG. 17 is a diagram showing a voltage applied between the input terminal of the active element and the counter electrode and a voltage applied between the pixel electrode and the counter electrode when the data signal applied during the selection period is a non-pulse signal. Waveform diagram of voltage.

FIG. 18 is a diagram showing the voltage applied between the input terminal of the active element and the counter electrode, the pixel electrode and the counter electrode when the number of pulses of the data signal applied in the selection period is 1 and the potential is low level. The wave form diagram of the voltage applied between and.

FIG. 19 shows the voltage applied between the input terminal of the active element and the counter electrode, the pixel electrode and the counter electrode when the number of pulses of the data signal applied in the selection period is 1 and the potential thereof is at a high level. The wave form diagram of the voltage applied between and.

FIG. 20 shows the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied in the selection period is the maximum allowable number of pulses and the potential thereof is at a low level; The wave form diagram of the voltage applied between an electrode and a counter electrode.

FIG. 21 is a diagram showing the pixel voltage and the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied in the selection period is the maximum allowable number of pulses and the potential is at a high level. The wave form diagram of the voltage applied between an electrode and a counter electrode.

[Explanation of symbols]

1 ... Pixel electrode, 2 ... Active element, 3 ... Signal line, 4 ... Counter electrode, TS ... Selection period, TO ... Non-selection period, SS ... Scan signal, AD ... Data signal, Va-c ... Input terminal of active element Voltage applied between the pixel electrode and the counter electrode, Vb-c ... Voltage applied between the pixel electrode and the counter electrode.

Claims (4)

[Claims] 1. A plurality of pixel electrodes arranged in a row direction and a column direction on one substrate of a pair of transparent substrates facing each other with a liquid crystal layer interposed therebetween, and semiconductors connected to these pixel electrodes, respectively. The liquid crystal display element, in which an active element including a nonlinear resistance element and a signal line for supplying a drive signal to the active element are provided, and a counter electrode facing the pixel electrode is provided on the other substrate, the pixel electrode In the method of sequentially selecting a plurality of pixels formed by the counter electrode and the liquid crystal between the counter electrode and time-division driving, between the drive signal input end of the active element and the counter electrode, an image during the selection period is displayed. In the non-selection period in which a voltage having a polarity corresponding to the data or a positive or negative polarity of the pulse width is applied and other pixels are selected, the potential changes in a cycle shorter than the selection period and Pair with signal line Method of driving a liquid crystal display element characterized by the area of the positive side and the negative side about the potential of the non-selection period of one to supply scan signals to the electrodes to apply a voltage of approximately equal waveform. 2. The potential of one of the positive and negative polarities is maintained on one of the signal line and the counter electrode during the selection period, and has either positive or negative polarity during the non-selection period and is higher than the potential during the selection period. A scanning signal that keeps a low potential is supplied, and on the other hand, it has a potential and a pulse width according to the image data, and the amplitude is almost equal to the positive and negative sides with respect to the reference potential in a cycle in which the selection period is divided into a plurality of periods. The method of driving a liquid crystal display element according to claim 1, wherein a data signal whose potential changes is supplied. 3. A plurality of pixel electrodes arranged in a row direction and a column direction on one substrate of a pair of transparent substrates facing each other with a liquid crystal layer in between, and semiconductors connected to each of these pixel electrodes. The liquid crystal display element, in which an active element including a nonlinear resistance element and a signal line for supplying a drive signal to the active element are provided, and a counter electrode facing the pixel electrode is provided on the other substrate, the pixel electrode In the method of sequentially selecting a plurality of pixels formed by the counter electrode and the liquid crystal between the counter electrode and time-division driving, a method is provided between the drive signal input end of the active element and the counter electrode, and In the non-selection period in which a voltage having a polarity corresponding to the data or a positive or negative polarity of the pulse number is applied and other pixels are selected, the potential changes in a cycle shorter than the selection period, and Pair with signal line Method of driving a liquid crystal display element characterized by the area of the positive side and the negative side about the potential of the non-selection period of one to supply scan signals to the electrodes to apply a voltage of approximately equal waveform. 4. The potential of one of the positive and negative polarities is maintained on one of the signal line and the counter electrode during the selection period, and is either positive or negative during the non-selection period, and is higher than the potential during the selection period. A scanning signal that keeps a low potential is supplied, and on the other hand, the potential and the number of pulses corresponding to the image data are provided, and the amplitude is approximately equal to the positive and negative sides with respect to the reference potential in a cycle in which the selection period is divided into a plurality of periods. The method for driving a liquid crystal display element according to claim 3, wherein a data signal whose potential changes is supplied.