JPH0567606A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a semiconductor device having at least two upper and lower insulating films, the insulating films can be reflow-treated under substantially the same conditions, and the lower insulating layer can be insulated when the upper insulating film is reflow-treated. Provided is a method for manufacturing a semiconductor device in which a film does not reflow. [Structure] After forming a lower insulating film and performing reflow treatment, impurities are introduced into the lower insulating film, and then,
An upper insulating film is formed and a reflow process is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of planarizing an integrated circuit structure in the semiconductor device.

[0002]

2. Description of the Related Art In integrated circuits, as the degree of integration increases, the number of polysilicon layers or polycide layers tends to increase. For example, a 4M bit DRAM has a four layer polysilicon structure. A transfer transistor portion, which is a word line, is formed in the first polysilicon layer.
A charge storage electrode of a capacitor is formed on the second polysilicon layer, a plate electrode is formed on the third polysilicon layer, and a bit line is formed on the fourth polysilicon layer. With such a multi-layer structure, it becomes difficult to form a pattern in the upper polysilicon layer because it is affected by the unevenness or steps of the lower polysilicon layer. Particularly when the upper polysilicon layer is etched by the RIE method, the polysilicon of the upper polysilicon layer remains in a sidewall shape along the edge portion of the step of the lower polysilicon layer, and as a result, the adjacent pattern is There is a problem of short circuit. It is also possible to replace these polysilicon layers with polycide layers.

Therefore, it is an important subject to plan the flattening of the integrated circuit structure as the density of the integrated circuit increases. One of the flattening techniques is a reflow technique. This technique is a reflow process by heat treatment after forming an insulating film made of, for example, BPSG (Boro-Phospho-Silicate Glass) on a polysilicon layer or a polycide layer (hereinafter also simply referred to as a polysilicon layer) having steps or irregularities. The insulating film is reflowed to flatten the steps or irregularities on the surface of the polysilicon layer or the like. After that, a polysilicon layer or the like may be further formed on the insulating film,
The reflowed insulating film absorbs steps or irregularities on the surface of the polysilicon layer or the like.

For example, in the example of the above-mentioned 4 Mbit DRAM, after patterning the third polysilicon layer or the like,
A lower insulating film made of, for example, BPSG is formed thereon, and then the lower insulating film is subjected to reflow treatment.
As a result, the lower insulating film absorbs steps or irregularities of the third polysilicon layer or the like. Then, a contact window for the bit line is opened through the lower insulating film so as to reach the diffusion layer. Subsequently, a fourth-layer polysilicon layer or the like is formed on the lower insulating film, and then the fourth-layer polysilicon layer or the like is patterned. Since the steps or irregularities on the surface of the third polysilicon layer or the like are flattened by the reflow treatment of the lower insulating film, the fourth polysilicon layer or the like is formed by the RIE method and without much overetching. , Can be finely patterned.

[0005]

Next, an upper insulating film made of, for example, BPSG is formed on the fourth polysilicon layer or the like. Then, an aluminum electrode window is opened in the upper insulating film, the upper insulating film is subjected to reflow treatment, and then an aluminum electrode is formed. Here, when the upper insulating film is reflow-treated, the lower insulating film is also reflowed. As a result of the reflow of the lower insulating film, there arises a problem that the fourth polysilicon layer or the like formed thereon moves or bends.

As one means for preventing the lower insulating film from reflowing when the upper insulating film is reflow-treated, the concentrations of impurities (for example, boron and phosphorus) in the lower and upper insulating films are changed. It can be mentioned. That is, the concentrations of impurities in the lower and upper insulating films may be changed so that the lower insulating film reflows at a higher temperature than the upper insulating film.

However, such a method is not a preferable method. The reason is that BP with different impurity concentration is used.
This is because two insulating film forming devices are required to form the SG insulating film. Further, when two kinds of BPSG insulating films having different impurity concentrations are formed by one insulating film forming apparatus, there is a problem that an error in the impurity concentration management is likely to occur. Therefore, the above method is not a preferable method from the viewpoint of the productivity of the semiconductor device.

Furthermore, the above method is not suitable for high integration of semiconductor devices. In the conventional manufacturing method using only one BPSG insulating film, the reflow treatment of the BPSG insulating film is performed at about 900 ° C. for about 30 minutes. On the other hand, even in the above-described method using the two-layer BPSG insulating film, the two reflow processes need to be performed at about 900 ° C. and the total reflow process time needs to be about 30 minutes. In this time, smoothing cannot be sufficiently performed.
In addition, the lower insulating film has a higher temperature than the upper insulating film, for example, 9
In the method of performing the reflow process at 50 ° C., there arises a problem that X _{j of} the diffusion layer becomes deep and the source / drain of the transistor is punched through.

According to the present invention, in a semiconductor device having at least two upper and lower insulating films, the insulating films can be reflow-treated under substantially the same conditions, and when the upper insulating film is reflow-treated, the lower insulating film is removed. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not reflow.

[0010]

According to the present invention, the above object is to form an insulating film of a lower layer, perform reflow treatment, and then introduce impurities into the insulating film of the lower layer.
This is achieved by forming an upper insulating film and performing reflow treatment.

It is preferable that the two upper and lower insulating films are made of BPSG, and that the boron and phosphorus concentrations in the lower insulating film and the upper insulating film before the reflow treatment are substantially the same. The concentration of phosphorus and boron in BPSG was 7
± 3 atomic wt% and 3 ± 1.5 atomic wt% are preferable.

The introduction of impurities into the lower insulating film can be carried out by using a gas diffusion method, but it is preferably carried out by an ion implantation method. When the ion implantation method is used, the impurities include boron ions, phosphorus ions, arsenic ions, and BF.
_Two ions or a combination of these ions can be used. When these ions are used alone, the concentration of impurities is 1 × 10 ¹⁵ cm ^{-2 to} 3 × 10 ^16.
It is desirable to be cm ⁻² . Also, phosphorus ion and B
When F ₂ ions are combined, their respective concentration ranges are preferably 1 × 10 ¹⁵ cm ^{−2 to} 1 × 10 ¹⁶ cm ⁻² . Further, when using the gas diffusion method, BBr ₃ can be used as an impurity.

After the introduction of impurities, the insulating film is heat-treated,
It is also possible to diffuse the impurities in the lower insulating film and uniformly distribute them.

[0014]

In the method of the present invention, after the lower insulating film is formed and the reflow process is performed, impurities are introduced into the lower insulating film. As a result, the content of impurities in the lower insulating film is increased, and the temperature at which the lower insulating film starts reflow can be increased. Therefore, even if the reflow processing conditions of the lower insulating film and the upper insulating film are made substantially the same, it is possible to prevent the lower insulating film from reflowing during the reflow processing of the upper insulating film.

[0015]

DETAILED DESCRIPTION A 4M bit D with a four layer polysilicon structure.
The method of the present invention was applied to the RAM manufacturing process. This DR
In the AM, a transfer transistor portion, which is a word line, is formed in the first polysilicon layer by a known process, and a charge storage electrode of a capacitor is formed in the second polysilicon layer. Plate electrodes are formed on the three polysilicon layers. A lower insulating layer made of BPSG was formed on the third polysilicon layer. The phosphorus concentration in the lower insulating layer was 7 atomic wt% and the boron concentration was 3 atomic wt%. The formation of the lower insulating layer
It was performed by the CVD method. Then, a reflow process was performed on the lower insulating film at 900 ° C. for 20 minutes.

Then, an impurity implantation process was performed on the lower insulating film by an ion implantation method. Ion implantation conditions were BF ₂ ions: 50 KeV 3 × 10 ¹⁵ cm ⁻² and P (phosphorus) ions: 70 KeV 2 × 10 ¹⁵ cm ⁻² . After the ion implantation, heat treatment was performed at 850 ° C. for 20 minutes to diffuse the above-mentioned impurities introduced by the ion implantation method in the lower insulating layer and uniformly distribute them.

After that, a contact window for the bit line is opened through the lower insulating film so as to reach the diffusion layer. Then, a fourth polysilicon layer is formed on the lower insulating film,
Then, the fourth polysilicon layer was patterned by the RIE method to form a bit line. Then, an upper insulating film made of BPSG was formed on the fourth polysilicon layer by the CVD method. As in the lower layer, the phosphorus concentration in the upper insulating layer is 7 atomic wt% and the boron concentration is 3 a.
It was set to tomic wt%. Then, an aluminum electrode window was opened in the upper insulating film, and then the upper insulating film was subjected to reflow treatment. The reflow treatment conditions were the same as those of the lower insulating film, that is, 900 ° C. for 20 minutes. Even under such reflow processing conditions, the lower insulating film did not reflow, and the fourth polysilicon layer formed thereon did not move or bend. Then, an aluminum electrode was formed to complete a 4M bit DRAM.

Impurities may be introduced into the lower insulating film over the entire surface of the lower insulating layer, or the impurities may be introduced into only necessary portions using a mask.

The application of the method of the present invention to the manufacturing process of DRAM has been described above.
Can also be applied to the manufacturing process of. Even in SRAMs, there is a tendency toward four-layer polysilicon. That is, the gate electrode of the transistor is formed on the first polysilicon layer, the Vss wiring is formed on the second polysilicon layer, and the TFT transistor is formed on the third and fourth polysilicon layers. In this case, BPSG is formed on the second polysilicon layer.
After a lower insulating film made of is formed and subjected to a reflow treatment, impurities are introduced into the lower insulating film.

After that, a third layer and a fourth layer are formed on the lower insulating film.
A polysilicon layer is formed to form a TFT transistor. After forming the TFT transistor, B
Although an upper insulating film made of PSG is formed and a reflow process is performed, the BPSG in the lower layer is not reflowed.
The transistor does not move. After that, the SRAM is completed through a normal process.

[0021]

According to the method of the present invention, since the impurity concentration contained in the lower insulating film is different from the impurity concentration contained in the upper insulating film, when the upper insulating film is reflowed, The lower insulating film does not reflow.
Therefore, it is possible to prevent the phenomenon that the polysilicon layer or the like existing on the lower insulating film moves or bends, and it is possible to prevent the deterioration of the quality and the yield of the semiconductor device. Also,
The allowable range of the heat treatment temperature and the like in the semiconductor device manufacturing process after the process according to the method of the present invention can be expanded.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having at least two upper and lower insulating films, wherein an insulating film of a lower layer is formed and a reflow process is performed, and then impurities are introduced into the insulating film of the lower layer. Thereafter, a method for manufacturing a semiconductor device is characterized in that an upper insulating film is formed and a reflow treatment is performed. 2. The upper and lower insulating films are made of BPSG, and the boron and phosphorus concentrations in the lower insulating film and the upper insulating film before reflow treatment are substantially the same. A method of manufacturing a semiconductor device according to item 1.