JPH0568154B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a signal that is associated with a signal having a certain width, such as a burst gate signal that is associated with a horizontal synchronization signal in the case of a video signal. It relates to a circuit suitable for generating this.

Conventional configuration and its problems It is necessary to generate a signal such as a blanking signal, burst gate signal, or pedestal clamp signal along with a signal having a certain width such as a synchronization signal in a video signal. There may be cases. For example, a blanking signal is used to inhibit the output of a video signal during a horizontal blanking interval. Furthermore, when processing color video signals, a burst gate signal is used to extract the burst signal added after the synchronization signal and process various color signals. Furthermore, a pedestal clamp signal is used to clamp the luminance signal to a specific potential in order to reproduce the DC component of the luminance signal and perform various processing.

An example of such a signal is shown in FIG. Figure a shows the horizontal synchronizing signal of the video signal and its preceding and following parts. b indicates a horizontal synchronization signal that has been synchronously separated. c.
indicates a blanking signal. d indicates a burst gate signal, which has a certain relationship with the horizontal synchronizing signal, and is generally created with the horizontal synchronizing signal as a reference. This signal can also be used as a pedestal clamp signal.

By the way, if strictness is not required, instead of these signals, as shown in figure e, the synchronization signal becomes "High" at the start point and becomes "Low" almost at the end of the blanking section. A signal such as that shown in f is used as a blanking signal, or a signal that becomes "High" at the end of the synchronization signal and becomes "Low" in the blanking section after the burst signal is used as a burst gate signal or pedestal signal. It may also be used as a clamp signal.

FIG. 2 shows a conventional example of a circuit for generating a signal such as that shown in FIG. 1 e or f. A video signal is input to a terminal 1, and a synchronization signal is separated by a synchronization separation circuit 2. 3 is a constant current source, and 4 is a switch circuit that is closed during a period when no synchronizing signal is input. These 3 and 4 constitute a current source that operates when no synchronizing signal is input.

Now, assuming that no synchronization signal is input for a sufficiently long period, the capacitor 7 is charged by the constant current source 3, and the voltage at the terminal 15 is equal to the voltage of the constant voltage source 9 and the forward direction of the diode 9. The voltage is fixed to the sum of the voltages. 6 is a constant current source, and 5 is a switch circuit that closes during the synchronization signal period. These 5 and 6 constitute a current source that operates when a synchronizing signal is input. 10 is a voltage comparator, 11 is a logic circuit, and 12 is an output terminal.

FIG. 3 is an explanatory diagram showing the operation of FIG. 2.
Figure a shows the synchronization signal separated by the synchronization separation circuit 2. b indicates the voltage at terminal 15. The voltage V ₀ before the synchronization signal is input is the voltage of the voltage source 9 V ₉ ,
If the forward voltage of diode 8 is V _D8 , then V ₀
=V ₉ +V _D8 ...(1) It is expressed as follows. The current of constant current source 6 is I ₆ , the length of the synchronizing signal section is T ₁ , and the capacitance value of capacitor 7 is C ₇
Then, the amount of voltage change ΔV ₁ at the terminal 15 during the synchronization signal period is ΔV ₁ =I ₆ ·T ₁ /C (2). Next, when the time required for the voltage at the terminal 15 to return to V ₀ after the synchronization signal ends is T ₂ and the current from the current source 3 is I ₃ , equation (3) holds true.

ΔV ₁ =I ₃ ·T ₂ /C (3) From formulas (2) and (3), T ₂ =I ₆ ·T ₁ /I ₃ (4) is expressed.

From equation (4), T ₁ is a value unique to the video signal, so I ₆ and I ₃
By appropriately selecting the ratio of , the value of T ₂ can be arbitrarily selected. Voltage comparator 10 has terminal 15
It is detected that the voltage has become slightly lower than the voltage V ₀ determined by equation (1). FIG. 3c shows the output of the voltage comparator 10. As mentioned above, this signal
It can be used as a blanking signal. Logic circuit 11 operates as an exclusive OR circuit and outputs the signal shown in FIG. 3d. The period during which this signal is "High" is approximately _T2 , and the value of _T2 can be arbitrarily set by appropriately selecting the ratio of _I3 and _I6 . This signal corresponds to the signal shown in FIG. 1d, and can be used, for example, as a burst gate signal or a pedestal clamp signal.

Next, an example of the voltage comparator 10 is shown in FIG. In the figure, 7, 8, 9 and 15 are the same as in FIG. Transistor 23, 24, 25, 3
0, resistors 26, 29, 31, and a constant voltage source 32, the circuit compares the base voltages of transistors 23 and 24, and when the base voltage of transistor 23 becomes lower than the base voltage of transistor 24, a voltage is applied to terminal 33. Outputs “High” voltage. The diode 20, the transistor 27, and the resistors 21, 22, and 28 are a circuit that generates a voltage slightly lower than the aforementioned _V0 .

By the way, in the example shown in FIG.
When is output, the transistor 23 is conductive and its base current I _BQ23 flows. This current becomes a charging current for capacitor 7, so when this effect is taken into consideration, terminal 12 in Figure 2
From equation _{( 4} ), _the period _{T 20 of the} output signal _obtained by However, an error occurs. This error becomes particularly noticeable when the circuit shown in FIG. 2 is integrated into an IC. In other words, since only a small capacitance capacitor can be realized inside the IC, I ₃ and I ₆ must be set small to make ΔV ₁ shown in equation (2) or (3) an appropriate value, and I _BQ23
This is because the influence of this cannot be ignored.

Furthermore, in order to generate a voltage slightly lower than the above-mentioned V ₀ , a special circuit is required as mentioned above, and the total number of elements increases.

Purpose of the Invention The present invention eliminates the negative effect of a voltage comparator on a capacitor charging/discharging circuit as in the conventional example, and significantly simplifies the circuit configuration by using a voltage comparator attached to a signal having a constant width. An object of the present invention is to provide a signal generating device that generates a signal.

Structure of the Invention The structure of the present invention is that the emitter is connected to a capacitor that is charged and discharged, a constant voltage source is connected to the base, and the output is taken out from the collector by a transistor. The above object is achieved by configuring a voltage comparison circuit and setting the initial voltage of the capacitor such that the charge is sufficiently discharged by this transistor.

DESCRIPTION OF THE EMBODIMENT FIG. 5 shows an embodiment of the invention. In this figure, the same elements as in FIG. 2 are given the same numbers. The emitter of a transistor 40 is connected to the contact 15. Also transistor 40
A constant voltage source 42 is connected to its base, and a resistor 41 and the base of a transistor 30 are connected to its collector. The emitter of transistor 30 is
It is grounded and the collector is connected to the power supply through a resistor 31. The collector output of transistor 30 corresponds to the output of voltage comparator 10 in FIG. 2 and is connected to logic circuit 11.

The operation shown in FIG. 5 will be explained below. As in the case of Figure 2, in the section before the synchronization signal is input,
The capacitor 7 is charged by the current from the constant current source 3, and after a sufficient period of time, the voltage at the terminal 15 becomes
The voltage is fixed to V ₀₁ determined by equation (6).

V ₀₁ =V _BEQ40 +V ₄₂ (6) Here, V _BEQ40 is the base-emitter voltage of the transistor 40, and V ₄₂ is the voltage of the constant voltage source 42. At this time, the current from the constant current source 3 flows from the emitter to the collector of the transistor 40 and then flows into the resistor 41. This current causes resistance 4
A voltage is generated across the transistor 1, turning the transistor 30 "ON", and the collector voltage of the transistor 30 becomes approximately ground potential.

On the other hand, when a synchronization signal is input, switch 4 opens and switch 5 closes, so that the capacitor 7 starts to be discharged by the current from the constant current source 6 and the contact 15
voltage begins to drop. When the capacitor 7 begins to discharge, the transistor 40 is immediately cut off, so that no current flows through its collector, and both ends of the resistor 41 are at ground potential. Therefore, transistor 30 is turned "OFF" and its collector voltage becomes equal to the power supply voltage.

Next, when the synchronization signal section ends, capacitor 7
begins to be charged again by the current source 3, and the voltage at terminal 15 increases. The voltage at contact 15 is restored
When the voltage reaches V ₀₁ , the transistor 40 becomes conductive, the voltage at the contact 15 is fixed at V ₀₁ , and the current from the constant current source 3 is outputted through the emitter of the transistor 40 to the collector. At this time, the collector voltage of the transistor 30 becomes the ground voltage as described above. The collector output of transistor 30 is input to logic circuit 11. At this time, the waveform of the synchronizing signal, the voltage of contact 15, the voltage of transistor 30
The collector voltage and the output voltage of the logic circuit 11 correspond to a, b, c, and d in FIG. 3, respectively. Here, c can be used as a blanking signal, and d can be used as a burst gate signal or pedestal clamp signal.

By the way, in the embodiment of the present invention shown in FIG. 5, the transistor 40 is in a cut-off state in a section where the voltage of the capacitor 7 is lower than V ₀₁ . Therefore, the transistor 40 does not affect the charging and discharging time constants of the capacitor 7 unlike in the conventional example, and the width of the signal output to the terminal 12 is correct for the value determined by equation (4). can get.

On the other hand, the circuit composed of 40, 41, 42 in FIG. 5 is 8, 9, 20, 21, 22,
This corresponds to a circuit composed of 23, 24, 25, 26, 27, 28, and 32, and the number of elements is significantly reduced.

In addition, in FIG. 5, the switch circuit 4 closes when the synchronization signal is input, and the switch circuit 5 closes when the synchronization signal is input.
It is clear that when configured to close when no synchronization signal is input, signals such as blanking signals, burst gate signals, pedestal clamp signals, etc. can be easily generated by replacing transistor 40 with an NPN transistor. be.

Effects of the Invention According to the present invention, an emitter is connected to a capacitor that is charged and discharged in accordance with an input signal, a constant voltage is supplied to the base, and a transistor is provided to take out a signal from the collector, resulting in a simple configuration. , has characteristics as designed values,
It is possible to obtain a signal associated with a signal having a certain width.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing an example of a synchronization signal in a video signal and a signal accompanying the synchronization signal, Fig. 2 is a circuit diagram of a conventional example that generates a signal accompanying the synchronization signal, and Fig. 3 is a waveform diagram showing an example of a synchronization signal and a signal accompanying the synchronization signal. FIG. 4 is a circuit diagram showing a conventional voltage comparator and its surroundings, and FIG. 5 is a circuit diagram showing an embodiment of the present invention. 2... Synchronous separation circuit, 3... Constant current source, 4...
Switch circuit that closes in sections other than synchronous signals, 5...
...Switch circuit that closes in the synchronization signal section, 6... Constant current source, 7... Capacitor, 10... Voltage comparator, 11... Logic circuit, 40... Transistor, 41... Resistor, 42... Constant voltage source .

Claims (1)

[Scope of Claims] 1: a first current source; a second current source having a polarity opposite to that of the first current source; and when a synchronization signal having a certain width is input, the first current source a first switch circuit that allows the current of the second current source to pass through when a synchronization signal having a certain width is not input;
and a capacitor commonly connected to a second switch circuit, an emitter connected to a connection point between the capacitor and the first and second switch circuits, a base connected to a constant voltage source, and a signal taken out from the collector. A signal generation circuit characterized in that it is composed of transistors. 2. Signal generation characterized in that a signal accompanying the synchronization signal is generated based on the synchronization signal having a certain width and the signal taken out from the collector of the transistor according to claim 1. circuit.