JPH0568210A - Solid-state image pickup device - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the influence of aliasing due to sampling of high-frequency noise in the output amplifier of a solid-state image sensor. A read-out of the solid-state image pickup device 101 is made slower than a television rate, the read signal is band-limited by a low-pass filter 2, and the CDS circuit 301 performs a CDS process on the band-limited output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device for performing a CDS process for reducing output noise of a solid-state image pickup device.

[0002]

2. Description of the Related Art A conventional means for reducing output noise of a solid-state image pickup device in a solid-state image pickup device such as an electronic still camera will be described below.

First, the structure and operation of an electronic still camera, which is an example of a solid-state image pickup device, will be described. Figure 5
2 is a block diagram of an electronic still camera, in which 201 is a lens, 202 is a diaphragm, 203 is a shutter, and 204 is a shutter diaphragm drive circuit. Reference numeral 101 is a solid-state image sensor for converting an image into an electric signal, 205 is a solid-state image sensor drive circuit, and 206 is a clock generation circuit. A signal processing circuit 207 obtains a luminance signal and a color-difference line-sequential signal by performing signal processing on the output obtained from the solid-state imaging device 101. Reference numeral 208 denotes an FM modulation circuit that FM-modulates the luminance signal and the color difference line sequential signal. A REC amplifier 209 amplifies the FM-modulated signal so that it can be magnetically recorded. 210 is a magnetic head, and 211 is a magnetic sheet that is a recording medium. 212
Is a motor for rotating the magnetic sheet 211, 213 is a motor servo circuit, and 214 is a system control circuit for controlling the operation of the entire system. Reference numeral 215 is a shutter release switch, and a series of still image capturing sequences is performed in synchronization with the operation of turning on the switch.

FIG. 6 shows an imaging sequence of an electronic still camera. In FIG. 6, the unnecessary charges in the A field of the solid-state image sensor 101 are transferred and removed while the shutter 203 remains closed at time T1. Similarly, from time T2, B
Transfer and remove unnecessary charges in the field. Next time T3
The solid-state image sensor 1 with the shutter 203 opened between T4 and T4.
01 is exposed to accumulate signal charges. Next, the shutter 203 is closed, and the electric field of the A field is read out and the signal processed signal is recorded in the nth track of the magnetic sheet 211 between times T4 and T5. Next, between times T5 and T6, the electric field of the B field is read out and the signal processed is recorded on the (n + 1) th track of the magnetic sheet 211.

Next, the structure and operation of the solid-state image sensor used in the electronic still camera will be described.

FIG. 7 shows an interline CCD as an example of a solid-state image pickup element often used in electronic still cameras.
FIG. In FIG. 7, 101 is a solid-state image sensor that is an interline CCD, 102 is a photodiode that converts light into electric charge and accumulates, and 103 is a vertical that vertically transfers the electric charge transferred from the photodiode 102 to 1H step by step. It is a CCD. V1 to V4 are vertical CCD 10
3 is a transfer electrode, and V1 also serves as a transfer gate for transferring the charges in the odd rows of the photodiodes to the vertical CCD 103. Similarly, V3 is a transfer gate corresponding to the photodiodes in even rows. Vertical CCD 103
Are driven by four-phase transfer pulses. 104 is a vertical CCD
It is a horizontal CCD that horizontally transfers the charges transferred from the 103 to 1H by one stage. H1 and H2 are horizontal CCD 104
, And is driven by a two-phase pulse. 105
Is an FDA (Floating Diffus) that converts electric charge into voltage and outputs it.
ion Amplifier). A floating diffusion layer (not shown) is provided at the final stage of the horizontal CCD 104, and the potential change at the final stage is detected by the output amplifier 105. Such a charge detection amplifier is called FDA. Vout is an output terminal. Reference numeral R is a reset gate electrode for removing the charges that have been read and resetting the output potential to the reference potential every clock cycle.

FIG. 8 is a diagram showing the read timing of the interline CCD of FIG. At time t1, the vertical blanking period starts, and at time t2, V1 becomes high level and the transfer gate opens, so that the charges in the odd rows of the photodiodes 102 are transferred to the vertical CCD 103. From time t3, the charges of the vertical CCD 103 are transferred toward the first-stage horizontal CCD 104 in one horizontal period. Horizontal CC
The electric charges transferred to D104 are transferred at high speed to FDA10.
It is converted into a voltage at 5 and output. The reading of charges from all odd-numbered lines ends at time t4. Next, at time t5 of the vertical blanking period, V3 becomes high level, the charges of the photodiodes 102 on even lines are transferred to the vertical CCD 103, and one line horizontal CCD is generated in one horizontal period from time t6.
The data is transferred to 104 and similarly transferred at high speed and output.

Since the output amplifier of the solid-state image pickup device as described above generates a peculiar noise called reset noise, the noise is usually reduced by using a technique called CDS (Corelated Double Sampling).

FIG. 9 is a timing chart for reading charges from the horizontal CCD 104. As shown in FIG. 9C, the reset pulse R resets the output potential of the FDA 105 to the reference potential. When the reset pulse R becomes low level, the floating diffusion layer of the FDA 105 enters a floating state, and the output potential of the FDA 105 is maintained at a predetermined voltage determined by the capacitance division ratio of the floating capacitance of the floating diffusion layer. This period is called a feedthrough period.

Next, as shown in FIG. 9B, when the horizontal transfer pulse H2 becomes low level, the signal charge is transferred to the final stage having the floating diffusion layer, and the signal charge is divided by the capacitance of the floating diffusion layer. The voltage change of is output from the FDA 105. However, the potential during the feedthrough period is affected by thermal noise during the reset period as shown in FIG.
It varies for each pixel period. Then, the potential of the signal period also varies accordingly. Such FDA-specific noise is called reset noise. This noise can be removed by taking the difference in potential between the signal period and the feedthrough period preceding it. Such a method is called CDS.

FIG. 10 is a diagram for explaining the configuration of a CDS circuit for performing CDS. As shown in FIG. 10A, the output signal of the solid-state imaging device 101 is sent to the subsequent stage after noise removal by the CDS circuit 301. As the configuration of the CDS circuit 301, the configurations shown in FIGS. 10B and 10C are often used. In FIG. 10B, the CDS circuit 301 is composed of a clamp circuit 302 and a sample hold circuit 303. The pulse P1 is used for clamping and the pulse P2 is used for sampling and holding. The timings of P1 and P2 are shown in FIGS. 9 (e) and 9 (f). First, the potential in the feedthrough period is clamped by the clamp circuit 302 with the pulse P1, the potential is fixed to a predetermined potential to eliminate the influence of reset noise, and then the potential in the signal period is sampled and held by the sample hold circuit 303 with the pulse P2. To get a noise free signal.

In FIG. 10C, the CSD circuit 301 has the first
The sample hold circuit 304, the second sample hold circuit 305, the third sample hold circuit 306, and the subtraction circuit 307. P2 is set in the first sample hold circuit 304 and the third sample hold circuit 306.
Pulse is added. A pulse P1 is applied to the second sample hold circuit 305. P1,
The timing of P2 is shown in FIGS. 9 (e) and 9 (f). First, the potential in the feed-through period is sampled and held by the second sample and hold circuit 305 by the pulse P1 and delayed. Next, the potential of the signal period and the potential of the delayed feed-through period are sampled and held by the first sample hold circuit 304 and the third sample hold circuit 306 at the timing of the pulse P2, and the subtraction circuit 3
The reset noise component is removed by subtracting at 07.

[0013]

CCD in principle
Although the CDS is supposed to be able to completely remove the noise, the noise of the solid-state image sensor cannot be completely removed.
The first cause is that the number of pixels in the recent solid-state imaging device is large and the reading frequency is high, so that the feed-through period and the signal period are very short, and it is difficult to perform clamp and sample hold accurately. The second cause is that noise in a high band other than reset noise is added by the FDA, so that the clamp circuit or the sample hold circuit clamps or holds the noise added uncorrelated with the reset noise. Will occur. FIG. 11 is a diagram for explaining how the noise reduction effect is impaired by the CDS turning back to the low frequency range when FDA high frequency noise is present.

In FIG. 11, it is assumed that the sampling frequency of the CDS is f _s and the noise band f _Nmax of the output amplifier is also f _s . Due to the noise reflected by the CDS sampling, the noise in the feed-through period and the noise in the signal processing period are each √2 times. Furthermore, even if the reset noise is completely canceled by subtracting uncorrelated noise, the high frequency noise of the output amplifier becomes twice the original noise. Actually, noise in a band exceeding f _s exists in the output amplifier of the solid-state image pickup device, so that the noise further increases.

[0015]

In the solid-state image pickup device of the present invention, the reading of the solid-state image pickup element is made slower than the television rate, the read signal is band-limited by a low-pass filter, and the band-limited output signal is obtained. The CDS processing is performed on

[0016]

[Operation] According to the present invention, the reading rate of the solid-state image sensor is reduced, and the noise of the solid-state image sensor is further reduced by performing CDS after removing the noise of the output amplifier by a low-pass filter.

In the solid-state image pickup device of the present invention, when it is necessary to perform signal processing at a television rate, a CD is used.
After S processing, A / D conversion may be performed, the A / D converted signal may be stored in a memory, and converted again to a television rate.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, only changed or added portions of the block diagram of the electronic still camera of FIG. 5 and portions necessary for explanation are shown.

In FIG. 1, reference numeral 1 is a clock generation circuit having a function of slowing down a horizontal read clock.
Reference numeral 2 is a low-pass filter for removing high-frequency components of noise of the output amplifier of the solid-state image sensor 101, and 3 is a CDS circuit 301.
An A / D converter circuit 4 for converting the output of the above into a digital value is a frame memory. Reference numeral 5 is a D / A conversion circuit for converting the data in the frame memory 4 into an analog value. The output of the D / A conversion circuit 5 is connected to the image pickup signal processing circuit 207 of FIG. 5 for signal processing.

FIG. 2 is an operation sequence diagram of the embodiment shown in FIG. FIG. 3 is an explanatory diagram of horizontal read timing in the embodiment of FIG. For comparison, FIG. 3 (a)
(F) shows a conventional timing example.

The operation of this embodiment will be described with reference to FIGS. 1, 2, 3, and 5. From time T1 to time T2 in FIG. 2, unnecessary charges in the A field of the solid-state image sensor 101 are swept and cleared. Next, from time T2 'to time T3, unnecessary charges in the B field are swept out and cleared. The shutter 203 is opened between times T3 and T4 to expose the solid-state image sensor 101. After the shutter is closed and the exposure is completed, the signal charge of the A field of the solid-state image sensor 101 is read out from time T4 to T5 '. Next, from time T5 'to T6', the signal charge of the B field of the solid-state image sensor 101 is read. Reading of the A and B fields is performed at a speed lower than the television rate. Here, from time T2 after clearing the A field to B
In the present invention, the A and B fields are read out at a low speed because a certain interval is provided before the field clear start time T2 '. Therefore, in the imaging sequence of FIG. This is because the time until the start differs between the A field and the B field, which causes a difference in generated noise.

For low-speed reading, the horizontal transfer pulse and reset pulse periods are set to H2 'and R'as shown in FIGS. 3 (g) and 3 (f).
By making it longer. The high-pass noise of the output amplifier of the solid-state imaging device 101 is cut as shown in FIG. 3 (j) by band-limiting the signal read at a low speed by the low-pass filter 2 and then input to the CDS circuit 301 to cause reset noise. To be removed. The signal from which the reset noise is removed is converted into a digital value by the A / D conversion circuit 3 and stored in the frame memory 4. From time T6 ', the data of the A field is read from the frame memory 4 at the television rate, converted into an analog value by the D / A conversion circuit 5, and processed by the imaging signal processing circuit 207.
The data is recorded on the magnetic disk 211. From time T7, the B field data is read from the frame memory 4 at the television rate, converted into an analog value by the D / A conversion circuit 5, processed by the imaging signal processing circuit 207, and then the magnetic disk 211.
To record. FIG. 4A shows the return of the high-frequency noise when the high-frequency noise is band-limited to f ′ _Nmax by low-pass filter processing after low-speed reading. When this signal is read out from the memory, the time axis is restored and the noise energy is kept constant, so the amplitude spectrum of the noise becomes one half of the route when low-pass processing is not performed.

In the embodiment described above, since analog recording is performed, it is once digitized and then converted into analog information again. However, the present invention is also applicable to digital recording such as a card camera. Applicable,
In such a case, it is not necessary to return the time axis to the TV rate,
Digital signal processing may be performed after A / D conversion processing and recorded on a digital recording medium.

One of the features of the present invention is that the reading speed of the solid-state image sensor is slower than the television rate. However, for high-definition use, the number of pixels of the solid-state image sensor is further increased. In the conventional solid-state image pickup device shown in (1), the read-out frequency becomes high and the feed-through period and the signal period become shorter, so that the present invention is more preferably used.

[0026]

As described in detail above, according to the present invention, it is possible to reduce the influence of aliasing due to sampling of high frequency noise in the output amplifier of the solid-state image pickup device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation sequence diagram of the embodiment of FIG.

FIG. 3 is an explanatory diagram of horizontal read timing in the embodiment of FIG.

FIG. 4 is a diagram for explaining the influence of the return of noise to the low frequency band due to CDS when there is high frequency noise of FDA.

FIG. 5 is a block diagram of an electronic still camera.

FIG. 6 is an imaging sequence of an electronic still camera.

FIG. 7 is an explanatory diagram of an interline CCD as an example of a solid-state image sensor often used in an electronic still camera.

FIG. 8 is a diagram showing the read timing of the interline CCD of FIG. 7.

FIG. 9 is a timing chart for reading charges from the horizontal CCD 104.

FIG. 10 is a diagram illustrating a configuration of a CDS circuit that performs CDS.

FIG. 11 is a diagram for explaining the influence of the return of noise to the low frequency band due to CDS when FDA high frequency noise is present.

[Explanation of symbols]

1 Clock generation circuit with a function to slow down the horizontal read clock 2 Low pass filter 3 A / D conversion circuit that converts the output of the CDS circuit into a digital value 4 Frame memory 5 Converts the data in the frame memory into an analog value D
/ A conversion circuit

Claims (2)

[Claims] 1. A solid-state imaging device in which reading of a solid-state imaging device is slower than a television rate, a read signal is band-limited by a low-pass filter, and CDS processing is performed on the band-limited output signal. 2. The solid-state imaging device according to claim 1, wherein
A solid-state imaging device that performs A / D conversion after CDS processing, stores the A / D converted signal in a memory, and converts the signal into a television rate again.