JPH056845A - Thin film transistor forming panel - Google Patents

Abstract

(57) [Summary] [Construction] The blocking layer provided on the channel region of the i-type semiconductor layer 5 is the metal oxide film 8 obtained by anodizing the metal film over its entire thickness. [Effect] Since the metal film and the gate insulating film 4 are completely different in material, the gate insulating film 4 is not etched by the etching solution when the metal film is patterned. The blocking layer can be formed on the channel region of the i-type semiconductor layer without causing the blocking layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor forming panel used for an active matrix liquid crystal display device or the like.

[0002]

2. Description of the Related Art A thin film transistor (TF) is formed on an insulating substrate.
A thin film transistor forming panel (hereinafter referred to as a TFT panel) in which T) and a wiring connected to an electrode of the thin film transistor is formed is used, for example, in an active matrix liquid crystal display element or the like.

FIG. 5 is a plan view of a part of a conventional TFT panel used in an active matrix liquid crystal display device.

In this TFT panel, a large number of pixel electrodes 2, a large number of thin film transistors 3 that are active elements thereof, and a gate line GL connected to the gate electrodes of each thin film transistor 3 are provided on a transparent insulating substrate 1 made of glass. And a data line DL connected to the drain electrode of each thin film transistor 3.

The thin film transistor 3 is generally of an inverted stagger structure. As shown in FIG. 6, the thin film transistor 3 having the inverted stagger structure includes a gate electrode G formed on the substrate 1, a gate electrode insulating film 4 made of Si N (silicon nitride) that covers the gate electrode, and a gate insulating film. A formed on the film 4 so as to face the gate electrode G
I-type semiconductor layer 5 made of -Si (amorphous silicon), and n made of a-Si on the i-type semiconductor layer 5.
The n-type semiconductor layer 6 is composed of a source electrode S and a drain electrode D formed via the type semiconductor layer 6.
Are separated in a portion corresponding to the channel region (region between the source electrode S and the drain electrode D) of the i-type semiconductor layer 5.

The gate electrode G of this thin film transistor 3
Is integrally formed with the gate line GL, the drain electrode D is integrally formed with the data line DL, and the source electrode S is connected to the pixel electrode 2. Further, the gate insulating film 4 is formed on almost the entire surface of the substrate 1 so as to cover the gate wiring 3 as well, and the pixel electrode 2 and the data wiring DL are formed on the gate insulating film 4.

By the way, in manufacturing the TFT panel having the thin film transistor 3 having the above-mentioned inverted stagger structure, the portion corresponding to the channel region of the n-type semiconductor layer 6 formed on the i-type semiconductor layer 5 is etched during the manufacturing thereof. When separated by, the surface of the channel region of the i-type semiconductor layer 5 is also etched, and the i-type semiconductor layer 5 is damaged.

Therefore, in the above TFT, as shown in FIGS. 5 and 6, a blocking layer 7 made of an insulating film is provided on the channel region of the i-type semiconductor layer 5 of the thin film transistor 3, and the n-type semiconductor is provided. By separating the layer 6 on the blocking layer 7, the channel region of the i-type semiconductor layer 5 is prevented from being damaged when the n-type semiconductor layer 6 is separated and etched.

That is, FIG. 7 is a manufacturing process diagram showing the manufacturing method of the TFT panel, and the TFT panel is manufactured by the following processes.

[Step 1] First, as shown in FIG. 7A, a gate electrode G and a gate wiring GL are formed on a substrate 1, and a gate electrode G and a gate wiring GL are formed thereon.
A gate insulating film 4 covering the above, an i-type semiconductor layer 5, and a blocking layer 7 are sequentially formed.

The gate electrode G and the gate line GL are formed by forming a gate metal film on the substrate 1 by a sputtering method and patterning the gate metal film into a predetermined shape by a photolithography method. .

Further, SiN is generally used for the blocking layer 7, and the gate insulating film 4 and i are used.
The type semiconductor layer 5 and the blocking layer 7 are continuously formed by the plasma CVD method.

[Step 2] Next, as shown in FIG. 7B, the blocking layer 7 is formed by photolithography.
Patterning is performed so as to cover the channel region of the type semiconductor layer 5. This blocking layer 7 is patterned by NH
This is performed by wet etching using a mixed solution of 4 and HF as an etching solution.

[Step 3] Next, as shown in FIG. 7C, the i-type semiconductor layer 5 is patterned into a predetermined shape by photolithography. The patterning of the i-type semiconductor layer 5 is performed by dry etching using a mixed gas of carbon tetrachloride and helium as an etching gas.

[Step 4] Next, as shown in FIG. 7D, an n-type semiconductor layer 6 is formed by a plasma CVD method, and a source / drain metal film 10 is formed thereon by a sputtering method. .

[Step 5] Next, as shown in FIG. 7E, the source / drain metal film 10 is patterned by photolithography to form a source electrode S, a drain electrode D and a data line DL. The n-type semiconductor layer 6 is removed by etching except the portions below the source / drain electrodes S and D and the data line DL to complete a thin film transistor.

The patterning of the source / drain metal film 10 is performed by wet etching.

The n-type semiconductor layer 6 is etched by using the etching gas used for etching the i-type semiconductor layer 5. In this case, the channel region of the i-type semiconductor layer 5 has the blocking layer 7 formed therein. Because it is covered with
When the n-type semiconductor layer 6 is etched, the channel region of the i-type semiconductor layer 5 is not etched and damaged.

After that, a transparent conductive film such as ITO is formed on the gate insulating film 4 by the sputtering method, and the transparent conductive film is patterned by the photolithography method to form the pixel electrode 2, and then, as shown in FIG. And the TF shown in FIG.
Complete the T panel.

[0020]

However, in the above-mentioned conventional TFT panel, the locking insulating film 7 provided on the i-type semiconductor layer 5 of the thin film transistor 3 has the same insulating material (SiN) as the gate insulating film 4. Therefore, when patterning the blocking layer 7 formed on the i-type semiconductor layer 5, a pinhole defect may occur in the gate insulating film 4 below the i-type semiconductor layer 5. there were.

This is because the i-type semiconductor layer 5 may have pinholes. If the i-type semiconductor layer 5 has pinholes, the blocking layer 7 shown in FIG. 7B is formed.
At the time of patterning, the etching solution reaches the gate insulating film 4 through the pinhole of the i-type semiconductor layer 4 and causes the pinhole a in the gate insulating film 4.

As described above, the source / drain electrodes S and D of the thin film transistor 3 and the data line DL are formed by patterning the blocking layer 7 and the i-type semiconductor layer 5 and then forming the n-type semiconductor layer 6 and the n-type semiconductor layer 6 thereon. Since the source / drain metal film 10 is formed by patterning these films, if the gate insulating film 3 has the pinhole a as described above, the formed thin film transistor 3 is formed.
A short circuit occurs between the gate electrode G and the source / drain electrodes S and D, and between the gate line GL and the data line DL.

That is, for example, when the pinhole a of the gate insulating film 3 is located at the portion where the gate electrode G and the drain electrode D face each other as shown in FIG. 6, a short circuit occurs between the gate electrode G and the drain electrode D. Occurs, and when the pinhole a is at the portion where the gate electrode G and the source electrode S face each other, a short circuit occurs between the gate electrode G and the source electrode S, and the pinhole a is the gate. Wiring GL and data wiring D
If it is located at the intersection facing L, a short circuit will occur between the gate line GL and the data line DL.

For this reason, the above-mentioned conventional TFT panel has a problem that an interlayer short circuit often occurs in the thin film transistor 3 and the wirings GL and DL, and therefore the manufacturing yield is low.

The inter-layer short circuit in the thin film transistor and the wiring portion is not limited to the above-mentioned TFT panel, but also occurs in various thin film transistor forming panels such as a circuit panel in which an electronic circuit is composed of thin film transistors having an inverted stagger structure. Also in these thin film transistor forming panels, conventionally, since the blocking layer formed on the channel region of the i-type semiconductor layer is formed of an insulating material similar to that of the gate insulating film, the i-type semiconductor layer has a pinhole. , The gate insulating film is etched during the patterning of the blocking layer to generate pinholes,
The above-mentioned interlayer short circuit has occurred.

An object of the present invention is to prevent an interlayer short circuit from occurring in a thin film transistor and a wiring portion, which enables a blocking layer to be formed on a channel region of an i-type semiconductor layer without etching a gate insulating film. It is an object of the present invention to provide a thin film transistor forming panel that can prevent and improve the manufacturing yield.

[0027]

In the thin film transistor forming panel of the present invention, a blocking layer made of a metal oxide film obtained by anodizing a metal film over its entire thickness is provided on the channel region of the i-type semiconductor layer. It is characterized by.

Note that the metal oxide film is provided from above the i-type semiconductor layer to above the gate insulating film, and the metal oxide film above the gate insulating film is provided along the gate wiring in a region above the gate wiring. It is desirable that the gate lines and the data lines be formed linearly along the gate lines and the data lines in the regions above the gate lines and below the data lines.

[0029]

That is, according to the present invention, the blocking layer provided on the i-type semiconductor layer is a metal oxide film obtained by anodizing a metal film. The metal oxide film is formed by forming a metal film. This can be formed by patterning this and then anodizing this metal film over its entire thickness.

The metal film and the gate insulating film are
Since the materials are completely different, the gate insulating film is not etched by the etching solution when patterning the metal film, and therefore, the gate insulating film is not etched on the channel region of the i-type semiconductor layer. A blocking layer can be formed.

Further, in the present invention, the metal oxide film is provided from above the i-type semiconductor layer to above the gate insulating film, and the metal oxide film on the gate insulating film is provided in a region on the gate wiring. If it is formed linearly along
This metal oxide film can be formed by patterning the metal film into the shape described above and applying a voltage to the metal film from the end of the linear portion to anodize the entire metal film. The blocking layer made of the metal oxide film can be simultaneously formed on the i-type semiconductor layer of each thin film transistor arranged along the line.

Further, in the present invention, if the metal oxide film on the gate insulating film is formed in a grid line shape along the gate wiring and the data wiring in the region above the gate wiring and below the data wiring, When the metal film patterned in such a shape is anodized to form the metal oxide film, the end of the linear portion along the gate wiring of the metal film and the end of the linear portion along the data wiring are It is possible to uniformly anodize the entire metal film by applying a voltage from both of them, and thus it is possible to simultaneously form a blocking layer composed of a homogeneous metal oxide film on the i-type semiconductor layers of all thin film transistors. it can.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a thin film transistor forming panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device will be described below with reference to the drawings.

1 to 3 show a first embodiment of the present invention, FIG. 1 is a plan view of a part of a TFT panel, and FIG. 2 is a sectional view of one thin film transistor of the TFT panel. 1 and 2, the same components as those shown in FIGS. 5 and 6 are designated by the same reference numerals and the description thereof will be omitted.

In the TFT panel of this embodiment, a blocking layer composed of a metal oxide film 8 obtained by anodizing a metal film over its entire thickness is provided on the i-type semiconductor layer 5 of the thin film transistor 3. The metal oxide film 8 is formed of, for example, Al (aluminum) anodized Al (A
l ₂ O ₃ ).

The Al oxide film 8 is an insulating film electrically, and therefore the blocking layer is formed by the Al oxide film 8.
Even if it is formed by, the source electrode S and the drain electrode D will not be short-circuited.

The Al oxide film 8 is formed by forming an Al film, patterning the Al film in the shape of a blocking layer, and then anodizing the Al film.
The l film 8 is provided from above the channel region of the i-type semiconductor layer 5 to above the gate insulating film 4.

Further, the oxide Al film 8 on the gate insulating film 4
Is linearly formed in a region on the gate wiring GL along the gate wiring GL, and both ends of the linear portion are
It extends to the outer edge of the gate insulating film 4 formed on the substrate 1 over substantially the entire surface thereof. The linear portion of the Al oxide film 8 is formed to have a width slightly smaller than the width of the gate wiring GL.

FIG. 3 is a manufacturing process diagram showing a manufacturing method of the TFT panel. The TFT panel is manufactured by the following process.

[Step 1] First, as shown in FIG. 3A, the gate electrode G and the gate wiring GL are formed on the substrate 1, and the gate electrode G and the gate wiring GL are formed thereon.
Gate insulating film (SiN film) 4 covering the i-type semiconductor layer 5
And are sequentially formed. The gate electrode G and the gate wiring GL are formed by the same method as the conventional method, and the gate insulating film 4 and the i-type semiconductor layer 4 are continuously formed by the plasma CVD method.

[Step 2] Next, as shown in FIG. 3B, the i-type semiconductor layer 5 is patterned into a predetermined shape by photolithography. The patterning of the i-type semiconductor layer 5 is performed by dry etching using a mixed gas of carbon tetrachloride and helium as an etching gas.

[Step 3] Next, as shown in FIG. 3C, on the i-type semiconductor layer 5 and the gate insulating film 4,
An Al film 8a for forming a blocking layer is formed on almost the entire surface of the gate insulating film 4 by a sputtering method.

[Step 4] Next, as shown in FIG. 3D, the Al film 8a is formed by photolithography.
The blocking layer formed on the channel region of the i-type semiconductor layer 5 and the linear portion along the gate line GL are patterned. The patterning of this Al film is performed by wet etching.

In this case, the surface of the gate insulating film 4 exposed by the patterning of the i-type semiconductor layer 5 and the i-type semiconductor layer 5 are exposed to the etching solution for the Al film 8a, but the Al film 8a and the gate insulating film ( Si N film) 4 and i
Since the material is completely different from the type semiconductor layer 5,
The gate insulating film 4 and the i-type semiconductor layer 5 are not etched by the etching solution when the i film 8a is patterned.

[Step 5] Next, as shown in FIG. 3E, the Al film 8a is anodized over its entire thickness,
This Al film 8a is referred to as an oxidized Al (Al ₂ O ₃ ) film 8.

The anodic oxidation of the Al film 8a is carried out by immersing the substrate 1 in an electrolytic solution so that the Al film 8a faces the counter electrode (platinum electrode) in the electrolytic solution, and the Al film 8a is used as the anode and the counter electrode. Is used as a cathode, and a voltage is applied between the Al film 8a and the counter electrode.

As described above, when a voltage is applied between the Al film 8a and the counter electrode in the electrolytic solution, the Al film 8 serving as the anode is formed.
a undergoes a chemical conversion reaction and is anodized, and this Al film 8a becomes the oxidized Al film 8.

In this case, since the Al film 8a is patterned in the shape of a linear portion along the blocking layer and the gate wiring GL formed on the channel region of the i-type semiconductor layer 5, the Al film 8a is formed. By connecting a clip member or the like to both ends of the linear portion and applying a voltage to both ends of the linear portion, a voltage is applied to the entire Al film 8a.
The l film 8a can be anodized over the entire surface, and therefore, a blocking layer made of the Al oxide film 8 is simultaneously formed on the i-type semiconductor layer 5 of each thin film transistor 3 arranged along the gate line GL. Can be formed.

[Step 6] Next, as shown in FIG. 3F, the n-type semiconductor layer 6 and the source / drain metal film 10 are sequentially formed. The n-type semiconductor layer 6 is a plasma CV.
The film is formed by the D method, and the source / drain metal film 10 is formed by the sputtering method.

[Step 7] Next, as shown in FIG. 3G, the source / drain metal film 10 is patterned by a photolithography method to form a source electrode S, a drain electrode D and a data line DL. The n-type semiconductor layer 6 is removed by etching except the portions below the source / drain electrodes S and D and the data line DL to complete the thin film transistor 3.

The patterning of the source / drain metal film 10 is carried out by wet etching, but the oxide Al film 8 is hardly etched by the etching solution for the source / drain metal film 10, so that the thickness of the oxide Al film 8 is reduced. Even if the thickness is thin, the oxidized Al film 8 does not disappear.

The n-type semiconductor layer 6 is the i-type semiconductor layer 5
Etching is performed using the etching gas used for the etching, but the channel region of the i-type semiconductor layer 5 is oxidized by A
l Since it is covered with a blocking layer consisting of the film 8,
When the type semiconductor layer 6 is etched, the channel region of the i-type semiconductor layer 5 is not etched and damaged.

After that, a transparent conductive film such as ITO is formed on the gate insulating film 4 by the sputtering method, and the transparent conductive film is patterned by the photolithography method to form the pixel electrode 2. And the TF shown in FIG.
Complete the T panel.

Although the Al film 8a for forming the blocking layer is formed after the i-type semiconductor layer 5 is patterned in this embodiment, the i-type semiconductor layer 5 in each thin film transistor 3 portion is continuous. However, if the characteristics of each thin film transistor 3 are not affected, the patterning of the i-type semiconductor layer 5 is performed to form an Al film 8a and then the Al film 8a is formed.
It may be performed after patterning. In this case, A
The i-type semiconductor layer 5 remains under the linear portion of the oxidized Al film 8 obtained by anodizing the l-film 8a so as to be continuous with the i-type semiconductor layer 5 in the thin film transistor 3 portion.

That is, the TFT panel of this embodiment is
The blocking layer provided on the i-type semiconductor layer 5 is an Al oxide film 8 obtained by anodizing the Al film. The Al oxide film 8 is formed by forming the Al film 8a as described above. After patterning this, the Al film 8a can be formed by anodizing the entire thickness thereof.

Since the Al film 8a and the gate insulating film (SiN film) 4 are made of completely different materials, the gate insulating film 4 may not be etched by the etching solution when the Al film 8a is patterned. Therefore, since the blocking layer can be formed on the channel region of the i-type semiconductor layer 5 without etching the gate insulating film 4, the thin film transistor 3 and the wiring G
It is possible to prevent the interlayer short circuit from occurring in the L and DL portions, and improve the manufacturing yield of the TFT panel.

In the above embodiment, the oxidized Al film 8 is used.
Is provided from above the channel region of the i-type semiconductor layer 5 to above the gate insulating film 4, and the Al oxide film 8 on the gate insulating film 4 is formed linearly along the gate wiring GL. The Al film 8a is formed by patterning the Al film 8a in the above-described shape, and applying a voltage to the Al film 8a from the end of the linear portion to anodize the entire Al film 8a. Because it can be done, the gate wiring GL
A blocking layer made of the Al oxide film 8 can be simultaneously formed on the i-type semiconductor layer 5 of each thin film transistor 3 arranged along the line.

Moreover, in the above-described embodiment, the linear portion of the Al oxide film 8 formed on the gate insulating film 4 is formed by the gate wiring GL.
Since the line portion is formed along the gate line GL in the upper region and the width of the linear portion is smaller than the width of the gate line GL, the oxide Al film 8 is formed on the gate insulating film 4.
Even if the linear portions are formed, the formation area of the pixel electrode 2 is not restricted.

FIG. 4 is a TFT showing a second embodiment of the present invention.
It is a top view of a part of panel.

In the TFT panel of this embodiment, the Al oxide film 8 on the gate insulating film 4 is provided in the region above the gate line GL and the region below the data line DL along the gate line GL and the data line DL. It is formed in a grid line shape.

In the TFT panel of the second embodiment, the Al oxide film 8 on the gate insulating film 4 is connected to the data wiring D.
The other structure is the same as that of the above-described first embodiment except that it is formed in the region below L as well, and the description thereof will be omitted by giving the reference numerals to the drawings.

The TFT panel of this embodiment is shown in FIG.
In the patterning process of the Al film 8a shown in FIG. 3, the Al film 8a is left linearly in the formation region of the data wiring DL.
In the anodizing step shown in (e), the Al film 8a in the data wiring forming region is also anodized at the same time, so that the first
It can be manufactured in the same manner as the manufacturing of the TFT panel of the embodiment.

In the TFT panel of the second embodiment, the Al oxide film 8 to be the blocking layer is
Of the gate insulating film 4 from above the channel region of the type semiconductor layer 5
Over the gate insulating film 4 and the metal oxide film on the gate insulating film 4 is formed on the gate wiring GL and the data wiring D.
In the region under L, the Al film 8a patterned in such a shape is anodized by oxidation because the lattice film is formed along the gate wiring GL and the data wiring DL.
When forming the Al film 8, the gate wiring G of the Al film 8a is formed.
A voltage can be applied from both ends of the linear portion along L and both ends of the linear portion along data line DL to uniformly anodize the entire Al film 8a.

Therefore, according to the second embodiment, it is possible to simultaneously form the homogeneous blocking layer of the oxidized Al film 8 on the i-type semiconductor layers 3 of all the thin film transistors 3.

In the first and second embodiments described above,
Although the metal oxide film 8 serving as the blocking layer is the oxide film of the Al film 8a, the metal oxide film 8 is not limited to Al and may be anodized of another metal film.

Further, the present invention is not limited to the TFT panels of the first and second embodiments, but may be, for example, a circuit panel having an electronic circuit composed of thin film transistors having an inverted stagger structure.
It can be applied to various thin film transistor forming panels.

[0067]

According to the thin film transistor forming panel of the present invention, the blocking layer provided on the i-type semiconductor layer is a metal oxide film obtained by anodizing a metal film. After forming the film and patterning it, the metal film can be formed by anodizing over its entire thickness. Further, since the metal film and the gate insulating film are completely different in material, The gate insulating film is not etched by the etching solution when the metal film is patterned.

Therefore, according to the present invention, since the blocking layer can be formed on the channel region of the i-type semiconductor layer without etching the gate insulating film, an interlayer short circuit occurs in the thin film transistor and the wiring portion. This can be prevented and the production yield can be improved.

Further, in the present invention, the metal oxide film is provided from above the i-type semiconductor layer to above the gate insulating film, and the metal oxide film on the gate insulating film is provided in a region above the gate wiring. If it is formed linearly along
This metal oxide film can be formed by patterning the metal film into the shape described above and applying a voltage to the metal film from the end of the linear portion to anodize the entire metal film. The blocking layer made of the metal oxide film can be simultaneously formed on the i-type semiconductor layer of each thin film transistor arranged along the line.

Further, in the present invention, if the metal oxide film on the gate insulating film is formed in a grid line shape along the gate wiring and the data wiring in a region above the gate wiring and below the data wiring, When the metal film patterned in such a shape is anodized to form the metal oxide film, the end of the linear portion along the gate wiring of the metal film and the end of the linear portion along the data wiring are It is possible to uniformly anodize the entire metal film by applying a voltage from both of them, and thus it is possible to simultaneously form a blocking layer composed of a homogeneous metal oxide film on the i-type semiconductor layers of all thin film transistors. it can.

[Brief description of drawings]

FIG. 1 is a plan view of a thin film transistor forming panel showing a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view taken along line II-II of FIG.

FIG. 3 is a manufacturing process diagram of a thin film transistor forming panel.

FIG. 4 is a plan view of a thin film transistor forming panel showing a second embodiment of the present invention.

FIG. 5 is a plan view of a conventional thin film transistor forming panel.

6 is an enlarged sectional view taken along the line VI-VI of FIG.

FIG. 7 is a manufacturing process diagram of a conventional thin film transistor forming panel.

[Explanation of symbols]

1 ... Substrate, 2 ... Pixel electrode, 3 ... Thin film transistor, G ...
Gate electrode, GL ... Gate wiring, 4 ... Gate insulating film, 5
... i-type semiconductor layer, 6 ... n-type semiconductor layer, S ... source electrode,
D ... Drain electrode, 8 ... Metal oxide film.

Claims (3)

[Claims] 1. A gate electrode, a gate wiring connected to the gate electrode, and a gate insulating film covering the gate electrode and the gate wiring are formed on an insulating substrate, and the gate electrode and the gate insulating film thereon are formed. An i-type semiconductor layer formed on the gate insulating film so as to face the gate electrode, and a source formed via an n-type semiconductor layer formed on the i-type semiconductor layer and separated in a channel region. In the thin film transistor forming panel, a thin film transistor is formed of an electrode and a drain electrode, and a data wiring connected to at least one of the source electrode and the drain electrode is formed on the gate insulating film. A metal oxide film, which is anodized over its entire thickness, is formed on the channel region of the metal oxide film. A thin film transistor-formed panel comprising a locking layer. 2. The metal oxide film is provided from above the i-type semiconductor layer to above the gate insulating film, and the metal oxide film on the gate insulating film is formed on the gate wiring in a region above the gate wiring. The thin film transistor formation panel according to claim 1, wherein the thin film transistor formation panel is formed along a line. 3. The metal oxide film is provided from above the i-type semiconductor layer to above the gate insulating film, and the metal oxide film on the gate insulating film is provided on the region above the gate wiring and below the data wiring. The thin film transistor formation panel according to claim 1, wherein the thin film transistor formation panel is formed in a region along the gate line and the data line in a grid line shape.