JPH0568732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA transfer control method, and more particularly to a DMA transfer control method capable of high-speed processing.

[Conventional technology]

Conventionally, when using a DMA controller to transfer data from FIFO (first-in-first-out memory) to memory such as RAM, the main control unit first writes all the transfer data to the FIFO, and then transfers the data to the DMA controller. A startup instruction including the memory address of the transfer destination and the number of bytes of transfer data (transfer byte number) is added to start the DMA controller. Also, if you want to transfer more data to memory than the number of bytes that the FIFO can store (number of bytes that can be stored),
After writing data equal to or less than the number of bytes that can be stored in the FIFO, the process of adding a startup instruction including the transfer destination memory address and the number of transfer bytes to the DMA controller is repeated until the data transfer is completed.

[Problem that the invention seeks to solve]

In the conventional method described above, the main control unit writes the transfer data to the FIFO and then issues a startup instruction to the DMA controller.
Since the DMA controller has a hardware waiting time (waiting time caused by setting the number of transfer bytes, setting the transfer destination address, etc.) from when a startup instruction is applied until it starts transferring data, There is a problem in that no processing is performed at all after the activation instruction is given until the data transfer starts, resulting in a large amount of wasted time. Also, when transferring data that exceeds the number of bytes that can be stored,
After writing data equal to or less than the number of bytes that can be stored in the FIFO, the process of adding a startup instruction including the transfer destination memory address and the number of transfer bytes to the DMA controller is repeated until the data transfer is completed. There are also problems with inefficiency.

The present invention solves the above-mentioned problems, and its purpose is to enable efficient DMA transfer.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a DMA transfer control method in which data written by a main control unit to a FIFO is transferred to a memory using a DMA controller. A byte counter indicating the number of bytes is provided, and the DMA controller compares the number of block transfer bytes preset by the main control unit with the number of bytes indicated in the byte counter, and a first comparator that applies a read signal of the same number as the number of block transfer bytes to the FIFO when the number of bytes indicated by is greater than or equal to the number of block transfer bytes; a transfer completion search circuit that sets the number of transfer bytes output by the main control unit and calculates the remaining number of transfer bytes based on the set number of transfer bytes and a read signal for the FIFO; The number of transferred bytes is compared with the number of block transferred bytes, and the number of remaining transferred bytes obtained by the transfer completion search circuit is compared with the number of bytes indicated by the byte counter, and the remaining transfer bytes obtained by the transfer completion search circuit are compared. The number of remaining transfer bytes determined by the transfer completion search circuit matches the number of bytes indicated by the byte counter, and the remaining transfer byte count obtained by the transfer completion search circuit is less than the block transfer byte number. a second comparator that applies the same number of read signals to the FIFO as writing means for sequentially writing read data into the memory starting from the set memory address, and the main control unit, when transferring data to the memory, tells the DMA controller the number of transfer bytes of transfer data. and a memory address to which the data is to be transferred, as well as issuing a startup instruction. Thereafter, writing of transfer data to the FIFO is started, and all transfer data is sequentially written to the FIFO.

[Effect]

When the main control unit transfers data to memory,
It outputs the number of bytes of transfer data and the memory address of the transfer destination to the DMA controller, as well as instructs it to start, and then starts writing data to the FIFO, which was not done at all in the past. During the hardware waiting time from when a startup instruction is given to the DMA controller until data transfer actually starts.
Since transfer data can be written to the FIFO, data transfer time can be shortened.

After giving a startup instruction to the DMA controller, the main control unit starts writing transfer data to the FIFO, and sequentially writes all transfer data to the FIFO.
The first comparator outputs the same number of read signals as the number of block transfer bytes each time the number of transfer data bytes accumulated in the FIFO exceeds the number of block transfer bytes.
Add to FIFO. As a result, data corresponding to the number of block transfer bytes is transferred in blocks. The second comparator applies the same number of read signals as the remaining number of transfer bytes to the FIFO when the number of remaining transfer bytes of the transfer data becomes less than the number of block transfer bytes and all the remaining transfer bytes are stored in the FIFO.
As a result, the remaining transfer data is transferred. Here, the first comparator creates a read signal based on the number of block transfer bytes preset by the main controller and the number of bytes indicated by the byte counter,
The second comparator creates a read signal based on the number of block transfer bytes preset by the main controller, the number of bytes indicated by the byte counter, and the number of remaining transfer bytes. Since it is determined by the number of transfer bytes set by the control unit and the read signal,
Even when transferring data that exceeds the number of bytes that can be stored in the FIFO, it is possible to perform startup processing only once.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
It is composed of a main control section 1, a DMA controller 2, a FIFO 3 having a byte counter 4, and a memory 5.

The FIFO 3 having a byte counter 4 activates the addition signal line 12 every time one byte of data 11 is added from the main control unit 1 to cause the byte counter 4 to count up, and activates the subtraction signal every time one byte of data 16 is read out. Line 13 is activated to cause byte counter 4 to count down. That is, the count value 14 of the byte counter 4 indicates the number of bytes of data stored in the FIFO 3. Also,
The FIFO 3 deactivates the write permission signal line 28 when the number of bytes of data stored therein becomes equal to the number of storable bytes.

The DMA controller 2 includes first and second comparators 6 and 7, a transfer completion search circuit 8, a buffer 9,
10 and an or gate 29.
The comparator 6 compares the number of block transfer bytes 17 (the number of bytes of data transferred in one block transfer) set by the main control unit 1 at the time of initial setting with the count value 14 of the byte counter 4, and the comparison result is Count value 14 ≧ Number of block transfer bytes 17
When this happens, the same number of read signals 22 as the number of block transfer bytes (17) are output. Transfer completion search circuit 8
has a counter (not shown) that counts the number of bytes of data actually transferred using the read signal 15 as an input clock. The value obtained by subtracting the count value of is added to the comparator 7 as the number of remaining transfer bytes 23, and when the number of remaining transfer bytes 23 becomes "0", a DMA completion signal 19 is applied to the main control unit 1. Note that the above counter is reset when the number of transferred bytes is set to 18. The comparator 7 compares the count value 14 and the number of remaining transfer bytes 23, and also compares the number of block transfer bytes 17 and the number of remaining transfer bytes 23, and the comparison result is that the count value 14 = the number of remaining transfer bytes 23, and the remaining When the number of transferred bytes is 23<the number of block transferred bytes is 17, the remaining number of transferred bytes is 23.
The same number of read signals 24 are output.

Next, the operation shown in FIG. 1 will be explained.

The main controller 1 sets the number of block transfer bytes, 17, in the comparator 6 in the DMA controller 2 at the time of initializing the entire device. After this, when data is transferred from the FIFO 3 to the memory 5 using the DMA controller 2, the main control unit 1 first performs the following steps.
The number of transfer bytes 18 and the memory address 21 of the data transfer destination are added to the DMA controller 2, the activation instruction line 20 is activated, and then the transfer data 11 is written into the FIFO 3. At this time, if the number of transfer bytes 18 added to the DMA controller 2 is larger than the number of bytes that can be stored in the FIFO 3, the main control unit 1 confirms that the write permission line 28 from the FIFO 3 is activated and then transfers the data. 11 is written. Further, when the DMA controller 2 confirms that the activation instruction line 20 has been activated, it stores the memory address 21 from the main control unit 1 in the buffer 10 and sets the number of transfer bytes 18 in the transfer completion search circuit 8.

When writing of the transfer data 11 to the FIFO 3 is started, the count value 14 of the byte counter 4 gradually increases. Then, when the count value 14 reaches the number of block transfer bytes 17, that is, when the relationship of count value 14≧number of block transfer bytes 17 is satisfied, the comparator 6 outputs the same number of read signals 22 as the number of block transfer bytes 17, as described above. Output.
This read signal 22 is passed through an OR gate 29.
The FIFO 3 outputs one block worth of transfer data 16 in accordance with the read signal 15 output from the OR gate 29. The DMA controller 2 sequentially stores the data 16 output from the FIFO 3 in the buffer 9, and sends the data 27 stored in the buffer 9 to the write signal 26 as in the past.
The data is sequentially written into the memory 5 starting from the address 25 stored in the buffer 10 according to the timing.
At this time, the memory address stored in the buffer 10 is set to the write signal 26 in the same way as before.
It will be changed sequentially according to the following.

Even while data is being written to memory 5, transfer data is being written to FIFO 3, and when the count value 14≧block transfer byte number 17, the same operation as described above is performed. When the count value 14=the number of remaining transfer bytes is 23, and the number of remaining transfer bytes 23<the number of block transfer bytes 17, the following operation is performed.

When the above conditions are satisfied, that is, when the number of remaining transfer bytes 23 of the transfer data becomes less than or equal to the number of block transfer bytes 17, and when all the remaining data is written to FIFO 3, the comparator 7 detects the number of remaining transfer bytes as described above. 23 and the same number of read signals 24 are output. This read signal 24 is applied to FIFO 3 via OR gate 29, and FIFO 3 is applied to OR gate 2.
Transfer data is sequentially output one byte at a time in accordance with a read signal 15 output from 9. The data output from FIFO 3 is temporarily stored in buffer 9,
The data 27 stored in the buffer 9 is transferred to the buffer 1 of the memory 5 according to the timing of the write signal 26.
They are written in order starting from address 25, which is stored in address 0. In other words, if the number of bytes of residual data is 17 or more block bytes, data is transferred in units of block transfer bytes, and if the number of block transfer bytes is 17 or less, data is transferred in units of that number of bytes. It is done. Then, the data transfer is completed and the remaining transfer data count 23 becomes “0”.
Then, the DMA controller 2 notifies the main control unit 1 of the end of the DMA transfer using the DMA completion signal 19.

Note that it is also possible to integrate the portion surrounded by the dashed line in FIG.

〔Effect of the invention〕

As explained above, the present invention first provides DMA
It outputs the number of bytes to be transferred and the memory address of the transfer destination to the controller, as well as instructing the controller to start, and then starts writing the transfer data to the FIFO, which is an improvement to the DMA controller, which previously did not perform any processing at all. Transfer data can be written to the FIFO during the hardware waiting time from when a startup instruction is given until data transfer actually starts, which has the effect of shortening data transfer time. be.

Also, one data transfer to memory is performed every predetermined number of block transfer bytes;
Since the second comparator automatically detects and transfers the remaining data less than the number of block transfer bytes, the amount of data that can be transferred can be set to any length.

Furthermore, the present invention provides the same number of read signals as the number of block transfer bytes each time the number of transfer data bytes accumulated in the FIFO exceeds the number of block transfer bytes.
The first comparator circuit added to the FIFO, the number of remaining transfer bytes of the transfer data is less than the number of block transfer bytes, and all remaining transfer bytes are stored in the FIFO, so that read signals equal to the number of remaining transfer bytes are generated. After outputting a start instruction to the DMA controller, the main control unit starts writing the transfer data to the FIFO, and writes all the transfer data sequentially.
Since it is written to the FIFO, even when transferring data that exceeds the number of bytes that can be stored in the FIFO,
The processing required to start up the DMA controller can be reduced to one time, which has the effect of improving data transfer efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. In the figure, 1... Main control unit, 2... DMA controller, 3... FIFO, 4... Byte counter, 5... Memory, 6, 7... Comparator, 8... Transfer completion search circuit, 9,10...Batsuhua.

Claims (1)

[Claims] 1. The data written by the main control unit to the FIFO is
In a DMA transfer control method in which a controller is used to transfer data to memory, a byte counter is provided that indicates the number of bytes of data stored in the FIFO, and the DMA controller is provided with a byte counter that indicates the number of bytes of data stored in the FIFO. The number of block transfer bytes currently being transferred is compared with the number of bytes indicated by the byte counter, and if the number of bytes indicated by the byte counter is greater than or equal to the number of block transfer bytes, a read signal equal to the number of block transfer bytes is generated. a first comparator that adds the number of transferred bytes to the FIFO; a transfer completion search circuit that calculates the number of remaining transfer bytes based on the transfer completion search circuit; and a transfer completion search circuit that compares the remaining transfer byte number obtained by the transfer completion search circuit with the block transfer byte count, and also compares the remaining transfer byte count obtained by the transfer completion search circuit. The number of bytes is compared with the number of bytes indicated by the byte counter, and if the number of remaining transferred bytes determined by the transfer completion search circuit matches the number of bytes indicated by the byte counter, and the number of remaining transfer bytes determined by the transfer completion search circuit is a second comparator that applies read signals to the FIFO equal to the number of remaining transfer bytes determined by the transfer completion search circuit when the number of transfer bytes becomes less than the number of block transfer bytes; writing means for setting a memory address to which data outputted by the main control unit is to be transferred in response to an instruction, and sequentially writing data read from the FIFO to the memory from the set memory address; When transferring data to the memory, the main control unit outputs the number of transfer bytes of transfer data and the memory address of the data transfer destination to the DMA controller, and also issues a start instruction, and then transfers the transfer data to the FIFO. A DMA transfer control method characterized by starting writing of the FIFO and sequentially writing all transfer data to the FIFO.