JPH056896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a failure detection system, and more specifically, to a failure detection system for a store check mechanism attached to a store buffer of an information processing apparatus having a cache memory.

(Prior Art) In large-scale computers, in order to speed up processing, a store buffer is essential for a store path from an arithmetic processing unit to a cache memory, or from a cache memory to a main storage unit. In such a configuration, read commands to the memory are usually processed with priority over store commands. However, if there is a store to the same address as the read address in the store buffer, the data in this store buffer must be read. Therefore, the store buffer is provided with a comparator for each entry to compare the store address of each entry with the subsequent read address. If this comparator detects a match between the store address and read address of each entry at the memory read timing, the store command in the store buffer is processed first, followed by the read command. This structure maintains the order of command execution and guarantees reading of correct data (in this case, data rewritten in the previous store). Therefore, if the comparator fails, it becomes impossible to maintain the order of command execution, leading to serious failures such as garbled data.

(Problems to be Solved by the Invention) Conventionally, a method of comparing data with parity and parity checking the output has been used to detect a failure in this comparator. However, with this method, the only circuit that can detect a failure among the circuits that make up the comparator is exclusive OR, and the subsequent AND
It was not possible to detect circuit failures, etc.

The purpose of the present invention is to avoid serious failures such as data corruption by inputting the same address to two inputs of a comparator and detecting comparator failures in advance when the store buffer flushing operation takes priority. The purpose of this invention is to provide a fault detection method that can perform the following tasks.

(Means for Solving the Problems) In order to achieve the above object, a failure detection method for a store check mechanism according to the present invention is provided between a cache memory and a main memory in an information processing device, and is configured to detect data stored in the main memory. It consists of a memory store buffer with multiple entries that holds addresses corresponding to the memory store buffer, and a mechanism that issues a memory read request to the main memory. In a fault detection method for a store check mechanism that compares addresses and outputs a match signal if they are the same, a selector is provided at one input of a comparator corresponding to each entry of the store address, and at the timing of the read address, As a result of selecting each read address and comparing it with the corresponding store address, when a match is detected, a timing is generated to give priority to the store buffer cleaning operation, and when the store buffer cleaning operation is given priority, each selector selects each store address. The selected comparators are configured to compare the same store address, and output a signal indicating a failure when a comparator does not output a matching signal.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention.

Store buffer 1 is, for example, an address store buffer extracted from a cache store buffer of four entries.

The structure of the store buffer shown in the figure and the part not shown is a FIFO structure, and is composed of, for example, a register or a register file, a pointer indicating input and output entries, and a control circuit that controls the pointer.

The contents of the store buffer can be referenced in addition to being read, and a comparator, which will be described later, compares the store buffer address with the read address.

A register 20 with a selector 20a switches between accepting a read request and a store request, and sends the request to the main memory.

Normally, lead requests are processed with priority. However, when the line 15 becomes "0" at the timing generated by the store priority processing timing generation circuit 21, the inverted output of the AND gate 17 becomes "1", so the selector 20a selects the output of the store buffer 1, and the store has priority. be processed.

Comparators 2 to 5 are for comparing the store address held in the store buffer 1 with the read address. One input of the comparators 2 to 5 is the selector 2a to 5a, and this selector 2a
5a is the output of the selector 18 since the inverted output of the AND gate 6 becomes "1" when the line 14 is "0", and the output of the AND gate 6 when the line 14 is "1".
Since the positive output of is "1", the store address held in store buffer 1 is selected. Therefore, comparators 2 to 5 compare the output (read address) of selector 18 with the store address held in store buffer 1 when line 14 is "0", and compare the output (read address) of selector 18 with the store address held in store buffer 1 when line 14 is "1". receives the addresses held in store buffer 1 at two inputs, and compares the same addresses.

The selector 18 and the register 19 are circuit units forming a loop for holding a read address when a read request is suspended due to store priority processing. When line 13 is “0”,
Since the inverted output of the AND gate 16 becomes "1", the selector 18 accepts a read address from the outside. Also, when the line 13 is "1", the positive output of the AND gate 16 is "1", so the selector 18
selects the output of register 19 and holds the read address.

Now, the operation when the line 14 is in the "0" state will be explained.

The line 14 is "0", and each selector 2a to 5a
selects the read address, so comparators 2 to 5
compares the read address and the store address held in store buffer 1. Comparator 2~
Since the output of 5 is ORed by the OR gate 7, if even one of the addresses held in the store buffer 1 matches the read address, the output of the OR gate 7 becomes "1". AND gate 6
Since the inverted output of is "1", the output of the OR gate 7 is inverted and output from the NAND gate 9. When the output of this NAND gate 9 is "0", it indicates that read overtaking has occurred, and when the line 12 becomes "0", the store priority processing timing generation circuit 21 is instructed to hold the read and give priority to the store. Request processing. If there is no address that matches the output (read address) of the selector 18 among the addresses held in the store buffer 1, the output of the OR gate 7 will be "0", so the NAND
The output of gate 9 becomes “1” and line 12 becomes “1”
status is maintained, and reads are processed with priority as usual.

Next, the operation when the line 14 is in the "1" state will be explained.

When line 14 is “1”, selectors 2a to 5a
Since selects the store address, the same address is input to two inputs of comparators 2 to 5. If the comparators function normally, the outputs of comparators 2 to 5 will all be "1". To confirm this,
If there is a comparator that inputs the outputs of comparators 2 to 5 to NAND gate 8, the output does not become "1".
Since the output of the NAND gate 8 becomes "1", the output of the AND circuit 10, which has a timing other than the read timing, becomes "1", thereby detecting that at least one of the comparators is malfunctioning.

FIG. 2 is a diagram showing in detail the store priority processing timing generation circuit 21 of FIG. 1.

Registers 40 to 42 are flip-flops (hereinafter abbreviated as FF) that are at "0" in a steady state.

Now, line 11 is “1” due to the read request.
When this happens, "1" is set in the FF 40 through the AND gate 30 and the OR gate 35. As a result, the line 13 also becomes "1", and the read address is held in the loop composed of the selector 18 and register 19, as described above. AND gate 3
As the output of 0 becomes "1", the output of the OR gate 37 also becomes "1". At this time, if the line 12 that instructs read suspension is inactive and is at "1", the AND gate 34 becomes "1" and the FF
42 is set to "1". Also, the output of the AND gate 34 is passed through the line 15 to the selector 20a.
When the register 20 is set to "1", a read request is accepted. FF40 and 4
After “1” is set in 2, FF42
FF40 is reset, and FF40 is reset by FF40.
2 is also reset, but while FF 42 is "1", "1" is output through line 14. This period is the store priority processing timing, in which read requests are not accepted and stores are processed preferentially.
Also, as described above, the store buffer comparator is tested during this period.

Next, a case will be described in which the line 12 instructing read suspension becomes active state "0" at the request timing. In this case, since the output of the AND gate 34 is "0", the FF 42 is in the "0" state, and "0" is output to the line 15. Therefore, a read request is not accepted, and a store request is accepted by the register 20 with selector 20a. Instead of "1" being set in FF42, "1" is output to FF41 through AND gate 32 and OR gate 36. After this,
After a while, when the store to the same address as the read is flushed from the store buffer 1 to the memory through the register with selector 20, the signal 12 indicating suspension of the read becomes inactive state "1", and the output of the AND gate 34 becomes “1”. From then on, as described above, reads are processed with priority, FF42 is set, FF41 is reset, and so on.
Enter store priority processing.

(Effects of the Invention) As described above, the present invention inputs the same data to two inputs of a comparator for detecting read overtaking of a store buffer so that a match signal is output when priority is given to the store buffer sweep operation. and is configured to detect failures.
Since a comparator failure can be discovered in advance and it can be seen that the order of command execution cannot be maintained, it is possible to prevent serious failures such as data garbled due to read overtaking.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the failure detection method according to the present invention. FIG. 2 is a block diagram showing details of the store priority processing timing generation circuit shown in FIG. 1. 1... Part of the memory store buffer, 2 to 5...
...Address comparator, 6, 16... Buffer with positive and negative outputs, 8, 9... NAND gate, 10...
...AND gate, 7...OR gate, 18...Selector, 19...Register, 20...Register with selector, 30, 31, 32, 33, 34...
AND gate, 35, 36, 37...OR gate,
38, 39... Buffer with positive and negative outputs, 4
0, 41, 42...Flip-flop for individual control.

Claims (1)

[Claims] 1. A memory store buffer with multiple entries that is provided between the cache memory and main memory in an information processing device and holds addresses corresponding to data stored in the main memory, and a mechanism that issues memory read requests to the main memory. In the failure detection method of the store check mechanism, the store address held in the memory store buffer of the plurality of entries is compared with the address of the memory read, and if they are the same, a match signal is output. A selector is provided at one input of the comparator corresponding to each address entry, and at the timing of the read address, each read address is selected and compared with the corresponding store address. When a match is detected, priority is given to the store buffer flushing operation. When the timing is generated and priority is given to the store buffer cleaning operation, each selector selects each store address, each comparator compares the same store address, and when a comparator does not output a match signal, a failure occurs. 1. A failure detection method for a store check mechanism, characterized in that the system is configured to output a signal indicating a signal.