JPH056898A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a leakage current of a transistor by forming a polycrystalline silicon film to become source.drain regions through an insulating film, and then ion implanting fluorine in the silicon film. CONSTITUTION:After an insulating film 11 of a silicon oxide, etc., is formed on a silicon substrate 10, a polycrystalline silicon film which is doped with impurities (P, B) in high concentration, is deposited thereon, and patterned to form a lower gate electrode 12. Then, a silicon dioxide film to become a gate oxide film 13 is deposited on the entire surface, and a thin polycrystalline silicon film 14 is formed thereon. Thereafter, with a photoresist film 16 as a mask BF2 ions 15 are partly implanted in the film 14 to form a source region 17 and a drain region 18. Then, the film 16 is removed, fluorine ions 19 are implanted in the entire surface, and heat-treated to activate the impurity. Thus, since grain boundaries, unbonded hand of a defect in the silicon thin film can be inactivated, a leakage current can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device on an insulating film.

[0002]

2. Description of the Related Art A conventional method for manufacturing a lower gate type thin film transistor will be described with reference to FIG.

First, as shown in FIG. 3A, an insulating film 31 such as a silicon oxide film is formed on a silicon substrate 30. Then, a conductive film (for example, polycrystalline silicon doped with impurities at a high concentration) is deposited on the insulating film 31,
Patterning is performed to form the lower gate electrode 32, and then a silicon dioxide film to be the gate oxide film 33 is deposited thereon. Then, a thin polycrystalline silicon film 34 is deposited thereon to form an active region. This polycrystalline silicon film 34
Since the larger the grain size is, the smaller the leak current and the higher the mobility, amorphous silicon is first deposited and the temperature is set to 600 ° C.
A method of slowly polycrystallizing at temperatures around is often used.

Next, as shown in FIG. 3B, impurities 35 such as BF ₂ ⁺ ions are partially ion-implanted into the polycrystalline silicon film 34 at a high concentration with a resist film as a mask. A source region 37 and a drain region 38 are formed and impurities are activated by heat treatment to form a basic structure of a lower gate type thin film transistor. This structure is called a lower gate type because the gate electrode is located under the active region. However, if the order of forming the polycrystalline silicon film 34 to be the active region and the gate electrode is exchanged, a normal upper gate type thin film transistor can be formed. You can

[0005]

Since the active region of the thin film transistor thus formed is a polycrystalline silicon film, the characteristics of the thin film transistor are formed in single crystal silicon due to the grain boundaries or defects contained therein. It is much worse than a transistor. Usually, by performing heat treatment (around 400 ° C.) in a hydrogen atmosphere after forming a transistor or depositing a silicon nitride film containing a large amount of hydrogen and then performing a heat treatment (around 400 to 500 ° C.), internal defects are not damaged. It is being activated. As a result, for a typical polycrystalline silicon film thickness of 50 nm, the channel width W = 1 μm and the drain voltage Vd =
The leakage current value is about 1 pA at 5 V (P-type transistor). The leak current value is SRAM (Static).
Random Access Memory) cells, liquid crystal display pixels, and other devices that require low leakage current are large, and it is necessary to reduce the leakage current.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, fluorine ions are ion-implanted into a polycrystalline silicon film for forming source / drain regions.

[0007]

FUNCTION Fluorine has a function of inactivating dangling bonds of silicon at grain boundaries and defect portions which cause deterioration of transistor characteristics. However, it is easily removed from the film by exposing it to a high temperature, and therefore it is desirable to introduce it into the polycrystalline silicon film in a step as late as possible in the transistor manufacturing process. A significant portion of the fluorine remaining in the active region when the transistor is completed is believed to help deactivate the dangling bonds in the silicon.

[0008]

EXAMPLES Next, the present invention will be described with reference to examples. Figure 1
(A)-(c) is a longitudinal sectional view of a semiconductor chip for explaining the manufacturing process of the first embodiment of the present invention.
As shown in FIG. 1A, an insulating film 11 such as a silicon oxide film is formed on a silicon substrate 10, and a polycrystalline silicon film doped with impurities (P, B) at a high concentration is deposited on the insulating film 11. The lower gate electrode 12 is formed by patterning. Next, a silicon dioxide film to be the gate oxide film 13 is deposited on the entire surface, and a thin polycrystalline silicon film 14 is formed on the silicon dioxide film. The polycrystalline silicon film 14 is formed by first depositing amorphous silicon, heat-treating it at a temperature of 600 ° C. for 10 hours to polycrystallize it, and then performing element isolation by anisotropic etching using a patterned photoresist film as a mask. It was

Next, as shown in FIG. 1B, BF ₂ ions 15 are partially ion-implanted into the polycrystalline silicon film 14 with the photoresist film 16 as a mask at a concentration of 1 × 10 ¹⁵ cm ^-2. Then, the source region 17 and the drain region 18 are formed.

Next, as shown in FIG. 1C, the photoresist film 16 is removed, and fluorine ions 16 are applied to the entire surface by 1 × 1.
Ions are implanted by 0 ¹⁵ cm ^-2 and the impurities are activated by heat treatment. After that, a cover film and a wiring are formed in the same manner as in a normal manufacturing process, and a silicon nitride film is further deposited and heat treatment is performed at 450 ° C. to complete a transistor.

In the P-type thin film transistor in which the fluorine ion implantation is performed as described above, a leakage current of 0.3 pA is obtained with respect to the gate width W = 1 μm and the drain voltage Vd = −5 V, and the fluorine ion implantation simultaneously produced. The leak current could be reduced to 1/3 or less as compared with the leak current of 1 pA of the P-type thin film transistor which was not performed. Also, the mobility is improved by about 10%,
The swing could be improved to about 70%.

2A and 2B are sectional views of a semiconductor chip for explaining the manufacturing process of the second embodiment of the present invention. In this example, the present invention is applied to an upper gate N-type transistor.

First, as shown in FIG. 2A, after an insulating film 21 such as a silicon film is formed on a silicon substrate 20, a thin polycrystalline silicon film 22 is formed thereon (amorphous silicon). Was first deposited and polycrystallized by heat treatment at a temperature of 600 ° C. for 10 hours), element isolation was performed by anisotropic etching using the patterned resist as a mask, and then a silicon dioxide film to be the gate oxide film 23 on the entire surface. Deposit. Then, a polycrystalline silicon film doped with impurities at a high concentration was deposited on the gate oxide film 23 and patterned to form an upper gate electrode 24.

Next, as shown in FIG. 2B, 1 × 10 ¹⁵ cm ^{−2 of} arsenic ion (serving as a source / drain) 25 is implanted using this gate electrode 24 as a mask, and then fluorine ion 26 is implanted. The arsenic ion implantation region and the channel region at the end of the gate electrode were implanted by oblique implantation. After that, impurities were activated, a cover film was formed and wiring was formed according to a normal manufacturing process, and a silicon nitride film was further deposited and heat treatment was performed at 450 ° C. to complete a transistor.

Since the fluorine ions are light, it is possible to implant the fluorine ions up to the channel region if the electrode 24 of the upper gate is thin, but the impurities in the polycrystalline silicon layer are adversely implanted into the channel region. There is.
Since the injection region was limited to the source / drain region and the channel region at the end of the gate electrode, the mobility and the sub-threshold swing were hardly improved.
The leak current could be reduced to ⅕ or less of that of the first embodiment. The reason why the improvement of the leakage current is larger than that of the P-type transistor is considered to be that the impurity diffusion is suppressed by inactivating the dangling bonds at the silicon grain boundaries, and the overlap between the gate and drain regions is reduced. The effect of grain boundaries is much greater for N-type impurities than for P-type impurities). In addition, the channel length (on the mask) where the short channel effect starts to occur is 0.2 to 0.3 μ.
It could be shortened by about m.

[0016]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the polycrystalline silicon thin film is formed by implanting fluorine ions into the polycrystalline silicon film for forming the source / drain regions of the thin film transistor. Since the dangling bonds at the grain boundaries and the defective portions can be inactivated, there is an effect that the leak current of the transistor can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a lower gate type thin film transistor.

[Explanation of symbols]

10, 20, 30 Silicon substrate 11, 21, 31 Insulating film 12, 32 Lower gate electrode 13, 23, 33 Gate oxide film 14, 22, 34 Thin polycrystalline silicon film 15 BF ₂ ion 16 Photoresist film 17, 27, 37 Source region 18, 28, 38 Drain region 19 Fluorine ion 24 Upper gate 25 Arsenic ion 35 Impurity ion

Claims (1)

Claim: What is claimed is: 1. A polycrystalline silicon film to be a source / drain region is formed on a substrate via an insulating film, and then fluorine is ion-implanted into the polycrystalline silicon film. Method of manufacturing semiconductor device.