JPH056899A - Mesfet and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a resistance of an active layer at a source side of a lower part of a metal gate of a GaAsFET, etc. CONSTITUTION:An impurity concentration of an active layer 2 under a gate metal 8 is differentiated correspondingly from a source region toward a drain region. In order to differentiate the impurity concentration, an insulating film 3 of an inclined thickness is previously formed as a mask, and then an n-type or P-type impurity is ion implanted. Thus, the impurity concentration of the active layer is enhanced at the source side thereby to sufficiently reduce a source resistance, thereby improving performance as a high frequency FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, the present invention relates to a method for forming an active layer of MESFET such as GaAs used for ultra high frequency applications.

[0002]

2. Description of the Related Art Conventionally, for example, GaAsME for ultra high frequency applications
The method for forming the active layer of the SFET is to improve the high frequency performance such as noise figure (NF) and gain (Gain) in order to reduce the source resistance and improve the drain conductance.
As shown in FIG. 2, a high-concentration layer is provided on the source side and the drain side by an ion implantation method as shown in FIG. 3, or as shown in FIG. It has been attempted to realize an offset structure in which the drain side is provided separately.

2 to 4, A is a source electrode metal and D is a drain electrode So and a drain ohmic electrode Do are in electrical contact with each other. GA is a gate metal and is provided at the bottom of the recess region R in FIG. Further, in FIG. 4, Sc is a source region high concentration layer, and Dc is a drain region high concentration layer. And the gate metal G is
On the active layer A between the source region Sc and the drain region Dc,
It is provided by forming a so-called Schottky junction.

[0004]

The above-mentioned conventional method of forming the active layer of GaAs MESFET is a method for improving the performance by controlling the concentration and thickness of the active layer in the vicinity of the gate. However, it is difficult to control the active layer directly under the gate, which is the most important factor, and there is a limit in achieving improvement in performance.

[0005]

The MESFET of the present invention is characterized in that the impurities in the performance layer below the gate are made different according to the direction from the source region to the drain region.

In the manufacturing method of the present invention, in order to control the concentration and thickness of the performance layer below the gate, an insulating layer such as an oxide film or a nitride film having a thickness inclined from the source to the drain is formed. And a step of implanting ions through an insulating film having a slope, and a step of activating the impurities by annealing the ion-implanted layer.

[0007]

According to the above structure, the active layer just below the gate is formed by the impurities ion-implanted through the insulating film having a slope,
Since the active layer can be formed so as to have a high concentration on the source side and a low concentration on the drain side, the resistance on the source side can be reduced.

Further, when the operating bias is applied, the depletion layer at the drain end immediately below the gate electrode is likely to spread, so that the saturation characteristic of the drain current with respect to the source-drain voltage is improved and the drain conductance can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A to 1F are sectional views in order of steps of a GaAs MESFET according to a first embodiment of the present invention. Figure 1
(A) is a step of forming an n-type FET active layer 2 on a semi-insulating GaAs substrate 1 and then forming an insulating film 3 such as SiO ₂ or Si ₃ N _{4 having a} film thickness of 4000 Å to 10000 Å, and then referring to FIG. As shown in b), using the PR, that is, the photoresist 4 as a mask, the region 3g of the insulating film 3 which will be the gate later is etched to a film thickness of 1000 angstroms to 3000 angstroms to form a recess, and then FIG. A step of tilting the substrate 1 as shown in (C), dipping it in a solution containing silanol, curing in a tilted state, and forming a silica film 5 having a tilted thickness in the recesses etched in the previous step. , Then Fig. 1
As shown in (d), dry etching is performed under conditions such that the etching rates of the silica film 5 and the insulating film 3 are appropriate, and the insulating film in the concave portion which will be the gate region is reduced to 0 on the thin side.
˜several hundred angstroms, a step of processing so as to be 500 angstroms to 1000 angstroms on the thick side, and then removing the insulating film 3 in the region serving as the source and the region serving as the drain as shown in FIG. Then, Si ⁺ is ion-implanted with appropriate acceleration energy to form the n-type high-concentration layer 7 in the source / drain regions and the n-type impurity layer 6 with a gradient concentration in the gate region, and then anneal to activate the implanted impurities. The process and the process of forming the gate metal 8 and then forming the ohmic electrodes 9 and 10 on the source and drain and the source and drain electrode metals 11 and 12 on the ohmic electrode as shown in FIG. is there.

When the manufacturing method of the present invention is used, the impurity concentration immediately below the gate region can be made high on the source side and low on the drain side, thereby reducing the source resistance and expanding the depletion layer at the drain end immediately below the gate electrode. GaAsME with improved drain conductance, which facilitates the operation and has excellent drain current saturation characteristics with respect to the source-drain voltage.
SFETs can be manufactured.

Next, as a second embodiment, FIG.
In the step shown in (d), the step of processing the insulating film so that the source side is thicker and the drain side is thinner, contrary to the first example, and in the step shown in FIG. Although Si ⁺ which is an impurity is ion-implanted, in the second embodiment, a step of ion-implanting Be ⁺ which is a P-type impurity,
After that, the process includes the step of forming the MESFET as in the first embodiment. According to the second embodiment, by properly adjusting the Be ⁺ ion implantation conditions, it is possible to lower the active layer on the drain side without reducing the impurity concentration of the active layer on the source side. The same effect as can be obtained.

Further, as a third embodiment, a window portion reaching the active layer 2 is formed in the insulating film 3, and a silica film having an inclined thickness is formed in this window portion as in the first embodiment. Alternatively, P-type or N-type impurities may be ion-implanted through the silica film.

Furthermore, as a fourth embodiment, P-type or n-type impurities may be ion-implanted through a laminated film of a thin insulating film and an inclined silica film.

[0014]

As described above, by using the method for manufacturing a semiconductor device according to the present invention, the impurity concentration of the active layer just below the fine gate, which is difficult with the conventional manufacturing method, is high on the source side and high on the drain side. It is possible to lower the source resistance and facilitate the spread of the depletion layer at the drain end directly under the gate electrode, and the drain current saturation characteristics with respect to the source-drain voltage can be improved to improve the drain conductance. Further, there is an effect that the breakdown voltage of the gate / drain can be further improved. Therefore, it is possible to provide a GaAs MESFET having excellent performance that is used in high frequency applications.

[Brief description of drawings]

FIG. 1 shows a GaAs showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing the structure of a conventional MaAa MESFET.

FIG. 3 is a sectional view showing the structure of a conventional MaAa MESFET.

FIG. 4 is a sectional view showing the structure of a conventional MaAa MESFET.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 FET active layer 3 insulating film 4 PR photoresist 5 Silica film 6 Graded impurity layer 7 High concentration layer 8 gate metal 9 Source ohmic electrode 10 Drain ohmic electrode 11 Source electrode metal 12 Drain electrode metal

Claims (4)

[Claims] 1. A FET active layer is formed on a compound semiconductor substrate, a source region and a drain region are further formed, and a Schottky junction is formed on the FET active layer between the source region and the drain region. MES with metal gate
In the FET, the MESFE is characterized in that the impurity concentration of the FET active layer below the metal gate is made different according to the direction from the source region to the drain region.
T. 2. A FET active layer is formed on a compound semiconductor substrate, a source region and a drain region are further formed, and a Schottky junction is formed on the FET active layer between the source region and the drain region. MES with metal gate
In the FET manufacturing process, the FE under the metal gate
After forming an insulating film having a thickness inclined in the direction from the source region to the drain region on the T active layer in advance as a mask,
Ion implantation of n-type or P-type impurities through the insulating film to make the impurity concentration of the FET active layer below the metal gate different depending on the direction from the source region to the drain region. Characterized by MESFE
Method of manufacturing T. 3. A FET active layer is formed on a compound semiconductor substrate, a source region and a drain region are further formed, and a Schottky junction is formed on the FET active layer between the source region and the drain region. MES with metal gate
In the FET manufacturing process, the FE under the metal gate
After forming an insulating film having a thickness inclined in the direction from the source region to the drain region as a mask on the T active layer in advance,
Manufacturing in which n-type or P-type impurities are ion-implanted through the insulating film to make the impurity concentration of the FET active layer below the metal gate different depending on the direction from the source region to the drain region. Regarding the method, a step of forming an insulating layer having a uniform thickness on the FET active layer, and a metal gate of this insulating layer are provided as means for making the insulating film have a thickness inclined from the source region to the drain region. A step of forming a recess by etching only a region to be formed, and a silanol solution is supplied to the recess of the insulating film, and the silanol solution supplied to the recess is solidified while the compound semiconductor substrate is tilted. A step of forming a tilted silica film, and a step of dry etching the insulating film through the tilted silica film to form a tilted insulating film. Method for producing a MESFET, wherein Mukoto. 4. A FET active layer is formed on a compound semiconductor substrate, a source region and a drain region are further formed, and a Schottky junction is formed on the FET active layer between the source region and the drain region. MES with metal gate
In the FET manufacturing process, the FE under the metal gate
After forming an insulating film having a thickness inclined in the direction from the source region to the drain region as a mask on the T active layer in advance,
Manufacturing in which n-type or P-type impurities are ion-implanted through the insulating film to make the impurity concentration of the FET active layer below the metal gate different depending on the direction from the source region to the drain region. Regarding the method, as a means for making the insulating film have a thickness inclined in the direction from the source region to the drain region, the FET is formed by etching only the portion where the metal gate of the insulating film having a uniform thickness is to be formed.
A method for manufacturing a MESFET, characterized in that a compound semiconductor substrate having a window formed up to an active layer is arranged in a tilted manner, a silanol solution is stored in the window and is then stored, and a silica film as an insulating film is provided. .