JPH05713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal drive circuit for driving a liquid crystal display device, and particularly to a liquid crystal drive circuit suitable for a complementary MIS integrated circuit.

Oscillator circuits are used in microcomputers and computers that use ICs to generate operating clock signals. However, if this oscillation circuit is kept operating all the time, power consumption will increase considerably. Therefore, when the system is stopped, the clock signal is no longer necessary, so the oscillation of the oscillation circuit is stopped to reduce power consumption.

On the other hand, when the system is stopped,
A liquid crystal display is also often unnecessary. Moreover, when the driving method of the liquid crystal display device is, for example, multiplexing display using the voltage averaging method, the clock signal is lost when the oscillation of the oscillation circuit is stopped, so the liquid crystal driving circuit must also be stopped.

In this case, if the liquid crystal drive circuit is stopped without taking any precautions, the output signal level of the final output stage (driver) will depend on the data signal.
As a result, when the drive is stopped, the external terminals of the liquid crystal display device are no longer fixed at zero volts, and there is a possibility that the liquid crystal display device enters a stopped state with the direct current bias voltage applied to the liquid crystal.

Therefore, if the liquid crystal drive circuit is stopped in such a state, the applied voltage deteriorates the liquid crystal, resulting in a disadvantage that the life of the liquid crystal display device is shortened.

Therefore, the present invention uses a relatively simple circuit configuration to fix the level of the final output stage, that is, the external terminal of the liquid crystal display device, to approximately zero volts when the liquid crystal drive circuit stops due to the stoppage of the oscillation circuit. The purpose is to prevent the liquid crystal from entering a stopped state with a bias voltage applied to it, prevent the terminals of the liquid crystal display from floating, and prevent the liquid crystal display from turning on due to noise. .

The present invention will be explained below based on the drawings.

FIG. 1 shows a driving circuit for a segment type liquid crystal display device as an example. This drive circuit is configured to perform multiplexing display using the 1/3 bias method.

Although not particularly limited, the liquid crystal display device 1 is formed so that one digit consists of seven display segments and can display numbers. Common segment electrodes 2a, 2b, 2c, . . . of each digit are connected internally to a segment drive circuit 3a.

The common electrode on the back surface is divided into three parts, although not particularly limited, and each common electrode 4a, 4b, 4c is connected to a common electrode drive circuit 3b, respectively.

The drive circuits 3a and 3b have voltages V ₀ , 2/3V ₀ , 1/3V ₀ , and 0V generated by suitable voltage dividing circuits, etc.
are supplied respectively. The voltage V ₀ is selected to have an appropriate magnitude higher than the effective value of the liquid crystal lighting threshold voltage caused by the AC drive voltage signal. Here, V ₀ is chosen to be −3V. Therefore, the other voltages 2/3V ₀ become -2V and 1/3V ₀ become -1V.

Furthermore, data signals φ _d1 to _{φ do} outputted from a circuit that determines display numbers based on data output from an arithmetic circuit (not shown) or the like are input to the drive circuits 3a and 3b. Drive circuit 3a, 3
The gate circuits 5a and 5b at the previous stage of the circuit 5b generate and output drive signals φ ₁ to _{φ 4} in response to a clock signal.
In the drive circuits 3a and 3b, the above drive signals φ ₁ to _{φ 4}
One of the voltages -3V, -2V, -1V, _{and 0V} is selected by , and each electrode 2a, 2b, . . . and 4a- 4c, segment signal in time division method
Supply P _s and common signal P _c to light up the liquid crystal.

That is, the segment electrodes 2a, 2b... and the common electrodes 4a to 4c are controlled by the drive circuits 3a, 3b.
In between, a voltage of ±3V is applied to the selected point, and a voltage of ±1V is applied to the half-selected point and the non-selected point. Further, the drive circuits 3a and 3b drive the liquid crystal by applying AC waveforms with the above amplitudes to the selected point, half-selected point, and non-selected point, respectively, so that the average voltage applied to the liquid crystal becomes zero. Prevents deterioration.

Furthermore, when the same signal as the control signal ψ _c for stopping the oscillation circuit is received, the gate circuits 5a and 5b output any of -3V, -2V, -1V, and 0V to the drive circuits 3a and 3b. It outputs drive signals φ ₁ to _{φ 4} that prevent selection of the signals. When the control signal ψ _c is input, the drive circuits 3a and 3b control the level of the output stage, that is, the electrodes 2a and 2b.
..., 4a to 4c are operated to set them to zero volts.

Next, the specific circuit configuration of the drive circuits 3a and 3b will be explained. FIG. 2 shows a common electrode drive circuit 3b that drives common electrodes 4a to 4c divided into three parts.
An example is shown below.

This common electrode drive circuit 3b is operated by drive signals φ ₁ to _{φ 4} from the gate circuit 5b and includes switch circuits 6a and 6b for selecting voltages to be applied to the common electrodes 4a to 4c, and data Drivers 7a, 7b, 7 as output stages driven by signals φ _d1 to _{φ d3} to determine the output level
c, and a clamp circuit 8 that is turned on and off by a control signal _φc .

Note that the common electrode drive circuit 3b has three drivers 7a to 7 because the common electrode is divided into three parts.
However, in the segment drive circuit 3a, the same number of drivers with the same configuration as the segment electrodes are provided. Since the other configurations are exactly the same, only the common electrode drive circuit 3b will be described below.

First, the switch circuit 6a is composed of a p-channel type switch _MISFETQ1 and an n-channel type switch _MISFEQ2 connected in series, and voltages 0V and -1V are applied to both ends thereof. MISFETQ ₁
The common connection point a of Q2 and _Q2 is connected to the common power supply line _l1 . The gates of MISFETQ ₁ and Q ₂ are supplied with drive signals φ ₁ and φ ₂ from the gate circuit 5b, respectively, and the drive signals φ ₁ and φ ₂
One of MISFETQ ₁ and Q ₂ is turned on and the other is turned off. As a result, a voltage of either 0V or -1V is supplied from the node a to the common power supply line _l1 .

On the other hand, the switch circuit 6b is made up of n-channel type switches MISFET _Q3 and _Q4 connected in series, and -2V and -3V are applied to both ends thereof.
Also, the base of each MISFETQ ₃ and Q ₄ is commonly connected to the source of MISFETQ ₄ . MISFETQ ₃ and
The connection point b of Q ₄ is connected to the common power supply line l ₂ , and MISFETs Q ₃ and Q ₄ are selectively turned on and off by drive signals φ ₃ and φ ₄ supplied to their gates. Supply -2V or -3V to power line _l2 .

The drivers 7a, 7b, and 7c are p-channel type drivers connected in series between the common power supply lines _l1 and _l2 .
Consists of MISFETQ ₅ and n-channel type MISFETQ ₆ . Among these, the source of the n-channel type MISFETQ ₆ is connected to the base (p-well region).

A data signal φ _d is supplied to the gates of MISFETQ ₅ and Q ₆ , and the “0” level (0V) of the data signal φ _d turns on PMISFETQ ₅ and turns off nMISFETQ ₆ . Also, when the data signal φ _d is at the "1" level (-3V),
pMISFETQ ₅ is turned off and nMISFETQ ₆ is turned on.

As a result, one of the four voltages of the common power supply lines l ₁ and l ₂ is supplied to the node c, which is the output part, and is connected to the external terminal of the liquid crystal as a common signal P _c .

For example, if the data signal φ _d is "0" and the power line l ₁ is 0 V, the common signal P _c is 0 V; if φ _d is "0" and the power line l ₁ is -1 V, the output P _c is −
It becomes 1V. Also, if φ _d is "1" and the power line l ₂ is -2V, the output P _c will be -2 V, and if φ _d is "1" and the power line l ₂ is -3 V, the output P _c will be -3 V. Become.

Next, the clamp circuit 8 connects a pair of switches.
Consists of MISFETQ ₇ and Q ₈ . MISFETQ ₇ is connected between common power supply line l ₁ and ground level (0V).
Also, MISFETQ ₈ is connected between the common power supply line _l2 and the ground level. MISFETQ ₇
A control signal ψ _c for stopping the oscillation circuit is supplied to the gates of Q and Q ₈ , and when the control signal ψ _c is set to the "1" level (-3V), both MISFETs Q ₇ and Q ₈ are turned off. When turned on, the common power supply lines _l1 and _l2 are connected to ground level (0V). At this time, as mentioned above, from the gate circuit 5b, the switch circuits 6a and 6b are connected.
Drive signals ψ ₁ to ψ ₄ are supplied to MISFETQ ₁ to Q ₄ to turn them all off. Therefore,
When MISFETQ ₇ and Q ₈ are turned on by the control signal ψ _c , since voltage is no longer supplied from the switch circuits 6a and 6b, the common power supply line
Both l ₁ and l ₂ are fixed at 0V.

As mentioned above, when the common power supply lines l ₁ and l ₂ are fixed at 0V, if the data signal φ _d is "0",
Since MISFETQ ₅ is turned on, node c becomes 0V, which is the same as power line l ₁ , and the external terminal of the liquid crystal becomes 0V.
be made into

On the other hand, when the data signal φ _d is “1”,
MISFETQ ₅ is turned off. At this time,
When MISFETQ ₆ is turned on, node c is immediately set to 0V since power line l ₂ is already fixed at 0V by MISFETQ ₈ . However, due to the previous state, the potential of node c is -1V.
When it reaches ~-3V, nMISFETQ ₆ becomes like the source and drain are reversed, so
MISFETQ ₆ cannot be turned on.

However, since the source of MISFETQ ₆ is fundamentally connected, a diode is formed by the pn junction between the n-type drain region of MISFETQ ₆ and the substrate (p-well region). That is, at this time
The base of MISFETQ ₆ is connected to the source and is at 0V, so if node c is -1V to -3V, the charge at node c will be transferred from the drain to the base due to the diode characteristics of the pn junction between the drain region and the base. It will be extracted to the source side through. As a result, the potential difference between the node c and the power supply line _l2 is brought close to the threshold voltage of the diode (approximately -0.7V).

Therefore, the level of node c will quickly approach -0.7V regardless of the previous level. Therefore, the level of node c is -
When it reaches 0.7V, the charge is slowly removed through the surrounding leakage current path, and eventually node c is brought to 0V.

The above operation will be explained more clearly using FIG. 3. FIG. 3 schematically shows the IC cross-sectional structure and wiring of the drive circuit.

Although not particularly limited, the circuit is an N-type semiconductor substrate 1
0. Q ₄ to Q ₈ are MISFETs corresponding to MISFETs Q ₄ to _{Q 8} shown in FIG.

P-channel type MISFETs Q ₅ , Q ₇ , and Q ₈ are formed directly on the N-type semiconductor substrate 10 . N-channel type MISFETs Q ₄ and Q ₆ are located in p-well regions 11a and 1 provided on an N-type semiconductor substrate 10, respectively.
It is formed on the surface of 1b.

A wiring l ₃ for supplying a data signal ψ _d is connected to the gate electrodes G _{5 and} G ₆ of the MISFETs Q ₅ and Q 6 .
n-type drain region D ₅ of MISFETQ ₅ and MISFETQ ₆
is connected to the p-type drain region _D6 by a wiring _l4 , and a common signal _Pc is output from this wiring _l4 .

Note that the semiconductor substrate 10 is biased to 0V by the connection between the p-type source region S ₈ connected to the ground level of the MISFETQ ₈ and the substrate.

Therefore, consider the case where the data signal φ _d is "1" (-3V). At this time, MISFETQ ₅ is turned off. On the other hand, by the control signal φ _c
When MISFETQ ₈ is turned on, the voltage on the source S ₈ side
0V is supplied to the n-type source region _S6 of _MISFETQ6 via the wiring _l2 connected to the p-type drain region _D8 . At this time, since the n-type source region S ₆ of MISFETQ ₆ and the p-well region 11b are connected, the p-well region 11b is also set to 0V.

Then, the output node c becomes − due to the previous state.
When the voltage is set at 1V to -3V, a forward voltage is applied to the pn junction between the p-well region 11 and the n-type drain region _D6 , and it functions as a diode.
As a result, the charge at node c is removed, and the potential at node c is rapidly brought close to -0.7V, which is the threshold voltage of the pn junction. After that, the charge at node c is removed due to leakage in the periphery and becomes 0V.

Next, noise is introduced for some reason and node c
Consider the case where the level of

In this case, when the potential of node c drops below -0.7V, the drain region D ₆ of MISFETQ ₆ and p
The pn junction between the well regions 11b acts as a diode _d1 . Therefore, the charge at node c is removed and the potential at node c is set to -0.7V.

On the other hand, when the potential of the node c increases due to noise, the pn junction between the p-type drain region D ₅ of the MISFET Q ₅ and the N-type semiconductor substrate 10 functions as a diode d ₂ . Therefore, when the potential of node c exceeds 0.7V, which is the threshold voltage of diode _d2 , current flows through this pn junction, the voltage of node c becomes 0.7V, and then the potential of node c gradually becomes zero. can be approached.

Further, in the segment drive circuit 3a, each output node is set to ±0.7V in the same manner as described above.

Therefore, the external terminal of the liquid crystal display device 1 has a voltage of ±0.7V.
It will be clamped to.

In other words, for the drive circuits 3a and 3b,
The state of the driver when driving is stopped can be expressed as an equivalent circuit as shown in FIG.

In this circuit, node c is the diode _d1 appearing on MISFETQ ₆ and the diode d1 appearing on MISFETQ ₅ .
d ₂ connection point. Both ends of diodes _d1 and _d2 are fixed at ground level.

Therefore, the potential of the node c, that is, the terminal of the liquid crystal display device, is easily clamped to ±0.7V by the diodes d ₁ and d ₂ . Since this voltage is lower than the threshold voltage required to turn on the liquid crystal, it is possible to prevent the liquid crystal display from turning on due to noise.

Note that the resistance R shown in FIG. 4 represents the channel resistance of _MISFETQ6 .

By the way, in the drive circuit as shown in FIG. 2, gate circuits are provided in front of each of the drivers 7a to 7c, and MISFETQ ₅ is turned on regardless of the data signal _φd supplied to the driver. It is also possible to force the level of node c to 0V.

However, such a gate circuit must be provided for each driver, and the number of drivers is just the number of segment electrodes plus the number of common electrodes, so the number of gate circuits increases and the required The disadvantage is that the number of elements increases and the chip area increases.

In contrast, in the liquid crystal drive circuit of the present invention, there is no need to provide a gate circuit in front of each driver, and it is sufficient to simply provide a clamp circuit that fixes the common power supply line to 0V. Therefore, with a simple circuit configuration, when the liquid crystal drive is stopped, the external terminal of the liquid crystal display device can be fixed at 0V to prevent deterioration of the liquid crystal. This improves the life of the liquid crystal display device and prevents the liquid crystal from turning on due to noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal drive device, FIG. 2 is a circuit configuration diagram of a drive circuit showing an embodiment of the present invention, FIG. 3 is a schematic cross-sectional view of the main parts of this circuit, and FIG. The figure shows an equivalent circuit of the driver circuit when the drive is stopped. DESCRIPTION OF SYMBOLS 1...Liquid crystal display device, 3a, 3b...Drive means (drive circuit), 5a, 5b...Gate circuit, 7a, 7
b, 7c...output stage (driver), 8...clamp means (clamp circuit).

Claims (1)

[Claims] 1. A plurality of output stages that sequentially output predetermined voltages to be supplied to each external terminal of the liquid crystal display device in accordance with a data signal, and a first output stage that forms a voltage to be supplied to the output stage. and a second voltage forming means, wherein the plurality of output stages are coupled to the first voltage forming means via a first common voltage supply line; The first clamp circuit is coupled to the second voltage forming means via a second common voltage supply line, and the first clamp circuit is composed of a first MISFET. The gate of the first MISFET is configured to receive a drive stop control signal, the source of the first MISFET is coupled to a ground potential,
The drain of the first MISFET is coupled to the first common voltage supply line, and when the drive stop control signal is supplied, a ground potential is supplied to the first voltage supply line; A second clamp circuit coupled to the second common voltage supply line includes a second MISFET, the gate of the second MISFET receives a drive stop control signal, and the second clamp circuit is connected to the second common voltage supply line. The source of the MISFET is coupled to ground potential,
The drain of the second MISFET is coupled to the second common voltage supply line, and when the drive stop control signal is supplied, a ground potential is supplied to the second voltage supply line; The first voltage forming means is switch-controlled to select the first and second voltages, and the first voltage forming means is switch-controlled to select the first and second voltages.
and a third, third clamping means which is switch-controlled to an off state when the second clamping means is operated.
It consists of 4 MISFETs, the output of which is coupled to the first common voltage supply line, and the second voltage forming means is switch-controlled to select the third and fourth voltages, and the second voltage forming means is switch-controlled to select the third and fourth voltages.
and a fifth and fifth clamping means which is switch-controlled to an off state when the second clamping means is operated.
6MISFET, the output of which is coupled to the second common voltage supply line, and the output stage is configured to connect the first common voltage supply line and the second common voltage supply line by means of a display data signal. Complementary type that alternatively selects
A liquid crystal drive circuit characterized by comprising a MISFET. 2. A common electrode drive circuit having a plurality of output stages and a segment electrode drive circuit having a plurality of output stages that perform multiplexing display using a voltage averaging method operated by a clock signal formed based on the operation of an oscillation circuit. A system operation is performed in which calculation processing is sequentially advanced by an operation clock signal formed based on the operation of the oscillation circuit, and the oscillation of the oscillation circuit is controlled in order to reduce power consumption of the system. The electronic circuit system is configured to be stopped by stopping the system, the electronic circuit system comprising two voltage supply lines common to a plurality of output stages of the common electrode drive circuit and the segment electrode drive circuit. The two common voltage supply lines of the plurality of output stages are controlled in operation by the operation control signal of the oscillation circuit, and when the operation control signal is at the oscillation stop level, the liquid crystal of the liquid crystal display device is supplied with the voltage. An electronic circuit system comprising clamping means for reducing applied voltage to substantially zero.