JPH05715B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention generates a video signal for displaying characters such as a channel number and a time display on a cathode ray tube (CRT), and also allows for extremely easy switching of these displays. can be done efficiently
Concerning large-scale integrated circuits for CRT displays.

Conventional configurations and their problems In recent years, efforts have been made to add various functions to television receivers, and as mentioned above, there is a function that can display channel numbers, time, etc. on specific parts of the screen. Television receivers with this feature have now been realized.

FIG. 1 is a diagram showing the state of the screen and its display principle when, for example, the time of 12:35 (12:35) is displayed. The time of 12:35 will be displayed on the screen.

In Figure 2, one dot is composed of two scanning lines and two oscillation output pulses (Posc), and one character is displayed with 5 x 7 dots, and one line is an X character, and the whole is a Y character. 1 is a block diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display capable of displaying lines in rows; counter 2, RS flip-flop 3, hexadecimal counter 4,
X-ary counter 5, data memory 6, N-ary counter 7, RS flip-flop 8, hexadecimal counter 9,
It consists of a Y-adic counter 10, a character generator (read-only memory) 11, an output circuit 12, and a NOR gate 13. Note that 14 is a terminal to which a vertical synchronizing signal is applied, 15 is a terminal to which a horizontal synchronizing signal is applied, 16 is a terminal to which data is input, and 17 is a terminal to which a signal to the video circuit is output.

By the way, when the display illustrated in FIG. 1 is performed under control by a large-scale integrated circuit having such a circuit configuration, since one line is a time display of five characters, the Configure. On the other hand, since the number of display lines is one, the Y-adic counter 10 is not necessary. Therefore, the Y-base counter 10 shown in FIG. 2 is removed, and the overflow output terminal OVF of the hexadecimal counter 9 and the clear terminal of the RS flip-flop 8 are
The configuration is such that the CLR is directly connected.

The large-scale integrated circuit for CRT display having the configuration described above performs the following operations.

(1) Input data to be displayed on the television receiver from terminal 16 to data memory 6.

(2) When the vertical synchronization signal indicating the start of one screen of the television receiver is input to the terminal 14, the n-ary counter 7 and the RS flip-flop 8
and all hexadecimal counters 9 are cleared,
Output from the output terminal 17 to the video circuit is disabled.

(3) When the horizontal synchronization signal is input from terminal 15 after the vertical synchronization signal disappears, the n-ary counter 7
performs a counting operation, and when the horizontal synchronizing signal is input n times, it overflows and sets the RS flip-flop 8. By setting the RS flip-flop 8, a vertical display state is established.

(4) When a horizontal synchronizing signal is input, the m-ary counter 2, RS flip-flop 3, decimal counter 4, and 5-ary counter 5 are all cleared, and the horizontal display is initialized. As a result, the display is rendered invalid. Furthermore, the oscillation of the oscillation circuit section 1 is also stopped.

(5) When the horizontal synchronization signal disappears, the oscillation circuit section 1 starts oscillating and outputs a signal at a predetermined frequency.

(6) The output signal from the oscillation circuit section 1 is input to the m-ary counter 2, and the m-ary counter 2 overflows due to the arrival of m oscillation output pulses.
RS flip-flop 3 is set. When the RS flip-flop 3 and the RS flip-flop 8 of the vertical synchronizing signal section are both set, only the portion enabled in both the vertical and horizontal directions will be displayed.

Figure 3 shows the output of the character generator 11, the hexadecimal counter 4 and the output of the character generator 11 when the above display is made.
3 is a diagram showing the relationship between hexadecimal counters 9. FIG.

(7) Read the data addressed by the quinary counter 5 and the contents of the character generator 11 addressed by the hexadecimal counter 4 and the hexadecimal counter 9, and send them to the output circuit 12 and the output terminal 17.
The signal is then output to the video circuit. That is, in the initial state, the quinary counter 5 has the first data,
When displaying 12:35, the number 1 is addressed, and as shown in Figure 3, the hexadecimal counter 9 addresses the highest dot among the vertical dots, and the hexadecimal counter 4 addresses the horizontal dot. The leftmost dot among the five dots is addressed. At this time, there is no character output from the character generator 11, as shown by the broken line in FIG.

(8) The hexadecimal counter 4 receives the oscillation output pulse from the oscillation circuit section 1, executes a counting operation, and obtains an output corresponding to the address from the character generator 11. In the example shown in FIG. 3, there is no output in the period 0 to 3, there is character output in the period 4 to 5, and there is no output in the period 6 to 9. Note that the period 10 to 11 corresponds to the interval between adjacent characters, and there is no output to the video circuit during this period, regardless of data.

(9) When the hexadecimal counter 4 overflows, one count input is added to the quinary counter 5, and the next data in the data memory 6, the number 2, is addressed when displaying 12:35. Thereafter, video signals are output in the same manner, and a display signal output of five characters corresponding to one scanning line is obtained. Then, if the display signals for 5 characters are output in sequence, 5 characters will be displayed.
The advance counter 5 overflows and the character generator is disabled and there is no display signal.

(10) Next, when the horizontal synchronization signal is input, one count input is added to the hexadecimal counter 9, and the operations (5) to (9) described above are repeated, corresponding to one next scanning line. Outputs display signals for 5 characters. Thereafter, scanning is performed sequentially in the same manner, and the display ends when the hexadecimal counter 9 overflows.

FIG. 4 is a diagram showing the relationship between the CRT display described above, the scanning line, and the output of the character generator 11. As shown in FIG. 4a, the display (12:
35) is performed during the scanning period from the nth scanning line to the n+13th scanning line. Also, Figure 4b
is a timing chart showing the relationship between the horizontal synchronization signal (Hsync), the output of the oscillation circuit section 1 (OSC), and the output signal of the character generator 1 during the nth to n+2th scans, as shown in the figure. When the horizontal synchronization signal Hsync disappears, the oscillation output is output from the oscillation circuit section 1, and the nth and n+
During the first scan, the character generator 11 has character signal outputs corresponding to the four characters 1, 2, 3, and 5;
There are character signal outputs at locations corresponding to the five characters. Thereafter, character signals are output until the (n+13th) scan, and 12:35 is displayed as shown in FIG. 4a. Note that the display based on the output signal in FIG. 4b is assumed to be a white display on the screen when the video circuit is at ground level. That is, when the character signal output of the high level "H" shown in FIG. 4b is generated from the character generator 11 in the circuit shown in FIG. By setting the level to the ground level, the video circuit can be selectively set to the ground level. By the way, when the output signal level of the character generator 11 is at a low level "L", the above-mentioned transistor is turned off and the video circuit is not affected in any way, and the image being received is displayed. Further, while the character generator is in an invalid state, the character generator outputs the "L" level regardless of the address and operates so as not to affect the screen.

Figure 4c schematically shows the time relationship between the vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), and character signal input (CHYR), as well as the relationship between the horizontal synchronization signal (Hsync), display, and character signal output (CHAR). This is the diagram shown in Figure 4, except for the relationship between Vsync and Hsrnc.
As shown in Figures a and b.

A conventional large-scale integrated circuit for CRT display has the above-mentioned configuration and performs an operation of displaying the time and the like on the screen. By the way, such conventional
Although displays using large-scale integrated circuits for CRT displays were made in terms of time or channels, the number of characters that could be displayed was about 10 at most.

However, as television receivers and video tape recorders rapidly become more sophisticated, it becomes necessary to display a large number of characters, far exceeding the 10 characters mentioned above, and to display characters in color. It's reached.

FIG. 5 shows a conventional example of a CRT display for home video, and shows a display screen for inputting or checking a program as an example. The meaning of the screen is program 1 out of many programs.
(PROG1) shows that on Sunday (SUN), channel 10 will start recording on the VTR at 10:45 (ONTIME 10:45) and will end at 11:30 (OFFTIME 11:30). Also, the display color is the fifth
In the figure, a region 32 surrounded by a broken line is blue, a region 33 surrounded by a broken line is green, and a region 34 surrounded by a broken line is red. Next, the case where the screen shown in FIG. 5 is displayed will be explained. FIG. 6 shows an example of the configuration of the data memory 6. By inputting data to the data input terminal 16, the display data random access memory (hereinafter referred to as
A write address, write data, and a write signal are generated to the display data RAM 19, and data corresponding to FIG. 5 is written to the display data RAM 19. The state at this time is shown in FIG. Figure 7 shows the X address,
The RAM address consisting of the Y address is also shown. In the parts of Figure 7 where letters such as "P" and "R" are written, codes and codes corresponding to the colors to be displayed are written on the screen in Figure 5 and at the memory addresses corresponding to each. The part indicates that a code to suppress the display is written to each RAM address. Next, the data of the X-base counter 5 and the Y-base counter 10 are input from the data input terminals 20 and 21 to the display data RAM 19, and the contents of the RAM are sequentially read out to the output line 22 according to the values, and the character generator 11 is activated. via CRT
Generates a display signal. However, in the conventional configuration example shown in Figure 6, it takes a total of 16 x 5 to display one screen.
A large display data RAM equivalent to 80 characters is required. As is clear from these facts, as devices become more sophisticated, the number of characters to be displayed increases, the color classification of the display becomes more complex, and the RAM for display data becomes larger in capacity. This increases the area occupied by the semiconductor substrate in producing large-scale integrated circuits, resulting in higher costs. Furthermore, as the capacity of the display data RAM becomes larger, the amount of data to be transferred increases, which causes significant inconvenience in terms of the processing speed of the microcomputer that controls the display and the number of program steps required. .

Purpose of the Invention The present invention has been made with the intention of eliminating such inconveniences, and focuses on the fact that when displaying characters in color, it is sufficient to use around four display colors to cope with the high functionality of devices. By reducing the amount of data written to the display data RAM 19 and adding a display color selection circuit, the display data RAM 19 is made smaller and data transfer is kept to the minimum necessary, resulting in a low-cost large-scale integration for CRT display. It is intended to provide a circuit.

Structure of the Invention The present invention includes a rewritable memory unit into which display data is input and has a first output terminal and a second output terminal, a character generator, two two-input AND circuits, and one 2-input AND circuit. It consists of a display color selection circuit having a 3-input AND circuit, and the output terminal of the character generator is connected to one input terminal of each of the three AND circuits,
At the other input end of the two 2-input AND circuits above,
The first output terminal and the second output terminal of the memory section are respectively connected, and the first output terminal and the second output terminal of the memory section are respectively connected to the other two input terminals of the 3-input AND circuit through an inverter. The present invention is a large-scale integrated circuit for CRT display connected to a CRT, and by adding the display color selection circuit, the memory capacity of the rewritable memory is reduced, making it possible to downsize the display data RAM.

DESCRIPTION OF EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

FIG. 8 is a block diagram showing the circuit configuration of a large-scale integrated circuit for CRT display according to an embodiment of the present invention.
The conventional one shown in the figure is the display color selection circuit 23.
They are different in that they have the following. The display color selection circuit 23 is configured to receive a portion of the output signal from the data memory 6 as well as the output from the character generator 11. In addition, the output circuit 12 is also provided with 12a and 12b corresponding to the output signal of the display color selection circuit 23.

FIG. 9 shows the display color selection circuit 23 shown in FIG.
FIG. 2 is a diagram showing a specific example of the configuration. In the figure, 24 is a terminal into which the output signal OUT of the character generator 11 is input, 25,
26 is a terminal into which two of the output signals of the data memory 6 are input, and 27, 28, and 29 are output terminals of the display color selection circuit 23. 27, 28, and 29 are connected to external output circuits 12, 12a, and 12b. The inside of the display color selection circuit 23 is composed of an AND gate group 30 and an inverter group 31. In the display color selection circuit 23 having the above configuration, the terminal 2
When the level of the terminal 5 is "H" and the level of the terminal 24 is "H", the level of the terminal 27 becomes "H".
Similarly, if the level of terminal 26 is "H" and terminal 2
When the level of the terminal 4 is "H", the level of the terminal 28 becomes "H". Further, when the levels of terminals 25 and 26 are both "L" and the level of terminal 24 is "H", the level of terminal 29 becomes "H". Characters are output on the CRT screen when any of the terminals 27, 28, and 29 is at the "H" level. output circuit 12,
12a and 12b are normally color signal input circuits of a CRT display circuit, but for example, 12 may be a red input circuit,
If 12a is a green input circuit and 12b is a blue input circuit, when terminal 27 is "H", a red character output is displayed on the CRT screen, and when terminal 28 is "H", a green character output is displayed, When both terminals 27 and 28 are at "H", a yellow character output is displayed, and when both terminals 27 and 28 are at "L", a blue character output is displayed. In other words, when the terminal 24 is "H" and there is a character output, the terminal 25 is "H"
If the terminal 26 is "H", the red text is displayed, and if the terminal 26 is "H", the green text is displayed, and the terminal 26 is "H".
When both terminals 5 and 26 are at "H", a yellow character is displayed, and when both terminals 25 and 26 are at "L", a blue character is output. As can be seen from the above, the color of the CRT display characters can be switched to four colors depending on the "H"/"L" signal level of the terminals 25 and 26. In the above example, terminal 2
In this case, terminals 5, 26, and 27 were connected to the red, green, and blue input circuits, respectively.
By connecting 7 and 28 to green, blue, and red input circuits, respectively, a four-color display of red, green, blue, and cyan can be obtained. In normal color display, terminal 25,
There is another terminal corresponding to the terminal 26, and eight colors are displayed depending on the levels of these three terminals. However, in order to do this, for example, in order to display the color shown in Figure 5, 16 x 5 x 3 =
250-bit data memory for color display is required.
On the other hand, according to the present invention, by using the display color selection circuit 23, the color display data memory is reduced to 16×5×2=160 bits. In this case, the colors that can be displayed are limited to four, but by changing the connection to the color input circuit, any four of the eight colors can be selected, which is sufficient to accommodate higher functionality of the device. In a large-scale integrated circuit, the board area occupied by this color display data memory is larger than that of the display color selection circuit 23 described above, and especially as the number of characters to be displayed increases, the area also increases. Adding this and reducing the number of color display data bits by 1 bit is very advantageous in realizing a large-scale integrated circuit for CRT display that is inexpensive and can sufficiently handle the increasing functionality of equipment.

Effects of the Invention As is clear from the above explanation, the large-scale integrated circuit for CRT display of the present invention reduces the memory for display data for displaying characters in color on a CRT by adding a color display selection circuit. It is possible to keep the data transfer to the minimum necessary, and it is possible to realize an extremely inexpensive and efficient CRT color display, and it is fully compatible with the increasing functionality of equipment.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the state of the screen and its display principle when a predetermined time is displayed, Fig. 2 is a diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display for displaying 5 characters, Figure 3 is a diagram showing the relationship between the output of the character generator and the hexadecimal and hexadecimal counters when a display is made, Figures 4 a to c are CRT displays,
A diagram showing the relationship among scanning lines, horizontal and vertical synchronizing signals, oscillation output, and character generator output; FIG. 5 is a diagram showing a state in which many characters are displayed in color; FIG.
The figure shows an example of the configuration of a data memory according to a conventional example, FIG. 7 shows an example of data in a display RAM according to a conventional example, and FIG. 8 shows a circuit configuration of a large-scale integrated circuit for CRT display according to the present invention. 9 are diagrams showing the circuit configuration of a display color selection circuit according to an embodiment of the present invention. 1... Oscillation circuit section, 2... m-ary counter, 3,
8... RS flip-flop, 4... Decimal counter, 5... X-ary counter, 6... Data memory,
7...n-ary counter, 9...hexadecimal counter, 10
... Y-ary counter, 11 ... Character generator, 12,
12a, 12b...externally attached output circuit, 13
...NOR circuit, 14...Vertical synchronization signal application terminal,
15...Horizontal synchronization signal application terminal, 16...Data input terminal, 17, 17a, 17b...Signal output terminal, 18...RAM control circuit, 19...RAM for display data, 20...X-ary counter output Terminal to be added, 21...Terminal to which the Y-base counter output is added,
22...Data memory unit output line, 23...Display color selection circuit, 24...Terminal to which character generator output is applied, 25, 26...Terminal to which data memory unit output is applied, 27, 28, 29...Display Output terminal of color selection circuit, 30...AND circuit, 31...Inverter circuit, 32, 33, 34...Color area.

Claims (1)

[Claims] 1. A rewritable memory section into which display data is input and which has a first output terminal and a second output terminal, a character generator, two 2-input AND circuits, and one 3-input
Consists of a display color selection circuit with an AND circuit,
The two 2-input AND circuits and one 3-input
Connect the output end of the character generator to each one input end of the AND circuit, and
The first output terminal and the second output terminal of the memory section are respectively connected to the other input terminals of the AND circuit, and the third
A large-scale integrated circuit for a CRT display, in which a first output terminal and a second output terminal of the memory section are connected to two other input terminals of an input AND circuit via inverters respectively.