JPH0571925U - Automatic power off device - Google Patents

Abstract

(57) [Abstract] [Purpose] To ensure the safety of CPU runaway while suppressing battery consumption. [Configuration] Using the alarm function of the clock IC 12, when the battery power supply 11 is turned on, the CPU 1 sets alarm time data obtained by adding a predetermined time to the current time data to the clock IC 12 (performs alarm time data setting processing), At this alarm time, the alarm signal for turning off the battery power supply 11 is output from the timepiece IC 12.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention includes a CPU that is activated by turning on a battery power when a power switch is turned on. After performing a predetermined processing operation by this CPU, the power is automatically turned off by a power off command from the CPU. The present invention relates to a power-off device.

[0002]

[Prior Art]

 The battery power is turned on by the power switch that is turned on (closed) by the operator's operation or by inserting a medium such as a magnetic card, and the CPU is started, and the CPU performs predetermined processing. An automatic power-off device that turns off battery power in response to a power-off command is used in various consumer devices and systems.

By the way, in a device of this type having a CPU, if the CPU runs out of control, the control becomes impossible and a trouble occurs. Therefore, measures are taken to prevent this.

FIG. 1 shows a block diagram of an automatic power-off device according to a conventional example. Reference numeral 1 is a CPU, and 2 is a ROM. In this circuit, a watchdog timer IC is provided outside the CPU 1 for detection and safety measures when the CPU 1 runs out of control.

FIG. 2 is a waveform diagram showing the refresh signal from the CPU 1 and the output signal of the watchdog timer IC, and the watchdog timer IC 3 is repeated with the periodic refresh signal shown in (a) supplied from the CPU 1. After refreshing, the watchdog timer IC3 continues to output the "1" level signal as shown in (b).

Since the output signal of the wash dodder timer IC3 falls to the "0" level when the refresh is stopped, it is determined that the CPU1 has runaway, and the watchdog timer IC3 outputs the "0" level signal to supply power. Processing such as disconnection processing and reset of the CPU 1 was performed.

[0007]

[Problems to be Solved by the Invention]

 However, in a device using a battery as a power source, the provision of a watchdog timer IC causes the battery to be drastically consumed, and the device does not operate unless the battery is frequently replaced. Another problem was that batteries with large capacities could not be installed in space depending on the equipment and system in which this device was installed.

It is an object of the present invention to solve the above-mentioned drawbacks of the conventional device, and to provide an automatic power-off device capable of ensuring the safety during CPU runaway while suppressing battery consumption.

[0009]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention utilizes the alarm function of a clock IC, and when the battery power is turned on, the CPU sets an alarm time data obtained by adding a predetermined time to the current time data to the clock IC (alarm). When the alarm time comes, the alarm signal for turning off the battery power is output from the clock IC.

In this case, if there is no abnormality in the CPU, the battery power supply is turned off by the power supply off signal from the CPU, but if the CPU runs away, the battery power supply is turned off by the alarm signal.

[0011]

[Action]

 When an operator operates or a medium is inserted from the medium insertion port, the power switch is turned on, the battery power is turned on, and the CPU is activated. Then, the CPU performs alarm time data setting processing for adding a predetermined time to the current time data to the clock IC, and obtains an OR between the alarm signal from the clock IC and the power-off signal of the CPU. To turn off the battery power.

[0012]

【Example】

 Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of an automatic power-off device according to the embodiment, and FIG. 4 is a flowchart showing the control contents.

In FIG. 3, 1 is a CPU, 11 is a battery power source, 12 is a clock IC, and 13 is a RAM, and the clock IC 12 and the RAM 13 are connected to the CPU 1 by a bus line. Reference numeral 14 is a driver that operates according to a command from the CPU 1, and drives the operating body 15. 16 is an OR circuit for inputting the signal line 17 of the CPU 1 and the signal line 18 of the clock IC 12, 19 is a D-flip flop to which the output line 20 of the OR circuit 16 is connected to the clear terminal (reset terminal), and 21 is a flip flop An electronic switch connected to the clock terminal of 19, a transistor 22 that conducts when the Q output of the flip-flop 19 is input to the base, and a transistor 23 that applies the voltage V DD of the battery power supply 11 to the CPU 1 It is an operation end detection switch that is opened and closed.

As is apparent from the figure, the timepiece IC 12, the RAM 13, and the flip-flop 19 are always backed up by the battery power supply 11 with the drive voltage V F F. However, the CPU 1 which consumes a large amount of current during operation has the flip-flop as described above. The battery power supply 11 drives the battery 22 at the drive voltage V D D only when the power-on signal is output from the battery pack 19 and the transistor 22 is turned on.

Next, the control contents of the present embodiment will be explained based on the flow chart shown in FIG. This flow starts when the power switch 21 is turned on by inserting a medium or manually by the operator and the drive voltage V DD is applied to the CPU 1 from the battery power source 11.

First, the current time data T (year, month, day, hour, minute, second) in the clock IC 12 is read and recorded in the RAM 13 (S1). Next, a predetermined monitoring time data t is added to this T and set in the clock IC 12 (S2), and various processes are started (S3). Then, it is judged from the state of the operation end detection switch 23 whether or not the operation is completed, and if the operation is completed (Y in S4), the processing is completed (S5), and a power-off signal is output to the signal line 17, As a result, the flip-flop 19 is reset and the transistor 22 is turned off, so that the drive power source V DD of the battery power source 11 is turned off (S6).

Here, when the CPU 1 runs out of control (S0), an alarm signal is output from the clock IC 12 to the signal line 18 after the above-mentioned time-up of t, whereby the flip-flop 19 is reset and the power supply is turned on as described above. Is turned off.

That is, when the CPU 1 is operating normally, the power is turned off by the power-off signal, and when the CPU 1 runs out of control, the power is turned off by the alarm signal, thereby providing a fail-safe function for malfunction of CPU control and battery consumption. Can be fulfilled. The alarm signal output timing is set to be slightly later than the power-off signal.

[0019]

[Effect of the device]

 As described above, according to the present invention, the alarm function of the clock IC is used to turn off the battery power by the alarm signal from the clock IC even if the CPU runs out of control. It is possible to prevent the above-mentioned problem and to accurately control the power-off to minimize the consumption of the battery.

[Brief description of drawings]

FIG. 1 is a block diagram of an automatic power-off device according to a conventional example.

FIG. 2 is a timing chart thereof.

FIG. 3 is a block diagram of an automatic power-off device according to an embodiment of the present invention.

FIG. 4 is a flowchart showing the control contents.

[Explanation of symbols]

 1 CPU 11 Battery Power 12 Clock IC 13 RAM 16 OR Gate Circuit 17, 18 Signal Line 19 Flip Flop 21 Power Switch

Claims (1)

[Scope of utility model registration request] 1. A CPU provided with a CPU that is activated by turning on a battery power supply by turning on a power switch, and after the CPU performs a predetermined processing operation, the power is automatically turned off by a power-off command from the CPU. In the automatic power-off device, a clock IC and a RAM are provided, and when the power switch is turned on, the current time data in the clock IC is read and recorded in the RAM, and an alarm time obtained by adding a predetermined time t to the current time data. Set the data in the clock IC,
The signal line of the alarm signal from the timepiece IC that is output at this alarm time is connected to the input side of the OR gate circuit together with the signal line of the power OFF signal of the CPU, and the battery power is supplied by the output of the OR gate circuit. An automatic power-off device characterized by being turned off.