JPH0572004B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a rotary head type digital signal reproducing device, and in particular, even if the sampling frequency and number of quantization bits of the signals to be recorded are different, the recording format on the recording medium can be maintained. The present invention also relates to a suitable rotary head type digital signal recording/reproducing apparatus in which the recording wavelength is constant.

[Background of the invention]

Digital signal recording and reproducing devices that convert audio signals into digital signals and record and reproduce them on recording media are beginning to be adopted in consumer equipment such as rotary head type devices that utilize existing VTRs. Furthermore, the digital signal recording and reproducing device utilizes features such as the ability to freely compand the time axis using memory and the ability to perform ultra-fidelity recording and reproducing. Playback devices are likely to be adopted in the future. An example of a conventional rotary head type digital signal recording/reproducing apparatus is shown in FIG. In Figure 1,
1 is an analog signal input terminal, 2 and 15 are sample and hold circuits, 3 and 14 are A/D converters and D/A converters, 4 and 13 are signal processing circuits, 5 is a recording amplifier, and 6 is a recording signal output terminal, 7
is a recording/reproducing head, 8 is a rotating drum, 9 is a recording medium, 10 is a head reproduction output, 11 is a reproduction amplifier,
12 is a waveform equalization circuit, 16 is an analog signal output terminal, 17 is a reference signal generator, and 18 is a clock generation circuit.

During recording, the analog signal input from the analog signal input terminal 1 is sent to the sample/hold circuit 2.
The signal is sampled by the A/D converter 3 and converted into a PCM digital signal. Next, this PCM digital signal is added with an error detection/correction code, a synchronization signal, etc. in a recording system signal processing circuit 4, is amplified by a recording amplifier 5, and is rotated at a predetermined number of rotations via a recording signal output terminal 6. The information is recorded by the recording/reproducing head 7 moving at a predetermined speed onto the recording medium 9. During reproduction, the signal recorded on the recording medium 9 is reproduced by the recording/reproducing head 7, amplified by the reproducing amplifier 11, and then corrected by the waveform equalization circuit 12 for deterioration in transmission characteristics occurring in the recording medium 9 and the recording/reproducing head 7. do. Next, the reproduction system signal processing circuit 13 performs error detection and correction, and the D/A converter 14
The signal is converted into an analog signal by the sample and hold circuit 15, and then output from the analog signal output terminal 16. In addition, sample and hold circuits 2, 15, A/D converter 3,
The D/A converter 14 and the recording system and reproduction system signal processing circuits 4 and 13 generate the clock generation circuit 1 based on the reference clock obtained by the reference signal generator 17.
It is operated by a clock generated by 8.

The digital signal recording and reproducing device shown in Figure 1 is used not only for converting analog audio signals into PCM digital signals and recording and reproducing them, but also for converting analog audio signals into PCM digital signals and recording and reproducing them.
Digital dubbing from CD players and PCM broadcasts is important. For CD players, the sampling frequency is 44.1KHz and the number of quantization bits is 16 bits, while for PCM broadcasting, the sampling frequency is 48KHz,
The number of quantization bits is 16 bits and the sampling frequency is
32KHz, quantization bit number 14 bits (companding) 2
It is a kind. As described above, there are a plurality of values for the sampling frequency and number of quantization bits of an audio PCM signal, and a PCM digital signal recording/reproducing apparatus must be compatible with these systems.

When digital signals with different sample frequencies are recorded on a recording medium running at a predetermined speed by a recording/reproducing head rotating at a predetermined rotation speed as shown in Figure 1, the shortest wavelength will depend on the sample frequency. Change. The higher the sampling frequency, that is, the higher the transmission rate, the shorter the shortest wavelength. Therefore, since the sampling frequency ratio of each system is at most 1.5 times, there were drawbacks such as when matching with a system with a lower sampling frequency, signals from other systems with a higher sampling frequency could not be recorded or reproduced.

Furthermore, in order to record and reproduce digital signals with different numbers of quantized bits, 2 bits of data other than PCM data are added to the 14-bit data with a smaller number of quantized bits to form a 16-bit shape, and the quantized bits are It is necessary to record and reproduce it in the same way as in the case of 16 bits. However, for the purpose of recording and reproducing PCM data, the 2 bits added above have no function and increase redundancy, which is extremely inefficient. In order to improve this inefficiency, it is necessary to create a new frame generation format for 14-bit quantized PCM data.
There is a drawback that the circuit scale of the signal processing circuits 4 and 13 shown in the figure is approximately doubled.

[Purpose of the invention]

The purpose of the present invention is to record and reproduce PCM data with different sampling frequencies and quantization bit numbers.
Provides a PCM digital signal recording and reproducing device that provides a PCM data frame generation format with little increase in circuit scale and no change in redundancy, and is capable of recording on a recording medium at the same recording wavelength and recording format. It's about doing.

[Summary of the invention]

In order to transmit two different numbers of quantization bits n _s1 and n _s2 in the same frame configuration, the common multiple of n _s1 and n _s2 is set as the number of PCM data bits in one frame, and the error detection and correction code is used regardless of the number of quantization bits. generates and adds symbols consisting of a fixed number of bits in units, and generates frames without changing redundancy. When recording the PCM digital signal obtained in this way, the recording on the recording medium is performed by changing the rotation speed of the rotating drum to which the recording/playback head is fixed and the feeding speed of the recording medium in proportion to the transmission rate. The wavelength and recording format can be kept constant, and PCM digital signals with different sampling frequencies and quantization bit numbers can be efficiently recorded in the same system.

[Embodiments of the invention]

Below, an example of the present invention will be described with a sample frequency of 48KHz.
Quantization bit count: 16 bits, sampling frequency: 44.1K
Hz, quantization bit number 16 bits, and sampling frequency 32KHz quantization bit number 12 bits.
The case of recording and reproducing a PCM digital signal will be explained. First, we will discuss the method and signal processing circuit for creating the same frame configuration for two different quantization bit numbers, 16 bits and 12 bits, and then explain the recording wavelength and recording method on the recording medium using the digital signals obtained in this way. This article describes a PCM digital recording/playback device that maintains a constant format.

FIG. 2 shows an example of a frame structure in which the same frame structure is used for 16-bit and 12-bit quantization according to the present invention. Figure 2a shows the frame structure in 16-bit quantization, 1a is an 8-bit frame synchronization signal pattern, 2a is 8-bit control data for recording system control information in addition to PCM data, and 3a is quantized 16 bits. PCM data is 6 samples per bit, 4a is a 32-bit code for error correction, and 5a is a 16-bit code for error detection. b is the frame configuration in 12-bit quantization, 1b is the frame synchronization signal pattern 8 bits, 2b is the control data 8 bits, 3b
is 8 samples of PCM data with 12 bit quantization,
4b is a 32-bit code for error correction, and 5b is a 16-bit code for error detection.

In FIG. 2, the number of bits of PCM data 3a and 3b is a common multiple of 16 and 12 quantization bits, 96 bits, and is constant regardless of the number of quantization bits. If this is divided into 8 bits per symbol, PCM
For data 3a, one sample of 16 bits of data is divided into two symbols as shown in Figure 3a.
It consists of W ₀ , W ₁ , ...W ₁₁ . On the other hand, PCM data 3
b, as shown in Figure 3b, divides 12 bits of data of one sample into 8 bits 1 symbol and 4 bits, and these 4 bits are divided into 4 bits generated from other samples.
Combined with the bit, it becomes a symbol, and the symbol W ₀ ,
It consists of W ₁ ,...W ₁₁ . Therefore, as is clear from FIGS. 2a and 2b, the number of symbols in one frame is constant at 12, regardless of the number of quantization bits. Here, the error correction codes 4a and 4b in FIG.
Reed-Solomon codes can be added to the symbols P ₀ , P ₁ , P ₂ , and P ₃ using the symbols W ₀ to _{W 1} of the PCM data according to equation (1) shown below.

{IW ₀ +IW ₁ +IW ₂ +…+IW ₁₁ +IP ₀ +IP ₁ +IP ₂ +
IP ₃ = 0, T ¹⁵ W ₀ +T ¹⁴ W ₁ +T ¹³ W ₂ +…+T ⁴ W ₁₁
+T ³ P ₀ +T ² P ₁ +TP ₂ +IP ₃ =0, T ³⁰ W ₀ +T ²⁸ W ₁
＋T ²⁶ W ₂ ＋…＋T ⁸ W ₁₁ ＋T ⁶ P ₀ ＋T ⁴ P ₁ ＋T ² P ₂ ＋
IP ₃ = 0, T ⁴⁵ W ₀ +T ⁴² W ₁ +T ³⁹ W ₂ +…+T ¹² W ₁₁
+T ⁹ P ₀ +T ⁶ P ₁ +T ³ P ₂ +IP ₃ =0}(1) (Here, I is the identity element, T, T ² , T ³ ,...T ⁴⁵ is the individual of Galois field (2 ⁸ ) (It is a non-zero element, and the multiplication and addition shown are operations defined by the Galois field.) Therefore, as shown in Figure 2 a and b, the number of symbols in one frame of PCM data 3a and 3b is Since they are the same, the error correction codes 4a and 4b can be generated and decoded by the same arithmetic circuit regardless of the number of quantization bits.

Moreover, the error detection codes 5a, 5b are control data 2a, 2b, PCM data 3a, 3b,
Since the error correction codes 4a and 4b each have the same number of bits, they can be added by the same arithmetic processing of the error detection code. here,
Control data 2 as error detection code
a, PCM data 3a, error correction code 4a,
Added 16-bit CRC code. Therefore, the second
According to the figure, even if the number of quantization bits is different from 16 bits to 12 bits, by making the structure of one frame common, the redundancy is constant and error detection, correction code generation, and decoding are common. can be converted into

An example of a generation circuit for the frame generation method shown in FIG. 2 is shown in the configuration diagram of FIG. 4. In Figure 4, 1
9 is a 16-bit AD converter, and the upper 8 bits are 19
The lower 8 bits of U are 51,5 every 4 bits.
Output to 2. 20U and 20 are 8-bit data latches with clock inputs 20CU and 2, respectively.
Data is latched by 0C. 21U,2
1, 26, 33 are three-state buffers, and control signals 21CU, 21C, 26
When C and 33C are "0", the output mode is "1" and becomes high impedance mode. 22 is a multiplexer that switches and outputs two 8-bit input systems, and when the control signal 22C is "0", 22A is "1"
When this happens, a 22B signal is output. 23 is a RAM (random access memory) that stores data
The 8-bit data bus 23A is connected to each circuit, and the upper 4 bits of the data bus 23A are connected to the input 22B of the multiplexer 22. A RAM address control circuit 24 performs address and write control of the RAM 23, and outputs an address to 24A and a write control pulse to 24A. 25 is a Reed-Solomon code encoder, 2
Enter the data string added to 5A and
The parity of the four symbols P ₀ , P ₁ , P ₂ , P ₃ is set to 2
Output from 5B. 27 is a parallel/serial converter (hereinafter referred to as P/S converter) which converts an 8-bit parallel signal into a serial signal; 28 is a CRC circuit which inputs the output of P/S converter 27 and generates a CRC code. 29 is a pattern generator that generates a frame synchronization signal pattern, and 31 is a switch for switching data output 31A, CRC code output 31B, and frame synchronization pattern output 31C. 32 is an output terminal, and 30 is a clock generator for generating control clocks for each of the circuits mentioned above.

First, the operation shown in FIG. 4 when the number of quantization bits is 16 bits will be explained. The control signal 22C of the multiplexer 22 is fixed at the "0" level, and the lower 8-bit signals 191 and 192 of the AD converter 19 connected to the input 22A are transmitted to the latch 20. Also, the upper 8 bit signal 19 of the AD converter 19
U joins latch 20U. Therefore, the quantization bit
16-bit data is clocked at 20CU and 20C.
is stored in the latches 20U and 20 by the latches 20U and 20.
The output of these latches 20U, 20 is the buffer 2
1U, 21 and control signal 21
CU and 21C are sequentially set to “0” level in a time-sharing manner.
Data is supplied to the data bus 23A of the RAM 23 every 8 bits. This data is stored in RAM23.
It is stored using the address 24A generated by the RAM address control circuit 24 and the write control pulse 24W. Such processing is performed by the clock generator 30.
This is repeated for each sampling frequency _s generated in . Next, processing of the output data of the AD converter 19 stored in the RAM 23 will be explained using the memory map shown in FIG. In Figure 5, RAM23
is divided into three blocks A, B, and C, and performs three processes: writing data and control data for the AD converter 19, generating error correction codes/Reed-Solomon codes _P0 to _P3 , and serial data output processing. Perform processing sequentially. That is, the following processing is performed. Block A writes control data via buffer 33, and AD converter 1
When data 9 is being fetched and processed, block B sends data W ₀ to W ₁₁ to the encoder 25.
Perform the generation process of P ₀ to P ₃ , and in block C,
Data output processing to the P/S converter 27 is performed. Next, when the above processing is completed, block A performs the generation process of P ₀ to _{P 3} on the data of the AD converter 19 that was previously taken in, and block B generates the data for which the generation of P ₀ to _{P 3} has been completed. Process the output. Block C performs data writing processing for the new AD converter 19. In this way, blocks A, B, C
Then, the above three processes are performed sequentially, and the control data PCM data and P ₀ are sent from the P/S converter 27.
~C, W ₀ , W ₁ ,..., sent out from the P/S converter 27 which outputs P ₃ as a serial signal.
The serial data of W ₁₁ , P ₀ , P ₁ , P ₂ , P ₃ is
It joins the CRC circuit 28 and generates a 16-bit CRC code. The switch 31 sequentially switches the data 31A sent out from the P/S converter 27, the CRC code 31B sent out from the CRC circuit 28, and the frame synchronization signal pattern 31C, and sends them out to the terminal 32 as final data. By the above operations, the frame shown in FIG. 2a can be generated from 16-bit quantized PCM data.

Next, the operation shown in FIG. 2 when the number of quantization bits is 12 bits will be explained. The AD converter 19 transmits the upper 12 bits 19U and 191 of the 16-bit signal. Control signal 22 of multiplexer 22
C sets "0" and "1" for each sample, such that the output of the AD converter 19 is "0" level for sample 1, "1" level for sample 2, "0" for sample 3, etc. Add a repeating signal. Therefore, the latch 20 for sample 1 is the AD converter 19.
outputs 191 and 192 are added, and sample 2
In this case, the upper 4 bits of the data bus 23A of the RAM 23 and 191 of the AD converter 19 are added. The data written to the RAM 23 at this time will be explained using the memory map shown in FIG. In sample 1, the output of the AD converter 19 is latched as is in the latches 20U and 20. By the way, RAM23
Block A address 1 stores the upper 8 bits 19U of sample 1, and address 2 stores the lower 8 bits 191 and 192. Next, when sample 2 is stored in the latches 20U and 20, the RAM 23 uses the RAM address control circuit 24 to store the lower 8 bits 1 of the previously stored sample 1.
91 and 192 are output to the data bus 23A. Therefore, the data stored in the latch 20 is
By multiplexer 8, the upper 4 bits are the lower 4 bits (191) of sample 1, and the lower 4 bits are the lower 4 bits (191) of sample 2. The data in latch 20 is written again to address 2 of RAM 23, and the data in latch 20U is written to address 3. In this way, when the control signal 22C of the multiplexer 22 is "1", the RAM 23 outputs the lower 8 bits of the previously stored sample and writes it to the RAM 23 again, thereby generating one sample as shown in FIG. 12
Eight samples of data can be stored in block A using bits. The data obtained in this way
Since the number of data is the same as in the case of 16-bit quantization, the same processing and operation can be performed to generate the frame shown in FIG. 2b. The operation timing for the 16-bit and 12-bit quantization is shown in FIGS. 8 and 9. Figure 8 is a diagram showing the timing for 16-bit quantization, and Figure 9 is a diagram showing the timing for 16-bit quantization.
4 is a diagram showing the timing for bit quantization, and the symbols on the left side correspond to the symbols of each structure in FIG. 4, and indicate the signals of each structure. FIG.

In order to perform the processing of each component (data writing processing, error detection and correction code generation processing, serial data output processing) in a time-sharing manner, the buffer control signal 23 is used as shown in FIGS. 8 and 9.
C, 21Cu, 21C, 26C and clocks 25A, 27 for taking in data are constructed so as not to overlap in time. Further, the switch 31 for obtaining serial data output is connected to each terminal in FIG. 4 when each control signal 31A, 31B, 31C in FIGS. 8 and 9 is "1", and outputs the desired serial data. is obtained at terminal 32.

The difference between FIG. 8 and FIG. 9 is that the control signal 22C of the multiplexer 22 is "0" in FIG. 8, whereas in FIG. 9 it is a signal that repeats "0" and "1" for each sample. This is the point. This makes it possible to realize the same frame configuration even when 12-bit quantization is performed.

As explained above, even if there are two quantization bit numbers, 16-bit quantization and 12-bit quantization, the increase in circuit scale is small and the redundancy remains unchanged.
They can have the same frame configuration. here,
As an example of 12-bit quantization, the upper level of AD converter 19
Although 12 bits are assumed to be transmitted, it is clear that data obtained by instantaneously companding 16 bit quantized data to 12 bits can also be transmitted in the same frame configuration using the same method as described above.

A PCM digital signal recording and reproducing apparatus for recording digital signals generated by the method shown in FIG. 2 on a recording medium at the same recording wavelength and recording format will be described below.

FIG. 7 is a block diagram of a PCM digital recording/reproducing apparatus according to the present invention. In FIG. 7, circuits with the same symbols as in FIG. 1 are the same circuits, 200 is a digital dubbing input terminal, 220 and 23
0 is a waveform equalization circuit with different frequency characteristics from the waveform equalization circuit 12, 290 is a reference signal selection circuit, 270,
280 is a reference signal generator, 300 and 310 are a rotating cylinder rotation speed control circuit and a recording medium feed speed control circuit, respectively, 320 is a transmission rate control circuit, 330 is a control signal generation circuit, 34
0 is a recording/reproduction mode changeover switch, 350 is a control head, 360 is a control signal discrimination circuit, and 370 is a digital dubbing output terminal.

The operation shown in FIG. 7 will be explained below. The oscillation frequencies of the reference signal generators 17, 270, and 280 are the basic clocks of three types of systems with different sampling frequencies and numbers of quantization bits, and are clocks that have an integral multiple relationship with the transmission rate and sampling frequency. The transmission rate f _B1 when the sampling frequency _s is 44.1 KHz and the number of quantization bits is 16 bits is determined by the following equation since transmission is performed using the frame configuration shown in FIG. 2a.

f _B1 = sample frequency / number of samples in one frame × (
(number of bits in one frame) ...(2) Therefore, f _B1 is 1.176 _Mbps . The frequency of the reference signal generator 17 that generates the basic clock is set at the transmission rate so that it is an integral multiple of the sampling frequency.
f The frequency is 14.112 _MHZ which is 12 times _B1 . Similarly, the transmission rate f _B2 when the sampling frequency is 48 KHz and 16-bit quantization is 1.28 _Mbps , and the frequency of the reference signal generator 270 is 15.36 _MHZ when the sampling frequency is 32 KHz and 12-bit quantization, the transmission rate f _B3 is 0.64 _Mbps . The frequency of reference signal generator 280 is 7.68 _MHZ . The oscillation frequencies of these three reference signal generators 17, 270, 280 are selected by the reference signal selection circuit 290 and inputted to the clock generation circuit 18, so that the sample and hold circuits 2, 15 and the A/D converter 3, Various timing signals of the D/A converter 14, the recording system signal processing circuit 4, and the reproduction system signal processing circuit 13 are switched.

Control signals for selection of reference signal selection circuit 290 and waveform equalization circuit selection circuit 240 are generated from transmission rate control circuit 320. During recording, this transmission rate control circuit 320 can be controlled manually or
It is automatically detected and controlled from the input signal of the digital dubbing input terminal 200, and during playback, it can be controlled manually or
Automatic detection control from control signals. The control signal generation circuit 330 is a circuit that generates a signal for controlling the number of sample frequency quantization bits of the information to be recorded using three types of clocks from the reference signal selection circuit 290. A control signal is recorded in the control head 350 via the control head 350.
During reproduction, the control signal reproduced by the control head 350 is input to the control signal discrimination circuit 360 via the switch 340.
The sample frequency and number of quantization bits of the recorded information are determined and applied to the transmission rate control circuit 320, rotation speed control circuit 300, and feed rate control circuit 310.

The rotating drum rotation speed control circuit 300 changes the rotation speed of the rotating drum in proportion to the transmission rate of the PCM digital signal to be recorded. Generally, when recording a PCM digital signal on a recording medium, the maximum frequency that can be recorded is determined by the transmission characteristics determined by the recording medium and recording/reproducing head. Since this transmission characteristic depends on the recording wavelength during recording, if the relative speed between the recording medium and the recording/playback head is changed according to the transmission rate of the recording signal, efficiency can be achieved without wasting the use of the recording medium. Can record well. In the rotary head type recording and reproducing apparatus of this embodiment, the relative speed Vh between the recording medium and the recording and reproducing head is proportional to the rotational speed n of the rotary drum.

Vh=n×π×π ...(3) (here, φ is the diameter of the rotating drum) Therefore, the rotating drum rotation speed control circuit 300
In order to record efficiently, the sampling frequency is 44.1KHz, the quantization bit is 16 bits, and the transmission rate is _fB1.
= 48KHz, 16 based on the rotation speed of 30rps at 1.176 _MHZ
Bit, f _B2 = 1.28 _MHZ : 32.7rps, 32KHz, 12
When bit, f _B3 = 0.64 _MHZ , the rotation speed is set to 16.3 rps.

The recording medium feed speed control circuit 310 is for controlling the feed speed of the recording medium in proportion to the transmission rate of the PCM digital signal to be recorded. This is done because if the number of rotations of the rotary drum is changed depending on the transmission rate while the tape feed rate is constant, the track width and track pitch will change. In this example, the feed rate is 6 mm/S when the sampling frequency is 44.1 KHz, the quantization bit is 16 bits, f _B1 = 1.176 _MHZ , and the feed rate is 6.5 mm/S when the sampling frequency is 48 KHz, 16 bits, f _B2 = 1.28 _MHZ ,
3.3mm/S at 32KHz, 12 bits, f _B3 = 0.64 _MHZ
Set the feed speed to , track width on the recording medium,
Track pitch is kept constant. The rotation speed control circuit 300 and the feed speed control circuit 310 are controlled by determining and switching the transmission rate based on the clock frequency of the reference signal selection circuit 290 during recording, and during reproduction, the transmission rate is determined based on the signal from the control signal determination circuit 360. The number of rotations of the rotating drum and the feeding speed of the recording medium are changed.

As mentioned above, by changing the rotation speed of the rotating drum and the feeding speed of the recording medium in proportion to the transmission rate of the recording signal, the shortest wavelength on the recording medium is always constant, and as a result, the waveform equalization characteristics are also the same. Become. However, as the recording signal frequency changes in each system, the equalization characteristics shift on the frequency axis. Therefore, in FIG. 7, waveform equalization is performed using a waveform equalization circuit 12 for a sampling frequency of 44.1KHz, quantization bits of 16 bits, and a transmission rate of f _B1 =1.176 _MHZ .
48KHz 16-bit f _B2 = 1.28 _MHZ waveform equalization circuit 22
It consists of a waveform equalization circuit 230 for 0 and 32KHz, 12 bit f _B3 = 0.64 _MHZ , and a waveform equalization circuit selection circuit 24.
Select the equalization circuit output that matches the transmission rate with 0,
It is added to the signal processing circuit 13.

〔Effect of the invention〕

According to the present invention, even if there are PCM digital signal sources with different numbers of quantization bits, such as 16 bits and 12 bits, the same frame configuration can be achieved without changing the redundancy. Therefore, PCM with different number of quantization bits and sampling frequency
When recording a digital signal, regardless of its value, the drum rotation speed and recording medium feeding speed can be changed to keep the recording wavelength constant, and the recording format can also be kept constant, so that when the transmission rate becomes low, It is possible to avoid a decrease in the recording density of , and the situation where recording and reproduction become impossible when the transmission rate becomes high, and the recording time can be lengthened when the transmission rate is low.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional PCM digital signal recording/reproducing device, FIGS. 2 and 3 are diagrams showing an embodiment of the frame structure according to the present invention, and FIG. 4 is a signal realizing the frame structure shown in FIG. 2. processing circuit,
5 and 6 are diagrams showing a memory map of the RAM 23 to explain the operation of FIG. 4, and FIG. FIG. 8 is a diagram showing the timing of operations for 16-bit quantization, and FIG. 9 is a diagram showing the timing of operations for 12-bit quantization. 2,15...Sample/hold circuit, 3,1
9... A/D converter, 4, 13... Signal processing circuit, 8... Rotating drum, 7... Recording and reproducing head,
9... Recording medium, 12, 220, 230... Waveform equalization circuit, 14... D/A converter, 300... Rotation speed control circuit, 310... Feed rate control circuit.

Claims (1)

[Claims] 1. An A/D converter that converts an analog signal into a digital signal, a first signal processing circuit that performs predetermined signal processing on the output of the A/D converter, and an output of the first signal processing circuit. a rotary drum to which a recording/reproducing head is fixed for recording and reproducing data on a recording medium, a second signal processing circuit that performs predetermined processing on the digital signal reproduced during reproduction, and converting the output of the second signal processing circuit into an analog signal. In a rotary head type PCM digital signal recording and reproducing device comprising a D/A converter that converts the signal into a digital signal, the first signal processing circuit maintains redundancy even if the number of quantized bits of one sample to be transmitted differs from n _s1 and n _s2 . of one frame without changing the
Let the number of bits of PCM data be a common multiple of n _s1 and n _s2 ,
The same error detection and correction code is added, the frame structure is the same even if the number of quantization bits and sampling frequency are different, and the reference signal that serves as the operating clock of the above circuit is changed in proportion to the transmission rate of the digital signal to be recorded. A reference signal generator and a reference signal selection circuit for the purpose of the present invention, a rotation speed control circuit for changing the rotation speed of the rotating drum, and a transmission rate control circuit for controlling the reference signal selection circuit, regardless of the transmission rate. 1. A rotary head type digital signal recording and reproducing device, characterized in that the recording wavelength on a recording medium is kept constant. 2. The digital signal recording and reproducing device according to claim 1, further comprising a feed speed control circuit for changing the feed speed of the recording medium in proportion to the transmission rate of the digital signal to be recorded, 1. A rotary head type digital signal recording and reproducing apparatus, characterized in that the tape format on the recording medium is constant regardless of the tape format. 3. In the digital signal recording and reproducing apparatus according to claim 1 or 2, a waveform equalization circuit whose frequency characteristics change depending on the transmission rate of the digital signal to be recorded is provided regardless of the recording and reproducing system. A digital signal recording and reproducing device characterized by: