JPH0572798B2 - - Google Patents
Info
- Publication number
- JPH0572798B2 JPH0572798B2 JP58108209A JP10820983A JPH0572798B2 JP H0572798 B2 JPH0572798 B2 JP H0572798B2 JP 58108209 A JP58108209 A JP 58108209A JP 10820983 A JP10820983 A JP 10820983A JP H0572798 B2 JPH0572798 B2 JP H0572798B2
- Authority
- JP
- Japan
- Prior art keywords
- value
- circuit
- supplied
- input terminal
- reference value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/68—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、映像信号をデジタル化して処理を行
うようにしたテレビ受像機に使用されるACC回
路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an ACC circuit used in a television receiver that digitizes and processes video signals.
背景技術とその問題点
映像信号をデジタル化して処理を行うようにし
たテレビ受像機が提案されている。そのような場
合にいわゆるACCを行おうとすると、クロマ信
号のビツト数が少ないために正確な制御を行うこ
とができない。BACKGROUND ART AND PROBLEMS There has been proposed a television receiver that processes video signals by digitizing them. If so-called ACC is attempted in such a case, accurate control cannot be performed because the number of bits of the chroma signal is small.
すなわち制御の誤差を少なくするためには多く
のビツト数が必要となり、それができない場合に
はLSBが常に変化することによつて色飽和度が
変化し、画面上でちらつきとなつて見えてしま
う。 In other words, in order to reduce control errors, a large number of bits is required, and if this is not possible, the color saturation changes as the LSB changes constantly, causing flickering to appear on the screen. .
発明の目的
本発明はこのような点にかんがみ、ビツト数が
少なくても安定な動作が行われるようにするもの
である。OBJECTS OF THE INVENTION In view of these points, the present invention provides stable operation even when the number of bits is small.
発明の概要
本発明は、デジタル化されたクロマ信号のバー
スト部分の最大値と最小値を検出し、この値を積
分し、この積分値で所定の参照値を除算し、この
商を上記クロマ信号に乗算するようにしたACC
回路であつて、これによればビツト数が少なくて
も安定な動作が行われる。SUMMARY OF THE INVENTION The present invention detects the maximum and minimum values of a burst portion of a digitized chroma signal, integrates this value, divides a predetermined reference value by this integral value, and divides this quotient into the chroma signal. ACC to be multiplied by
This circuit allows stable operation even with a small number of bits.
実施例
図において、１は例えば８ビツトでデジタル化
されたクロマ信号の供給される入力端子であつ
て、この入力端子１からの信号がバースト期間の
最大及び最小のピーク値を検出する検出回路２に
供給され、この検出された値が積分回路３に供給
される。この積分値が除算回路４に供給され、こ
の値にて入力端子５に供給される参照値が除算さ
れる。この商が乗算回路６に供給されて入力端子
１からのクロマ信号に乗算され、出力端子７に取
り出される。Embodiment In the figure, reference numeral 1 denotes an input terminal to which a chroma signal digitized with, for example, 8 bits is supplied, and a detection circuit 2 detects the maximum and minimum peak values of the signal from this input terminal 1 during the burst period. The detected value is supplied to the integrating circuit 3. This integral value is supplied to the division circuit 4, and the reference value supplied to the input terminal 5 is divided by this value. This quotient is supplied to the multiplication circuit 6, multiplied by the chroma signal from the input terminal 1, and taken out at the output terminal 7.
この回路において、検出回路２からのバースト
期間の最大値と最小値を積分することにより、ク
ロマ信号のレベルが検出され、その値で参照値を
除算し、この値を乗算回路６の乗数とすることに
より、出力信号のレベルが参照値に等しくされ
る。 In this circuit, the level of the chroma signal is detected by integrating the maximum and minimum values of the burst period from the detection circuit 2, the reference value is divided by that value, and this value is used as the multiplier of the multiplication circuit 6. This makes the level of the output signal equal to the reference value.
こうしてACCが行われるわけであるが、この
回路によればフイードフオワード式にACCが行
われるので、乗数は近似値として一意的に決定さ
れ、ビツト数がある程度少なくても安定した動作
となる。 This is how ACC is performed. Since this circuit performs ACC in a feed-forward manner, the multiplier is uniquely determined as an approximate value, and stable operation is achieved even if the number of bits is small to some extent. .
発明の効果
本発明によれば、ビツト数が少なくても安定な
動作を行うことができるようになつた。Effects of the Invention According to the present invention, stable operation can be performed even with a small number of bits.
図は本発明の一例の構成図である。
１は入力端子、２はバーストピーク値検出回
路、３は積分回路、４は除算回路、５は参照値の
入力端子、６は乗算回路、７は出力端子である。
The figure is a configuration diagram of an example of the present invention. 1 is an input terminal, 2 is a burst peak value detection circuit, 3 is an integration circuit, 4 is a division circuit, 5 is a reference value input terminal, 6 is a multiplication circuit, and 7 is an output terminal.
Claims (1)
及び最小のピーク値を検出する検出回路２に供給
され、この検出された値が積分回路３に供給さ
れ、この積分値が除算回路４に供給され、この値
にて入力端子５に供給される参照値が除算され、
この商が乗算回路６に供給されて入力端子１から
のクロマ信号に乗算され、出力端子７に取出され
るようにしたACC回路において、検出回路２か
らのバースト期間の最大値と最小値が積分するこ
とにより、クロマ信号のレベルが検出され、その
値で参照値を除算し、この値を乗算回路６の乗数
とすることにより、出力信号のレベルが参照値に
等しくされるようにしたACC回路。1 The signal from input terminal 1 is supplied to a detection circuit 2 that detects the maximum and minimum peak values of the burst period, this detected value is supplied to an integration circuit 3, and this integrated value is supplied to a division circuit 4. , the reference value supplied to the input terminal 5 is divided by this value,
This quotient is supplied to the multiplication circuit 6, multiplied by the chroma signal from the input terminal 1, and taken out at the output terminal 7.In the ACC circuit, the maximum and minimum values of the burst period from the detection circuit 2 are integrated. By doing so, the level of the chroma signal is detected, the reference value is divided by that value, and this value is used as the multiplier of the multiplier circuit 6, so that the level of the output signal is made equal to the reference value. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58108209A JPS60188A (en) | 1983-06-16 | 1983-06-16 | Acc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58108209A JPS60188A (en) | 1983-06-16 | 1983-06-16 | Acc circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60188A JPS60188A (en) | 1985-01-05 |
| JPH0572798B2 true JPH0572798B2 (en) | 1993-10-13 |
Family
ID=14478780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58108209A Granted JPS60188A (en) | 1983-06-16 | 1983-06-16 | Acc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60188A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62156474U (en) * | 1986-03-27 | 1987-10-05 | ||
| JPH01277698A (en) * | 1988-04-30 | 1989-11-08 | Nippon Ferrofluidics Kk | Combined vacuum pump |
| JP3057255B2 (en) * | 1989-08-15 | 2000-06-26 | ソニー株式会社 | Image processing apparatus and image processing method |
| JPH04336979A (en) * | 1991-05-15 | 1992-11-25 | Matsushita Electric Works Ltd | Power tool |
| JPH05104454A (en) * | 1991-10-15 | 1993-04-27 | Matsushita Electric Works Ltd | Power tool |
-
1983
- 1983-06-16 JP JP58108209A patent/JPS60188A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60188A (en) | 1985-01-05 |
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