JPH0573014A - Display signal converter - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the bit width per dot when converting analog display data to digital signals. [Arrangement] The output 6 of the pallet 5 is converted into analog data 8, 9, 10 by a D / A converter 7 and input to a display signal converter 23. Then, it is converted into a digital signal 13 by the A / D converter 12. The comparator 25 compares this data with the internal register group of the second palette 24. Further, since the same value as that of the internal register group of the palette 5 is set in advance in the second palette 24 via the I / O data bus, as a result of comparison, it is converted into the data 26 for selecting the matching register. Stored in memory. The bit width of the display data stored in the memory can be reduced by converting the data indicating the selected register after the analog data is input and digitized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display signal conversion device, and more particularly to a display signal conversion device for converting input display information when it is digitized and stored in a memory into an optimum bit width.

[0002]

2. Description of the Related Art Conventionally, in a personal computer having an analog display output (hereinafter referred to as a personal computer), a second computer which operates at a different timing from the original display device.
As a method of displaying on the display device, the analog display data is analog-to-digital converted (hereinafter referred to as A / D conversion), digitized, and stored in the frame memory. Then, a method is known in which data is read out from the frame memory at a display timing of the second display device and displayed. This conventional technique will be described with reference to FIGS.

In FIG. 3, a portion surrounded by 11 is a personal computer, 1 is a CPU, 2 is an I / O data bus, 3 is a video memory, 4 is a video memory data bus, and 5 is a display data converter (hereinafter, referred to as a display data converter). A pallet), 6 is an output of the pallet, and 7 is a digital / analog converter (hereinafter, D /
It is called an A converter. ), 8, 9 and 10 are "red" respectively
It is an analog display data output that outputs a component, a “green” component, and a “blue” component. Further, a portion surrounded by 23 is a display signal converter, 12 is an A / D converter, 13 is a display data bus synchronized with the display timing of a personal computer, 14 is a timing converter, 15 is a frame memory, 16 is a frame. Memory data bus, 17 is a display data bus converted to the timing of the second display device, 18 is a D / A converter,
Reference numerals 19, 20, and 21 denote analog display data outputs to the second display device, which are a “red” component, a “green” component, and a “blue” component, respectively.
The component is being output. 22 is a second display device.

FIG. 4 shows the details of the pallet 5 in FIG. In FIG. 4, 101 is a 12-bit register, 102 is a selector, and 103 is an output of each register.

In the above configuration, the video memory 3 of the personal computer 11 stores 4-bit data for each dot of display data. Then, this display data is input to the palette 5 via the video memory data bus 4. Further, the palette 5 has 16 12-bit registers 101, and an arbitrary value can be set in this register from the CPU 1 via the I / O data bus 2. Then, the 4-bit display data is sent to the selector 102.
Decode with, select one of 16 registers,
By outputting the data of the register, the 4-bit display data is converted into the 12-bit display data.
As a result, 16 colors out of 2 4 (4 bits) = 16 colors before being input to the palette 5 to 2 12 (12 bits) = 4096 colors can be handled as colors that can be expressed. Like Then, the display data converted into 12 bits is A / D converted by the A / D converter 7 and output from the personal computer 11 as analog display data 8, 9, 10. In the display signal converter 23, the analog display data 8, 9 and 10 are input, and the A / D converter 12 converts the analog display data into digital 12-bit data again. This data is converted into the input timing of the frame memory 15 by the timing converter 14 and stored in the frame memory 15. Then, this data is read from the frame memory 15 and converted by the timing converter 14 into the display timing of the second display device. This data is the D / A converter 18
D / A converted in and output to the second display device. As described above, the analog display data output from the personal computer 11 is generally taken into the frame memory as digital display data.

As a conventional device using such a system, there is a projection liquid crystal unit, PC-PD101 manufactured by NEC Corporation.

[0007]

In the above prior art, the bit width of the display data of the video memory on the personal computer side is 1
A / D, while storing 4 bits per dot
The converted frame memory has 12 bits per dot. Since this is stored in the frame memory as it is, an extra memory is required. In other words, the video memory of the personal computer stores 4 bits of data indicating which register is selected from the 16 palette registers, whereas the frame memory stored after A / D conversion stores A / D The converted display data itself, that is, 12 bits is stored.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and reduce the number of bits stored in the frame memory to the number of bits for selecting a register in the palette, not the number of bits representing the display data itself. However, it is another object of the present invention to provide a display signal conversion device capable of reducing the memory capacity.

[0009]

The above object is to perform analog / digital conversion of analog data of a display output device for digital / analog converting data of a register selected from a first register group having an arbitrary bit width. In the display signal conversion device having the first means for inputting the same, the display information is written from the inside or the outside to the first register group, and at the same time, the same display information is written to the second register group of the display signal conversion device. As a result of comparison between the second means and the third means for comparing the display information digitized and input with the display information of the second register group, the digitized display information is the same in the second register group. This is achieved by providing a fourth means for converting the information into a register and writing the information in the memory.

[0010]

It is possible to know which register data of the palette the display information is by incorporating the information of the pallet of the personal computer into the display signal converter and comparing it with the A / D converted display information. It becomes possible to convert the digitized signal into the information input to the palette of the personal computer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a display signal conversion device and a personal computer connected thereto according to an embodiment of the present invention. still,
The same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The display signal converter 23 according to this embodiment includes a second palette 24, a comparator 25, and a 4-bit data bus 2.
6, a 4-bit data bus 27 after timing conversion,
An I / O data bus 29 has been added.

FIG. 2 is an enlarged configuration diagram of a portion surrounded by reference numeral 28 in FIG. The same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 2, 201 is a 12-bit register, 202 is a 12-bit comparator corresponding to each register, 203 is a selector, 204 is an output of each register, 2
Reference numeral 05 is a signal indicating the comparison result of each comparator, and 206 is an encoder.

The operation of the display signal conversion apparatus 23 according to this embodiment having such a configuration will be described. The operation of the personal computer 11 is the same as that of the conventional example. 1 for the second pallet 24
There are six registers 201, and these registers 201
When the CPU 1 writes data to the pallet 5,
At the same time, the same data is written via the I / O data bus 29. Therefore, register 1 of palette 5
01 and the register 201 of the second palette 24 always store the matched data. Analog display data 8 input from the personal computer 11 to the display signal converter 23,
9 and 10 are converted into 12-bit digital display data 13 by the A / D converter 12. Then, the converted display data 13 is compared with all the data bits of the 16 12-bit registers 201 by the comparator 202. Since the input display data 13 is the same as the data in the palette 5, there is a register having the same data content as at least one of the 16 registers 201 to be compared. Then, this result is output to the signal line 205 indicating the comparison result. There are 16 signal lines 205 in total, and this signal is encoded into 4-bit data by the encoder 206 and output to the 4-bit data bus 26. The 4-bit data is converted by the timing converter 14 into the operation timing of the frame memory and stored in the frame memory. Then, the data is read from the frame memory, converted by the timing converter 14 into the display timing of the second display device, and input to the palette 24 again. In the palette 24, this data is used as an input signal of the selector 102, and one register is selected from the 16 registers 101 to convert 4-bit data into 12-bit data. Then, the 12-bit data is D / A converted, and the second
Is being output to the display device. By the above operation, A /
The bit width of the display data after D conversion is 1 per dot.
It is possible to reduce from 2 bits to 4 bits.

In this embodiment, the second display device is an analog display, but the present invention is not limited to this, and a display which receives digital data may be used. The bit width of the data stored in the palette is
The bit width is not limited to 12 bits and can be set to any bit width. The point is that the data stored in the frame memory only needs to have a bit width enough to select the palette register.

[0015]

According to the present invention, the digitized analog information from the personal computer is compared with the contents of the pallet and converted into the information used in the personal computer to store one dot in the memory. It has the effect of minimizing the amount of information per hit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a display signal conversion device and a personal computer according to an embodiment of the present invention.

FIG. 2 is an enlarged configuration diagram of a portion denoted by reference numeral 28 shown in FIG.

FIG. 3 is a configuration diagram of a conventional display signal conversion device and a personal computer.

FIG. 4 is a configuration diagram of a pallet of the personal computer shown in FIG.

[Explanation of symbols]

1 ... CPU, 2 ... I / O data bus, 3 ... Video memory, 4 ... Video memory data bus, 5 ... Display data conversion device (palette), 6 ... Display data conversion device (palette) output, 7 ... Digital / Analog converter, 8 ... Analog display data output (red component), 9 ... Analog display data output (green component), 10 ... Analog display data output (blue component), 11 ... Personal computer, 12 ... Analog / digital converter, 13 ... Display data bus synchronized with display timing of personal computer, 14 ... Timing conversion device, 15 ... Frame memory, 16 ... Frame memory data bus, 17 ... Display data bus converted to timing of second display device, 18 ... Digital / analog converter,
19 ... Second analog display data output (red component), 20
... second analog display data output (green component), 21 ... analog display data output (blue component), 22 ... second display device, 23 ... display signal conversion device, 24 ... second palette,
25 ... Comparator, 26 ... 4-bit data bus, 27 ... 4-bit data bus after timing conversion, 28 ... Second palette and comparator, 29 ... I / O data bus, 101 ... 12
Bit register, 102 ... Selector, 103 ... Output of each palette register, 201 ... 12-bit register, 2
02 ... Comparator corresponding to each register, 203 ... Selector, 204 ... Output of each register of the second palette, 20
5 ... A signal representing the comparison result.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Hayashi 7-1, 1-1 Higashi Narashino, Narashino, Chiba Prefecture Hitachi Systems Office System Design and Development Center (72) Inventor Akihiro Shibata 7-1, Higashi Narashino, Narashino, Chiba No. 1 Hitachi Ltd. Office system design and development center (72) Inventor Akihiro Kato 7-1-1 Higashi Narashino, Narashino city, Chiba Hitachi Ltd. Office system design and development center

Claims (1)

[Claims] 1. A first means for inputting analog / digital converted analog data of a display output device which digital / analog converts data of a register selected from a first register group having an arbitrary bit width. In the display signal conversion device having: a second means for writing the same display information to the second register group of the display signal conversion device at the same time as writing the display information to the first register group from the inside or the outside, and digitizing the same. And a third means for comparing the display information input as described above with the display information of the second register group, and as a result of the comparison, the digitized display information is converted into information indicating the matched register of the second register group. A display signal conversion device comprising a fourth means for writing in a memory.