JPH0573058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a fuse for cutting a redundant part, and more particularly to a structure for a fuse arrangement part that prevents current leakage from a fuse blowing part.

Semiconductor integrated circuit devices (ICs) are equipped with redundant circuits for the purpose of changing functions and resolving defects, and these redundant circuits can be easily disconnected by blowing out by flowing a large current. A fuse made of a conductive film is used.

Further, the fuse is often used in analog ICs, such as when adjusting a feedback resistor provided to adjust the gain of an operational amplifier or the like.

In such fuses, current leakage that occurs at the blown portion of the fuse after blowing has a large adverse effect on the performance of these ICs, so there is a need for a fuse structure that improves the insulation of the fused portion.

[Conventional technology]

The most commonly used conductive film fuse is a polycrystalline silicon fuse using a polycrystalline silicon film as a blowing material.

The fuse is usually disposed on the field insulation film.

FIG. 4 is a schematic plan view (a) showing a conventional polycrystalline silicon fuse, a schematic cross-sectional view (b) taken along the line A-A, and a cross-sectional view (c) taken along the line B-B.

In the figure, 1 is, for example, an n-type silicon substrate;
2 is a field oxide film, 3 is a polycrystalline silicon fuse, 3m is a part to be fused, 3a and 3b are wiring connection parts, 4 is an interlayer insulating film, 5 is a wiring contact window,
6a and 6b are aluminum wirings, 7 is a cover insulating film, and 8 is a hole for fusing.

[Problem that the invention seeks to solve]

When forming the fuse, a pattern of polycrystalline silicon fuse 3 is formed on field oxide film 2, and impurities (for example, phosphorus, arsenic, etc.) are ion-implanted into the fuse pattern at a high concentration to form the fuse. After imparting high conductivity to the pattern, an interlayer insulating film 4 is formed thereon, a wiring contact window 5 is formed in the interlayer insulating film 4, and polycrystalline silicon is formed on the interlayer insulating film 4 in the contact window 5.・Aluminum wiring 6a in contact with fuse 3 pattern
and 6b, and a cover insulating film 7 is formed thereon, and then a control etching means is used to pierce the cover insulating film 7 and the interlayer insulating film 4 to expose the part 3m of the fuse 3 to be blown. A hole 8 is formed.

When the fuse is formed by such a method, when impurity ions are implanted at a high concentration into the pattern of the polycrystalline silicon fuse 3, the impurity is also implanted at a high concentration into the field oxide film 2 near the fuse pattern, causing etching.・The etching rate is improved, and there is no selectivity between the cover insulating film 7, the interlayer insulating film 4, and the field oxide film 2 in the control etching during opening formation, and the etching rate is improved within the substrate plane. Depending on the distribution, etc., the bottom surface of the fusing hole 8 may dig deeply into the field oxide film 2, as shown by the dotted line 9, and in extreme cases, the surface of the silicon substrate 1 may be exposed.

In such a case, as shown in the schematic side cross-sectional view after fusing shown using the same reference numerals in FIG. Silicon substrate 1
A current path I _L is formed between the fused ends 3m _A and 3 m _B of the fuse 3 via the fuse 3, resulting in a problem that the fuse is incompletely cut.

Although not shown in the figure, even if the substrate surface is not exposed, the field oxide film near the fuse is very thin, so cracks may occur in the field oxide film due to thermal shock during fusing, or cracks may occur in the field oxide film. There has been a problem in that current leaks between the fused ends of the fuse through the substrate through pinholes and the like, impairing the performance of the IC on which the fuse is disposed.

[Means for solving problems]

The above problem has a fuse formed on a semiconductor substrate of one conductivity type via an insulating film, and an electrically floating well region of the opposite conductivity type is disposed in a region of the semiconductor substrate below the fuse. and a selectively electrically floating one conductivity type impurity region in a lower region of at least one end of the fuse in the well region, the one conductivity type impurity region and the opposite conductivity type well region forming a selectively electrically floating impurity region. The present invention is solved by a semiconductor device characterized in that a pn junction is provided so as to be formed across the fuse in the lower region.

[Effect]

That is, in the semiconductor device of the present invention, the fuse is formed on an electrically floating well of a conductivity type opposite to that of the substrate via an insulating film, and one end or both ends of the fuse in the well region of the opposite conductivity type are formed. By providing an electrically floating independent impurity region of one conductivity type in the lower region of the well, a potential barrier is formed at the junction between the well and the one conductivity type impurity region, and a potential barrier is formed at the junction between the well and the substrate. Due to the potential barrier between the two melting ends of the fuse, when both melting ends of the fuse contact the semiconductor surface, a current flows between the two melting ends of the fuse through the well, and both melting ends or one melting end of the fuse This prevents current from flowing between the fused end of the fuse and the substrate when it contacts the semiconductor surface.

In this way, due to variations in manufacturing conditions when forming an opening for blowing a fuse, the semiconductor surface may be exposed at the bottom of the opening, or the thickness of the insulating film at the bottom of the opening may become extremely thin. However, since there is no current leak between the fused end of the fuse and the semiconductor substrate or between both fused ends of the fuse, performance deterioration of the semiconductor device is prevented.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 1 is a schematic plan view a showing an embodiment of the fuse structure according to the present invention, and its cross-sectional view taken along the line A-A, b. FIG. The figure is a schematic side sectional view showing another embodiment of the fuse structure.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIG. 1 showing an embodiment of the fuse portion structure according to the present invention, 1 is, for example, a carrier concentration of 10 ¹⁵
N-type silicon substrate of about cm ^-3 , thickness 2 is 6000 ~
Field oxide film of about 8000 Å, 3 is polycrystalline silicon fuse, 3m is the part to be fused, 3a and 3b
4 is a wiring connection part, 4 is an interlayer insulating film made of phosphosilicate glass (PSG), etc., 5 is a wiring contact window, 6a
and 6b are aluminum wiring, 7 is a cover insulating film made of PSG or the like, 8 is a hole for fusing, 10 is a p-well with a carrier concentration of, for example, 10 ¹⁶ to 10 ¹⁷ cm ^-3 and a depth of about 3 to 4 μm, and 11 is, for example, Carrier density 10 ¹⁷ cm
^-3 indicates an n-type impurity region with a depth of about 3000 Å.

As shown in the figure, in the fuse portion structure of the present invention, a well of a conductivity type opposite to that of the electrically floating substrate that includes the lower region of the fuse 3 is formed on the surface of, for example, an n-type silicon substrate below the fuse 3. A p-well 10 is provided, and the p-well 1
An impurity region of the conductivity type opposite to that of the well 10, that is, an n-type impurity region 11, is selectively electrically floating at one end of the blown portion of the fuse 3 at 0, for example, the lower region on the side closer to the wiring connection portion 3a.
is formed. Note that the end face of the electrically floating n-type impurity region 11 on the other end side of the fuse is located near the center of the fuse blown portion 3m. Further, the width of the n-type impurity region 11 is formed to be at least three times the width of the fuse blown portion 3m.

Note that the above structure is an example in which a + potential is applied to one end of the fuse 3 on the side connected to the internal circuit.

In the structure of the above embodiment, etching progresses excessively when forming the fusing hole 8, and the state after the fuse 3 is blown is shown in the second example when, for example, the semiconductor surface is exposed at the bottom of the fusing hole 8. It is a diagram.

In such a case, as shown in the figure, in the structure of the above embodiment, the polycrystalline silicon layer 103b hanging down from the ground side fused end _3mB of the fuse due to the blowout is placed on the p-type well 10. Also, a polycrystalline silicon layer 103 hanging down from the molten end 3 m _A on the side connected to the internal circuit to which + potential is applied.
a is in contact with n-type impurity region 11 . Therefore, the molten end _3mA is connected to the internal circuit to which a + potential is applied via the semiconductor with which the molten end comes into contact.
Leakage current flowing from the ground side molten end _3mB to the substrate 1 is blocked by a potential barrier formed by a reverse bias applied to the junction between the n-type impurity region and the p-well.

Note that in the structure in which only an electrically floating n-type impurity region is formed in the p-well,
At the fused end of the fuse connected to the internal circuit -
When a potential is applied, there is an electrically floating n in the lower region of the ground fused end of the fuse
It is sufficient to provide a type impurity region. That is, the arrangement of the n-type impurity region must be considered so that a reverse bias is applied to the junction between the electrically floating n-type impurity region and the p-well region.

FIG. 3 shows the fuse 3 in the well region 10.
This is an example in which separate electrically floating n-type impurity regions 11a and 11b are provided in the lower regions of both melting ends _3mA and _3mB , respectively.

In this structure, + and -
Regardless of which potential is applied, leakage current is blocked by a potential barrier at either junction between n-type impurity region 11a or 11b and p-well 10 to which reverse bias is applied.

In the structure shown in the above embodiment, the substrate, the well, and the impurity region provided in the well may all be formed of the opposite conductivity type to that of the above embodiment.

Further, the fuse material is not limited to the above polycrystalline silicon.

In the commonly used CMOS structure semiconductor IC, the well below the fuse is formed at the same time as the well where the transistor is formed, and the impurity region within the well is formed at the same time as the channel stopper on the substrate side. By using the above fuse arrangement structure, the manufacturing process is not complicated.

〔Effect of the invention〕

As described above, according to the present invention, current leakage between the two fused ends of the fuse and between the fused end of the fuse and the semiconductor substrate is prevented. Therefore, the present invention is effective in improving the manufacturing yield and reliability of semiconductor integrated circuit devices having fuses for cutting redundant parts.

[Brief explanation of drawings]

Fig. 1 is a schematic plan view a showing an embodiment of a fuse structure according to the present invention, and its sectional view taken along the line A-A, b, and Fig. 2 is a schematic side sectional view showing the state of the same embodiment after blowing. , FIG. 3 is a schematic side sectional view showing another embodiment of the fuse structure according to the present invention, and FIG. 4 is a schematic plan view a and its A showing a conventional fuse.
-A schematic cross-sectional view b, B-B arrow cross-sectional view c, and FIG. 5 are schematic side cross-sectional views showing the state of a conventional fuse after it is blown. In the figure, 1 is an n-type silicon substrate, 2 is a field oxide film, 3 is a polycrystalline silicon fuse,
3m is the part to be fused, 3a and 3b are the wiring connection parts, 4
5 is an interlayer insulating film, 5 is a wiring contact window, 6a and 6b are aluminum wirings, 7 is a cover insulating film, 8
10 indicates a fusing hole, 10 indicates a p-well, and 11 indicates an n-type impurity region.

Claims (1)

[Claims] 1. A fuse is formed on a semiconductor substrate of one conductivity type via an insulating film, and an electrically floating well region of the opposite conductivity type is disposed in a region of the semiconductor substrate corresponding to the lower part of the fuse, and A selectively electrically floating impurity region of one conductivity type is formed in a lower region of at least one end of the fuse in the well region, and a pn junction between the impurity region of one conductivity type and the well region of the opposite conductivity type is connected to the well region. A semiconductor device, characterized in that it is provided so as to be formed across the fuse in a lower region.