JPH0573079B2 - - Google Patents

Info

Publication number
JPH0573079B2
JPH0573079B2 JP60192663A JP19266385A JPH0573079B2 JP H0573079 B2 JPH0573079 B2 JP H0573079B2 JP 60192663 A JP60192663 A JP 60192663A JP 19266385 A JP19266385 A JP 19266385A JP H0573079 B2 JPH0573079 B2 JP H0573079B2
Authority
JP
Japan
Prior art keywords
polyimide
semiconductor chip
multilayer wiring
bonding pad
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60192663A
Other languages
Japanese (ja)
Other versions
JPS6253000A (en
Inventor
Hiroyuki Hamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60192663A priority Critical patent/JPS6253000A/en
Priority to FR868612072A priority patent/FR2586885B1/en
Publication of JPS6253000A publication Critical patent/JPS6253000A/en
Publication of JPH0573079B2 publication Critical patent/JPH0573079B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は大形コンピユータ等の電子機器に使用
される多層配線基板に関し、特に樹脂系の多層配
線基板上での半導体の実装構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multilayer wiring board used in electronic devices such as large-sized computers, and more particularly to a semiconductor mounting structure on a resin-based multilayer wiring board.

従来の技術 従来、この種の多層配線基板は、これを使用す
る大形コンピユータなどの電子機器の高性能化、
高速化に伴い、配線の高密度化が要求され、近年
高い絶縁性と微細な加工の容易さを有し、かつ比
誘電率の低いポリイミド系樹脂を使用した多層配
線基板が開発された。しかしながら、このポリイ
ミド系樹脂は硬度および抗張力が不十分のため、
表面のボンデイングパツド上に半導体チツプのリ
ードまたは接続ワイヤを熱圧着してボンデイング
する際に、この熱圧着時の圧力によつてポリイミ
ド絶縁層の表面にへこみが生じて正常なボンデイ
ングができないばかりでなく、更に下層の配線層
にも影響を与え、配線不良の原因にもなるという
欠点があつた。この対策として第２図に示すよう
にボンデイングパツド１８と配線層１５との間に
Cu、Niなどのメタル層１６を介在させる構造が
考えられた。（例えば特願昭58−249488号、特開
昭60−140897号公報） しかしながら、上述のメタル層を設けること
は、多層配線基板を形成する層数が増加して、基
板金体にかかるストレスがふえるという欠点があ
り、またボンデイングパツドと配線層との間にメ
タル層があるため配線層とボンデイングパツドと
を結ぶ配線ルートが制限されるという欠点があつ
た。Conventional technology Conventionally, this type of multilayer wiring board has been used to improve the performance of electronic equipment such as large computers,
As speed increases, higher wiring densities are required, and in recent years, multilayer wiring boards using polyimide resins that have high insulation properties, ease of fine processing, and low dielectric constants have been developed. However, this polyimide resin has insufficient hardness and tensile strength,
When bonding semiconductor chip leads or connecting wires by thermocompression bonding onto the bonding pad on the surface, the pressure from the thermocompression bonding may cause dents in the surface of the polyimide insulating layer, preventing normal bonding. Moreover, it has the disadvantage that it also affects the underlying wiring layer, causing wiring defects. As a countermeasure to this problem, as shown in FIG.
A structure in which a metal layer 16 such as Cu or Ni is interposed has been considered. (For example, Japanese Patent Application No. 58-249488, Japanese Patent Application Laid-open No. 60-140897) However, providing the above-mentioned metal layer increases the number of layers forming a multilayer wiring board, and reduces stress on the board metal body. Moreover, since there is a metal layer between the bonding pad and the wiring layer, the wiring route connecting the wiring layer and the bonding pad is restricted.

また、ポリイミド系樹脂は無機絶縁と比較して
熱伝導性が悪い。例えばアルミナの熱伝導率が
17W／ｍＫに対してポリイミド系樹脂では
0.2W／ｍＫである。そのため、ポリイミド系樹
脂を絶縁層とした多層配線基板の熱伝導率も悪く
なるという欠点がある。 Furthermore, polyimide resin has poor thermal conductivity compared to inorganic insulation. For example, the thermal conductivity of alumina is
17W/mK compared to polyimide resin
It is 0.2W/mK. Therefore, there is a drawback that the thermal conductivity of a multilayer wiring board having an insulating layer made of polyimide resin is also poor.

発明が解決しようとする問題点 本発明の目的は、上記の欠点、すなわちポリイ
ミド層が変形しやすいとか、これを防ぐためにメ
タル層を用いると、層数が増え、ストレスが生
じ、また配線ルートが制限を受けるという問題点
を解決し、さらに基板の熱伝導性が悪いために実
装した半導体部品に発生する熱が放散しにくいと
いう問題点をも解決した半導体の実装構造を提供
することにある。Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned drawbacks, namely, that the polyimide layer is easily deformed, and if a metal layer is used to prevent this, the number of layers will increase, stress will occur, and wiring routes will be It is an object of the present invention to provide a semiconductor mounting structure that solves the problem of being subject to limitations and also solves the problem that heat generated in mounted semiconductor components is difficult to dissipate due to poor thermal conductivity of the board.

問題点を解決するための手段 本発明は上述の問題点を解決するめに、ポリイ
ミド系樹脂と薄膜選択めつき法による配線パター
ンとによつて多層化し、最上面の少なくとも一層
を硬質の無機化合物の微粉末を混入したポリイミ
ドによつて形成した多層配線基板と、この多層配
線基板の表面上に形成されるボンデイングパツド
と、このボンデイングパツドに熱圧着により接続
されるリードと、このリードを介して前記多層配
線基板上にフエイスダウンで実装される半導体チ
ツプとを有することを特徴とする。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has multilayered polyimide resin and a wiring pattern formed by thin film selective plating, and at least one layer on the top surface is made of a hard inorganic compound. A multilayer wiring board formed of polyimide mixed with fine powder, a bonding pad formed on the surface of this multilayer wiring board, a lead connected to this bonding pad by thermocompression bonding, and a and a semiconductor chip mounted face-down on the multilayer wiring board.

作 用 本発明は上述のように構成したので、ポリイミ
ド多層配線基板上のボンデイングパツド上に半導
体チツプのリードまたは接続ワイヤを熱圧着する
場合、少くとも最上層に硬度の高い無機化合物混
入層があるため、表面にへこみなどの変形が起る
ことがない。Function Since the present invention is constructed as described above, when the leads or connection wires of a semiconductor chip are thermocompression bonded onto the bonding pad on a polyimide multilayer wiring board, at least the uppermost layer is a layer containing a highly hard inorganic compound. Therefore, deformations such as dents do not occur on the surface.

また、リード付き半導体チツプをフエイスダウ
ンにて実装することにより、半導体チツプに発生
する熱を、基板を介さずに、半導体チツプの裏面
から直接放散することが可能となる。このため、
半導体チツプから発生する熱は、効率良く放散さ
れる。 Furthermore, by mounting the leaded semiconductor chip face-down, the heat generated in the semiconductor chip can be dissipated directly from the back surface of the semiconductor chip without going through the substrate. For this reason,
Heat generated from semiconductor chips is efficiently dissipated.

実施例 次に本発明の実施例について図面を参照して説
明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

本発明の一実施例を断面図で示す第１図を参照
すると、本発明の半導体の実装構造は、セラミツ
ク基板１上にポリイミド樹脂２と薄膜選択めつき
法による配線パターン３とが多層に形成され、そ
の最上層はシリカまたはアルミナなどの粉末を混
入したポリイミド層４であり、更にその表面に半
導体チツプ８実装のためのボンデイングパツド５
が形成されたポリイミド多層基板１３と、このボ
ンデイングパツド５上に半導体チツプ８がフエイ
スダウンで実装された構造になつている。また、
セラミツク基板１の上面には導体パターン１２が
形成されており、裏面には入出力用ピン１１が形
成され、導体パターン１２と入出力用ピン１１と
は電気的に接続されている。 Referring to FIG. 1, which shows a cross-sectional view of an embodiment of the present invention, the semiconductor mounting structure of the present invention has a polyimide resin 2 and a wiring pattern 3 formed by a thin film selective plating method in multiple layers on a ceramic substrate 1. The top layer is a polyimide layer 4 mixed with powder such as silica or alumina, and bonding pads 5 for mounting a semiconductor chip 8 are further formed on its surface.
The semiconductor chip 8 is mounted face-down on a polyimide multilayer substrate 13 on which a bonding pad 5 is formed, and on this bonding pad 5. Also,
A conductor pattern 12 is formed on the top surface of the ceramic substrate 1, and input/output pins 11 are formed on the back surface, and the conductor pattern 12 and the input/output pins 11 are electrically connected.

ポリイミド多層基板１３の表面には、シリコン
シート７を介して半導体チツプ８を、更にその上
に冷却板１０が実装され、半導体チツプ８と冷却
板１０との間隙には良熱伝導性のコンパウンド９
が充填され、半導体チツプ８で発生した熱が冷却
板１０を介して放熱されるようになつている。ま
た、半導体チツプ８はリード６をボンデイングパ
ツド５に接続されていて、リード６とボンデイン
グパツド５は熱圧着によつてボンデイングパツド
されている。つまり半導体チツプ８はリード６、
ボンデイングパツド５、配線３、導体パターン１
２、入出用ピン１１を介して外部の装置と電気的
に接続されることになる。ここでボンデイングパ
ツド５の直下の絶縁層はシリカまたはアルミナ粉
末を混入したポリイミド４で形成されているの
で、リード６とボンデイングパツド５との熱圧着
時の圧力などに対して充分な硬度及び抗張力を持
つている。そのため、従来必要としていたボンデ
イングパツド５と配線３との間のメチル層を削除
することができる。 A semiconductor chip 8 is mounted on the surface of the polyimide multilayer substrate 13 via a silicone sheet 7, and a cooling plate 10 is further mounted thereon, and a compound 9 with good thermal conductivity is mounted in the gap between the semiconductor chip 8 and the cooling plate 10.
The heat generated by the semiconductor chip 8 is dissipated via the cooling plate 10. Further, the semiconductor chip 8 has leads 6 connected to the bonding pads 5, and the leads 6 and the bonding pads 5 are bonded together by thermocompression bonding. In other words, semiconductor chip 8 has leads 6,
Bonding pad 5, wiring 3, conductor pattern 1
2. It will be electrically connected to an external device via the input/output pin 11. Here, the insulating layer directly under the bonding pad 5 is made of polyimide 4 mixed with silica or alumina powder, so it has sufficient hardness and resistance to the pressure during thermocompression bonding between the lead 6 and the bonding pad 5. It has tensile strength. Therefore, the methyl layer between the bonding pad 5 and the wiring 3, which was conventionally necessary, can be omitted.

また、半導体チツプ８から発生した熱は、熱伝
導性の悪いポリイミド配線基板１３を介すること
なく放散される。具体的には、半導体チツプ８の
裏面、コンパウンド９および冷却板１という伝導
経路を経て、外部へ放散される。このため、半導
体チツプ８の発生する熱は、効率良く放散され
る。 Furthermore, the heat generated from the semiconductor chip 8 is dissipated without passing through the polyimide wiring board 13, which has poor thermal conductivity. Specifically, it is radiated to the outside through a conduction path of the back surface of the semiconductor chip 8, the compound 9, and the cooling plate 1. Therefore, the heat generated by the semiconductor chip 8 is efficiently dissipated.

なお本実施例では、ポリイミド多層基板と半導
体チツプとの間にシリコンシートを有し、半導体
チツプの上方に冷却板を有し、かつ入出力用ピン
が基板の下面に出た構造で説明したが、冷却板を
もたない構造でも、さらに入出力用端子を端部に
もつ構造でも同様に実施できる。さらに硬質微粉
末入りポリイミド層は一層でなく数層にしても差
支えない。 In this example, a silicon sheet is provided between a polyimide multilayer substrate and a semiconductor chip, a cooling plate is provided above the semiconductor chip, and input/output pins are provided on the bottom surface of the substrate. The present invention can be similarly implemented with a structure without a cooling plate or with a structure with input/output terminals at the ends. Furthermore, the polyimide layer containing hard fine powder may be formed into several layers instead of one layer.

発明の効果 以上に説明したように、本発明によれば、表面
に導体パターンが形成された基板の上層の少なく
とも一層をシリカもしくはアルミナなどの硬質の
無機化合物の微粉末を混入したポリイミド層と
し、薄膜選択めつき法による配線パターンとポリ
イミドとで多層化された多層配線基板を使用する
ことにより、高密度化、高速化に有利なポリイミ
ド多層配線基板の層数を最小限に抑えて、熱圧着
によつて表面にへこみを生ずることなく、半導体
を実装することができるという効果がある。Effects of the Invention As explained above, according to the present invention, at least one upper layer of a substrate on which a conductive pattern is formed is a polyimide layer mixed with fine powder of a hard inorganic compound such as silica or alumina, By using a multilayer wiring board made by multilayering a wiring pattern and polyimide using the thin film selective plating method, the number of layers of the polyimide multilayer wiring board, which is advantageous for high density and high speed, is minimized and thermocompression bonding is performed. This has the effect that semiconductors can be mounted without creating dents on the surface.

また、本発明では、前述の多層配線基板上にボ
ンデイングパツドを形成し、このボンデイングパ
ツドとリードとを熱圧着で接続し、さらにこのリ
ードを介して、多層配線基板上に半導体チツプを
フエイスダウンで実装しているため、半導体チツ
プの発生する熱を効率よく放散することができる
という効果をも有する。 Furthermore, in the present invention, a bonding pad is formed on the multilayer wiring board described above, the bonding pad and the lead are connected by thermocompression bonding, and the semiconductor chip is then faceted on the multilayer wiring board via the lead. Since it is mounted down, it also has the effect of efficiently dissipating the heat generated by the semiconductor chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す断面図、第２
図は従来技術の一例を示す断面図である。 １，１４……セラミツク基板、２，１７……ポ
リイミド、３，１５……配線、４……硬質無機粉
末入りポリイミド、５，１８……ボンデイングパ
ツド、６，１９……リード、７……シリコンシー
ト、８，２０……チツプ、９……コンパウンド、
１０……冷却板、１１……入出力用ピン、１２…
…導体パターン、１３……ポリイミド多層基板、
１６……メタル層。 FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
The figure is a sectional view showing an example of a conventional technique. 1, 14... Ceramic substrate, 2, 17... Polyimide, 3, 15... Wiring, 4... Polyimide containing hard inorganic powder, 5, 18... Bonding pad, 6, 19... Lead, 7... Silicon sheet, 8, 20...chip, 9...compound,
10...Cooling plate, 11...I/O pin, 12...
...Conductor pattern, 13...Polyimide multilayer board,
16...Metal layer.

Claims (1)

【特許請求の範囲】 １ ポリイミド系樹脂と薄膜選択めつき法による
配線パターンとによつて多層化し、最上面の少な
くとも一層を硬質の無機化合物の微粉末を混入し
たポリイミドによつて形成した多層配線基板と、 この多層配線基板の表面上に形成されるボンデ
イングパツドと、 このボンデイングパツドに熱圧着により接続さ
れるリードと、 このリードを介して前記多層配線基板上にフエ
イスダウンで実装される半導体チツプとを有する
ことを特徴とする半導体の実装構造。[Scope of Claims] 1. Multilayer wiring made of polyimide resin and a wiring pattern formed by selective thin film plating, with at least one layer on the top surface made of polyimide mixed with fine powder of a hard inorganic compound. A board, a bonding pad formed on the surface of the multilayer wiring board, a lead connected to the bonding pad by thermocompression bonding, and a board mounted face-down on the multilayer wiring board via the lead. 1. A semiconductor mounting structure comprising a semiconductor chip.
JP60192663A 1985-08-31 1985-08-31 Semiconductor package construction Granted JPS6253000A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP60192663A JPS6253000A (en) 1985-08-31 1985-08-31 Semiconductor package construction
FR868612072A FR2586885B1 (en) 1985-08-31 1986-08-26 MULTI-LAYER WIRING SUBSTRATE.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60192663A JPS6253000A (en) 1985-08-31 1985-08-31 Semiconductor package construction

Publications (2)

Publication Number Publication Date
JPS6253000A JPS6253000A (en) 1987-03-07
JPH0573079B2 true JPH0573079B2 (en) 1993-10-13

Family

ID=16294973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60192663A Granted JPS6253000A (en) 1985-08-31 1985-08-31 Semiconductor package construction

Country Status (2)

Country Link
JP (1) JPS6253000A (en)
FR (1) FR2586885B1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4880684A (en) * 1988-03-11 1989-11-14 International Business Machines Corporation Sealing and stress relief layers and use thereof
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US7198969B1 (en) 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
DE9112099U1 (en) * 1991-09-27 1991-12-05 Siemens Nixdorf Informationssysteme AG, 4790 Paderborn Flat assembly
JPH07245360A (en) * 1994-03-02 1995-09-19 Toshiba Corp Semiconductor package and manufacturing method thereof
JP3034180B2 (en) * 1994-04-28 2000-04-17 富士通株式会社 Semiconductor device, method of manufacturing the same, and substrate
US6347037B2 (en) 1994-04-28 2002-02-12 Fujitsu Limited Semiconductor device and method of forming the same
US5627405A (en) * 1995-07-17 1997-05-06 National Semiconductor Corporation Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3529759A (en) * 1967-06-15 1970-09-22 Bell Telephone Labor Inc Apparatus for bonding a beam-lead device to a substrate
JPS52149358A (en) * 1976-06-08 1977-12-12 Fujitsu Ltd Multilayer wiring method
FR2404990A1 (en) * 1977-10-03 1979-04-27 Cii Honeywell Bull SUBSTRATE FOR THE INTERCONNECTION OF ELECTRONIC COMPONENTS WITH INTEGRATED CIRCUITS, EQUIPPED WITH A REPAIR DEVICE
JPS6022396A (en) * 1983-07-19 1985-02-04 日本電気株式会社 Circuit board
JPS6070798A (en) * 1983-09-27 1985-04-22 富士通株式会社 Interlayer insulating layer

Also Published As

Publication number Publication date
JPS6253000A (en) 1987-03-07
FR2586885A1 (en) 1987-03-06
FR2586885B1 (en) 1989-12-01

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