JPH057308A - Sync signal detection and playback system - Google Patents

Abstract

PURPOSE:To simplify circuit configuration by deciding whether the level and the period of a signal obtained by envelope-detecting the IF signal of a MUSE signal satisfy a prescribed condition or not, and detecting the HD of all lines from a decided result. CONSTITUTION:An envelope detecting part 1 fetches the IF signal of definite amplitude obtained by receiving the MUSE signal, and simultaneously, it extracts an envelope signal by detecting the IF signal, and supplies it to an A/D converting part 2. The converting part 2 fetches and quantizes the envelope signal at a period set beforehand, and converts it into the digital signal of the preset number of bits, and supplies it to a synchronous signal detecting part 3. The detecting part 3 detects the clamp level period of the digital signal, and detects an HD period, and simultaneously, it generates a second gate signal corresponding to the HD period, and supplies it to an HD synchronizing signal regenerating part 4. In such a configuration, the synchronous signal of the MUSE signal can be detected by a simple circuit, and the drastic can be attained.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION The present invention transmits a MUSE signal to VSB-
The present invention relates to a sync signal detection and reproduction method used when overmodulated by the AM method.

SUMMARY OF THE INVENTION The present invention provides a MUSE signal for V
Whether the level of the signal obtained by envelope detection of the IF signal when overmodulated by the SB-AM method or the level of the signal obtained by directly sampling the IF signal and the period satisfy a predetermined condition Is detected to detect the clamp level period, the HD of all lines is detected based on the detection result, and the HD sync signal is reproduced based on the detection result and each of the signals.

[0004]

2. Description of the Related Art In a television system of the NTSC signal system, since the sync signal has a negative polarity, the sync signal is separated and extracted using a technique such as amplitude separation.

[0005]

However, MUs used in hi-vision television systems and the like.
Since the SE signal uses the positive sync signal,
The synchronization signal cannot be extracted by such techniques as amplitude separation.

For this reason, there is a problem in that the synchronizing signal must be extracted by a very complicated circuit as used in the MUSE decoder or the like, resulting in an increase in manufacturing cost.

In view of the above circumstances, the present invention can detect the sync signal of the MUSE signal and reproduce the sync signal with a simple circuit, thereby significantly reducing the cost of the sync signal detection circuit and the sync signal reproduction circuit portion. It is an object of the present invention to provide a synchronization detection and reproduction method capable of achieving down.

[Structure of Invention]

[0009]

In order to achieve the above object, the synchronization signal detection method according to the present invention is such that the level and period of the signal obtained by envelope detection of the IF signal of the MUSE signal satisfy predetermined conditions. A clamp level detection unit that determines whether or not it is satisfied, and H that detects HD for the HD period of all lines based on the determination result of this clamp level detection unit.
And a D detector.

The sync signal reproducing system according to the present invention is
The HD portion of the signal obtained by envelope detection of the IF signal of the MUSE signal is gated based on the detected HD, and the operation is performed based on the signal obtained by this gating operation to calculate from the midpoint of the HD period. A phase error detection unit that generates a phase error signal indicating a shift, a clock generation unit that regenerates a clock signal based on the phase error signal obtained by this phase error detection unit, and a clock signal obtained by this clock generation unit And an HD sync signal reproducing section for reproducing the HD sync signal each time the count value reaches a predetermined value.

[0011]

In the above structure, the clamp level detection unit determines whether the level of the signal obtained by envelope detection of the IF signal of the MUSE signal and the period satisfy the predetermined conditions, and the HD detection unit. Thus, the HD of all lines is detected from the determination result of the clamp level detection unit.

[0012]

1 is a block diagram showing an example of a sync signal detection / reproduction circuit to which a first embodiment of a sync signal detection / reproduction system according to the present invention is applied.

The synchronizing signal detecting / reproducing circuit shown in this figure includes an envelope detecting section 1, an A / D converting section 2, a synchronizing detecting section 3 and an H detecting section.
D sync signal reproducing section 4 and I obtained by receiving the MUSE signal transmitted in the transmission signal format shown in FIG.
F signal is taken in, the clamp level part is detected and H
When the D period is detected, the HD sync signal corresponding to this HD period is reproduced.

The envelope detecting section 1 takes in an IF signal of a constant amplitude obtained by receiving the MUSE signal, detects this IF signal and extracts an envelope signal, and A / D this.
It is supplied to the conversion unit 2.

The A / D conversion unit 2 takes in the envelope signal output from the envelope detection unit 1 at a preset cycle, for example, a clock rate of 32.4 MHz, quantizes it, and is preset. It is converted into a digital signal having the number of bits, for example, 8 bits, and this is supplied to the synchronization detection unit 3.

The synchronization detector 3 includes a first gate signal generator 5
And a system clock signal generation unit 6, a second gate signal generation unit 7, and a control signal generation unit 8.
The HD level is detected by detecting the clamp level period of the digital signal output from the / D conversion unit 2, and the second gate signal corresponding to this HD period is generated and supplied to the HD synchronization signal generation unit 4. To do.

As shown in FIG. 3, the first gate signal generation section 5 includes a clamp level detection circuit 10, a clamp period determination circuit 11, a signal loop circuit 12, and a first gate signal generation circuit 13, and The digital signal output from the A / D conversion unit 2 is taken in to detect the clamp level period, and the first gate signal is generated based on the detection result, and the first gate signal is generated by the system clock signal generation unit 6.
The signal is supplied to the second gate signal generator 7 and the control signal generator 8.

The clamp level detection circuit 10 outputs a reference level signal having a level corresponding to the modulation degree of the IF signal input to the envelope detection unit 1, for example, a level close to zero in a state where carrier suppression is extremely close. The difference between the set level setting circuit 14 and the reference level signal output from the level setting circuit 14 and the digital signal output from the A / D converter 2 is calculated to generate a difference signal indicating the absolute value thereof. Difference extraction circuit 15, a clamp level setting circuit 16 for setting a clamp level determination value, a value of a difference signal output from the difference extraction circuit 15, and a clamp level determination set in the clamp level setting circuit 16. When the value of the difference signal output from the difference extraction circuit 15 is smaller than the clamp level determination value by comparing with the value, a low level A comparator circuit 17 for generating an intelligent signal, a rise detection circuit 18 for detecting a low level detection signal when the low level detection signal is output from the comparator circuit 17, and a low level detection signal for the comparator circuit 17 Is output, a fall detection circuit 19 is provided for detecting this and generating a clear signal.

Then, when the digital signal output from the A / D converter 2 is taken in and the difference between the level of this digital signal and the reference level signal becomes smaller than a preset clamp determination value, a low level is set. A detection signal is generated and supplied to the clamp period determination circuit 11, a load signal is generated and supplied to the clamp period determination circuit 11, and the difference between the level of the digital signal and the reference level signal is the above-mentioned. When it becomes larger than the clamp judgment value, the generation of the low level detection signal is stopped, and the clear signal is generated to generate the clear signal.
Supply to 1.

The clamp period determination circuit 11 is an OR circuit 20 which takes the logical sum of the load signal output from the clamp level detection circuit 10 and the load signal output from the signal loop circuit 12, and the clamp period data value "748". When the load signal is output from the clamp period data setting circuit 21 in which is set and the OR circuit 20, the clamp period data value “748” set in the clamp period data setting circuit 21 is used as an initial count value. Before the clamp level detection circuit 10 outputs a clear signal by decrementing the count value each time a system clock signal is supplied, the clamp level period is set to 0 when the count value becomes zero. And a counter circuit 22 for generating a clamp period end detection signal indicating that the end of is detected. That.

Then, the clamp level detection circuit 10
Each time the load signal is output from the signal loop circuit 12 or the clamp period data value “74” set in the clamp period data setting circuit 21 by the counter circuit 22.
8 "is loaded, and thereafter, the count value is decremented each time the system clock signal is supplied, and before the clamp level detection circuit 10 outputs a clear signal, when the count value becomes zero, A clamp period end detection signal indicating that the end of the clamp period has been detected is generated, and is generated as a signal loop circuit 12 and a first gate signal generation circuit 1.
3 and supply.

The signal loop circuit 12 performs a shift operation each time a system clock signal is supplied, and when a clamp period end detection signal is output from the clamp period determination circuit 11, the signal loop circuit 12 takes in the signal and outputs H after "22" clocks.
Shift register circuit 23 that outputs as a D period end signal
And a gap period data setting circuit 24 in which a gap period data value “190” indicating the length between the clamp level period of the MUSE signal and the HD synchronization period is set, and the HD period end signal from the shift register circuit 23. When output,
The gap period data value "190" set in the gap period data setting circuit 24 is loaded as an initial count value, and thereafter, each time the system clock signal is supplied, the count value is decremented to zero. And a counter circuit 25 that generates a load signal that indicates the start timing of the current clamp level period that is predicted based on the previous measurement result.

When the clamp period determination circuit 11 outputs a clamp period end detection signal, the clamp period end detection signal is fetched and delayed by "22" clocks, and when the system clock signal is counted by "190", a load signal is output. It is generated and supplied to the clamp period determination circuit 11.

Further, the first gate signal generating circuit 13 has a line number setting circuit 26 in which a line numerical value obtained by an experiment or the like is set, and each time the clamp period determining circuit 11 outputs a clamp period end detection signal. This is counted, and when the count result and the line number set in the line number setting circuit 26 match, a counter circuit 27 that generates a detection signal and period data in which a clock number for one scanning line is set Each time a detection signal is output from the setting circuit 29 and the counter circuit 27, the clock numerical value set in the period data setting circuit 28 is loaded as an initial count value, and then the system clock signal is supplied. A counter circuit 29 for decrementing the count value every time and generating a first gate signal when the count value becomes zero. That.

When the clamp period end detection signal is output a predetermined number of times from the clamp period determination circuit 11, counting of the system clock signal is started and when the system clock signal is counted "960", the first gate signal Is generated and supplied to the system clock signal generation unit 6, the second gate signal generation unit 7, and the control signal generation unit 8.

The system clock signal generator 6 outputs the first gate signal generator 5 as shown in FIG.
A phase comparison circuit 3 that compares the phase of the gate signal with the phase of the feedback signal and generates a signal having a voltage value according to the comparison result.
0, a loop filter circuit 31 that integrates the signal output from the phase comparison circuit 30, and the control signal generation unit 8
When the second control signal is not output from the loop filter circuit 31, the signal output from the loop filter circuit 31 is taken and output, and when the second control signal is output from the control signal generation unit 8, the loop filter circuit is output. A sample and hold circuit 32 that samples the signal output from the circuit and holds it until the second control signal is no longer output, and continues to output the sampled signal, and the voltage of the signal output from the sample and hold circuit 32. A VCXO 33 that oscillates at a frequency (fundamental frequency is “33.75 KHz”) according to the value to generate a system clock signal,
The system clock signal output from the VCXO 33 is frequency-divided into "1/1125" to generate a feedback signal, and the frequency-dividing circuit 34 supplies the feedback signal to the phase comparison circuit 30.

Then, a system clock signal synchronized with the first gate signal output from the first gate signal generation unit 5 is generated and is generated by the first gate signal generation unit 5,
And the second gate signal generator 7.

The second gate signal generator 7 outputs the first gate signal from the first gate signal generator 5 when the control signal generator 8 outputs the first control signal as shown in FIG. AND circuit 35 for passing through, and a period data setting circuit 36 for setting the clock numerical value "960" for one scanning line. When the first gate signal is output from the AND circuit 35, the AND circuit 35 is reset to the initial state. Then, the clock value set in the period data setting circuit 36 is loaded as an initial count value, and thereafter, the count value is decremented every time the system clock signal is supplied, and the count value becomes zero each time. The counter circuit 37 includes a counter circuit 37 which generates the second gate signal, returns to the initial state, and repeats this operation.

Then, when the first gate signal generator 5 outputs the first gate signal while the control signal generator 8 is outputting the first control signal, the counter circuit 37 is reset. While returning to the initial state, the clock numerical value set in the period data setting circuit 36 is loaded as the initial count value. After that, the count value is decremented each time the system clock signal is supplied, and the second gate signal is generated every time the count value becomes zero, and the state returns to the initial state. Hereinafter, this operation is repeated to "96
The second gate signal is generated every 0 "clock and supplied to the control signal generation unit 8 and the HD synchronization signal reproduction unit 4.

The control signal generator 8 comprises a first control signal generator 40 and a second control signal generator 41 as shown in FIG. 6, and the first gate signal generator 5 outputs the first gate signal. When the relationship between the signal and the second gate signal output from the second gate signal generator 7 does not satisfy a preset condition, a first control signal is generated to generate the second gate signal. The system clock signal generator 6 supplies the second control signal to the unit 7 or generates the second control signal.
Or to supply.

The first control signal generation circuit 40 is composed of two AND circuits 42 and 44 and one OR circuit 43, and the first control signal generation circuit 5 outputs the first gate signal generation unit 5.
When the gate signal and the second gate signal output from the second gate signal generator 7 do not match in time, the mismatch detection circuit 45 detects this and generates a pulse signal.
A counter circuit 46 that counts each time a pulse signal is output from the mismatch detection circuit 45 and returns the count value to zero when the first control signal is supplied, and a count value of the counter circuit 46. When it reaches a preset value, a comparator circuit 47 that detects this and generates a first control signal to reset the counter circuit 46 is provided. When a state in which the first gate signal output and the second gate signal output from the second gate signal generator 7 do not match occurs a predetermined number of times, this is detected and a first control signal is generated. Then, this is supplied to the second gate signal generator 7.

As a result, after the first gate signal is no longer output from the first gate signal generator 5, FIG.
As shown in FIG. 7C, when the first gate signal generator 5 starts to output the first gate signal, as shown in FIG.
The second gate signal output from the gate signal generator 7 is synchronized with the first gate signal, and the system clock signal output from the system clock signal generator 6 is transferred to the first gate as shown in FIG. 7B. Synchronize to the signal.

The second control signal generation circuit 41 is composed of one AND circuit 48, and the first gate signal generation unit 5 is in a state where the second gate signal generation unit 7 outputs the second gate signal. When the first gate signal is no longer output from the device, a signal presence / absence detection circuit 49 for detecting this and generating a rising pulse signal, a data setting circuit 50 for setting data "1", and the second gate signal generation When the second gate signal is output from the section 7, the data “1” set in the data setting circuit 50 is loaded, and in this state, when the rising pulse signal is output from the signal presence / absence detection circuit 49, And a down counter circuit 51 for down counting the loaded data “1” to generate a second control signal. When the first gate signal generator 5 stops outputting the first gate signal while the gate signal is being output, this is detected to generate a second control signal, which is generated by the system clock signal generator. 6 and locks the frequency of the system clock signal output from the system clock signal generator 6.

The HD sync signal reproducing section 4 includes a phase error signal detecting section 55, a loop filter section 56, and a VCXO 5
7 and a counter circuit 58, and based on the second gate signal output from the second gate signal generator 7 as shown in FIG. 9A, the A gate signal as shown in FIG.
The HD period portion of the digital signal output from the / D converter 2 is cut out, the midpoint of the HD period is detected based on the cut out digital signal, and the HD sync signal is reproduced at an accurate timing according to the midpoint. To do.

As shown in FIG. 8, the phase error signal detector 55 includes a gate circuit 56, a shift register circuit 58, and an arithmetic circuit 59. The second gate signal generator 7 outputs the second gate. Based on the signal, the digital signal output from the A / D converter 2 is gated to select only the HD portion, and an operation is performed based on the selected digital signal to show an error from the midpoint of the HD period. A phase error signal is generated and supplied to the loop filter unit 56.

When the second gate signal is output from the second gate signal generator 7, the gate circuit 56 outputs the A signal.
The digital signal output from the / D converter 2 is passed and supplied to the shift register circuit 58 and the arithmetic circuit 59.

Each time the shift register circuit 58 is supplied with the clock signal, the shift register circuit 58 takes in the digital signal output from the gate circuit 56, sequentially shifts and delays the digital signal, and "8" obtained by this delay operation. The digital signal before “clock” and the digital signal before “4” clock are supplied to the arithmetic circuit 59.

The arithmetic circuit 59 is the shift register circuit 5
A sign inverting circuit 65 that takes in the digital signal “8” clock before output from 8 and inverts the sign, a digital signal whose sign is inverted by the sign inverting circuit 65, and the current time output from the gate circuit 56. An adding circuit 66 for adding a digital signal, an absolute value circuit 67 for obtaining an absolute value of the digital signal obtained by the adding operation of the adding circuit 66, and a digital signal output from the absolute value circuit 67 Coefficient circuit 6 that multiplies -1/2 "
8 and an adder circuit 69 for adding the digital signal output from the coefficient circuit 68 and the digital signal “4” clocks before output from the shift register circuit 58 to generate a phase error signal. , Based on the digital signal “8” clocks before the shift register 58, the digital signal “4” clocks before, and the current digital signal output from the gate circuit 56. A phase error signal indicating an error from the midpoint of the HD period is calculated and supplied to the loop filter unit 56.

[0039]

[Equation 1]

In this case, as is apparent from the equation (1), the over-modulation is such that the polarity of the carrier in the HD waveform portion of the IF signal of the MUSE signal is inverted line by line,
As shown in FIG. 9B, even if the sign of the differential value of the level of the digital signal output from the A / D conversion unit 2 is inverted with the minimum point as Sakai, it is determined once per line. HD
It is possible to reliably detect the midpoint of the period and obtain the phase error with respect to the midpoint.

The loop filter unit 56 integrates the phase error signal output from the phase error signal detection unit 55 and supplies the signal obtained by this integration operation to the VCXO 57.

The VCXO 57 is the loop filter section 56.
Oscillates at a frequency according to the signal output from the clock signal to generate a clock signal,
The signal is supplied to the A / D converter 2 and the counter circuit 58.

The counter circuit 58 counts the clock signal output from the VCXO 57 and has a count value of "96".
Each time it becomes 0 ″, an HD sync signal is generated and output to the next stage circuit (not shown).

As described above, in this embodiment, since the level of the MUSE signal obtained by the receiving operation and the period determination are performed to detect the clamp level period, the HD of the MUSE signal can be detected by a simple circuit. It is possible to detect the period and reproduce the HD sync signal, which can achieve a significant cost reduction of the sync signal detection circuit portion.

Further, in the above-mentioned embodiment, the preset value of the level according to the modulation degree of the IF signal by the difference extraction circuit 15 provided in the first gate signal generation section 5,
Since the difference from the digital signal corresponding to the IF signal is extracted and the absolute values of these differences are used, malfunction due to noise can be prevented.

In addition, the first gate signal generator 5 causes I
Since the level determination of the F signal and the period determination of the “748” clock are performed over several frames to detect the clamp level period, the MU transmitted from the transmission side is detected.
Detecting the clamp level period even if the modulation degree of the SE signal is close to carrier suppression and the IF signal level in the clamp level period becomes very close to zero or overmodulation correspondingly. You can In this case,
As shown in FIG. 2, there is a possibility that a similar signal exists in the Y signal of the image. However, even if such a signal is erroneously determined as a signal in the clamp level period, the HD period exists immediately after that period. It doesn't matter. Further, there is a possibility that a signal similar to the above-mentioned signal may exist over the C signal period of the video and the Y signal period. However, in this embodiment, the signal loop circuit 12 terminates the HD period. Since it is determined from "191" clocks after,
Even if the counter 22 of the clamp period determination circuit 11 starts to operate by such a signal, a signal whose detection is started within “190” clocks by the signal loop circuit 12 can be excluded as an erroneous detection.

Further, in the above-described embodiment, the phase of the first gate signal output from the first gate signal generation section 5 and the phase of the second gate signal output from the second gate signal generation section 7 are When it deviates by a predetermined value or more, the control signal generation unit 8 detects this and generates a first control signal, and the counter circuit 37 of the second gate signal generation unit 7 is reset by this first control signal to reset the second control signal. Since the phase of the second gate signal output from the gate signal generation unit 7 is synchronized with the phase of the first gate signal output from the first gate signal generation unit 5, The deviation between the phase of the output first gate signal and the phase of the second gate signal output from the second gate signal generator 7 can be kept within a certain value.

Further, in the above-described embodiment, when the first gate signal generator 5 stops outputting the first gate signal while the second gate signal generator 7 outputs the second gate signal. Before the first gate signal is no longer output from the first gate signal generator 5 to the sample and hold circuit 32 by detecting this and generating the second control signal and supplying the second control signal to the system clock signal generator 6. Therefore, even if the first gate signal generator 5 does not output the first gate signal, the first gate signal generator 5 outputs the new first gate signal until the first gate signal is output. During this period (for example, for several frames), a substantially accurate system clock signal can be generated, which allows the second gate signal generator 7 to generate a substantially accurate second clock signal.
A gate signal can be output.

Further, in this embodiment, the phase error signal indicating the error from the midpoint of the HD period is generated to generate VCXO.
Since the HD sync signal is reproduced by counting the clock signals while making the phase of the clock signal output from 57 correspond to the midpoint, it is possible to reproduce an accurate HD sync signal.

FIG. 10 is a block diagram showing an example of a sync signal detecting and reproducing circuit to which the second embodiment of the sync signal detecting and reproducing system according to the present invention is applied. In this figure, the same parts as those shown in FIG. 1 are designated by the same reference numerals.

The sync signal detection / reproduction circuit shown in FIG.
The difference from the circuit shown in FIG. 5 is that a sampling unit 75 is provided in place of the envelope detection unit 1 and the A / D conversion unit 2, and a first gate signal generation unit 76 is provided in place of the first gate signal generation unit 5. That is.

The sampling unit 75 receives the I of the MUSE signal whose carrier is suppressed at the sampling timing based on the clock signal output from the HD sync signal reproducing unit 4.
The F signal is directly sampled to extract the digital signal,
This is the same as the first gate signal generator 76 of the synchronization detector 3 and H
It is supplied to the phase error detection unit 55 of the D synchronization signal reproduction unit 4.

As shown in FIG. 11, the first gate signal generating section 76 is provided with a clamp level detecting circuit 77, a clamp period determining circuit 11, a signal loop circuit 12, and a first gate signal generating circuit 13, and The digital signal output from the sampling unit 75 is captured to detect the clamp level period, and the first level is detected based on the detection result.
A gate signal is generated and used to generate a system clock signal generation unit 6, a second gate signal generation unit 7, and a control signal generation unit 8.
And supply to. The clamp period determination circuit 11, the signal loop circuit 12, and the second gate signal generation circuit 13 shown in this figure are the same as those provided in the first gate signal generation unit 5 described above.

The clamp level detecting circuit 77 comprises a digital value judging circuit 78, a rising edge detecting circuit 18 and a falling edge detecting circuit 19, and the sampling section 7
When the digital signal output from 5 is taken in and the value of this digital signal is "0" or "1", a low level detection signal ("1" signal) is generated and supplied to the clamp period determination circuit 11. At the same time, a load signal is generated and supplied to the clamp period determination circuit 11, and when the value of the digital signal becomes "2" or more, the generation of the low level detection signal is stopped and the clear signal is generated. Then, this is supplied to the clamp period determination circuit 11.

In this case, the digital value judgment circuit 78 is shown in FIG.
2, an inverter 80 that inverts the upper "7" bits of the digital signal output from the sampling unit 75, an inverter 81 that inverts the least significant bit of the digital signal, and a digital output from the sampling unit 75. The least significant bit of the signal and the inverter 80
AND circuit 82 for detecting the digital signal when the value of the digital signal is "1" by taking the logical product with the signal output from
And an AND circuit 83 for detecting the AND of the signals output from the inverters 80 and 81 when the value of the digital signal output from the sampling unit 75 is “0”, and each of these. And an OR circuit 84 that takes the logical sum of the signals output from the AND circuits 82 and 83, and detects the low level when the digital value output from the sampling unit 75 is "0" or "1". A signal is generated and is supplied to the clamp period determination circuit 11, the rising edge detection circuit 18, and the falling edge detection circuit 19.

As a result, like the clamp level detecting circuit 10 of the above-described embodiment shown in FIG. 3, when the value of the digital signal is at the clamp level, it is detected and the clamp period determining circuit 11 is operated. be able to.

Even in this case, the HD sync signal can be reproduced by detecting the clamp level period of the MUSE signal by the same simple circuit as in the above-described embodiment, whereby the sync signal detection circuit and the sync signal reproduction are performed. It is possible to significantly reduce the cost of the circuit portion.

[0058]

As described above, according to the present invention, the synchronizing signal of the MUSE signal can be detected and the synchronizing signal can be reproduced by a simple circuit, whereby the synchronizing signal detecting circuit and the synchronizing signal reproducing circuit portion can be obtained. It is possible to achieve a significant cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a sync signal detection / reproduction circuit to which a first embodiment of a sync signal detection / reproduction system according to the present invention is applied.

FIG. 2 is an MU input to the synchronization signal detection circuit shown in FIG.
It is a schematic diagram which shows the example of a format of SE signal.

FIG. 3 is a block diagram showing a detailed circuit example of a first gate signal generation unit shown in FIG.

FIG. 4 is a block diagram showing a detailed circuit example of a system clock signal generation unit shown in FIG.

5 is a block diagram showing a detailed circuit example of a second gate signal generation unit shown in FIG.

FIG. 6 is a block diagram showing a detailed circuit example of a control signal generation unit shown in FIG.

FIG. 7 is a timing diagram showing an operation example of the synchronization detection unit shown in FIG.

FIG. 8 is a block diagram showing a detailed circuit example of a phase error detection unit shown in FIG. 1.

9 is a waveform diagram showing an operation example of the HD synchronization signal reproducing section shown in FIG.

FIG. 10 is a block diagram showing an example of a sync signal detection / reproduction circuit to which a second embodiment of the sync signal detection / reproduction system according to the present invention is applied.

11 is a block diagram showing a detailed circuit example of a first gate signal generation unit shown in FIG.

12 is a circuit diagram showing a detailed circuit example of the digital value determination circuit shown in FIG.

[Explanation of symbols]

1 Envelope detector 2 A / D converter 3 Sync detector 4 HD sync signal playback unit 5 First gate signal generator (clamp level detector) 7 Second gate signal generator (HD detector) 55 Phase error detector 57 VCXO (clock generator) 58 Counter circuit (HD sync signal reproduction section) 75 Sampling section

Claims (3)

[Claims] 1. A clamp level detector for determining whether a level and a period of a signal obtained by envelope detection of an IF signal of a MUSE signal satisfy a predetermined condition, and a determination result of the clamp level detector. HD based on the whole line
A synchronization signal detection method, comprising: an HD detection unit that detects HD for a period. 2. The clamp level detector is the MUS.
2. The synchronization signal detecting method according to claim 1, wherein the IF signal of the E signal is directly sampled to determine whether the level and the period satisfy a predetermined condition. 3. The HD period of the signal obtained by envelope detection of the IF signal of the MUSE signal based on the detected HD is gated, and the operation is performed based on the signal obtained by the gate operation to perform the HD period. , A phase error detection unit that generates a phase error signal indicating a deviation from the midpoint, a clock generation unit that regenerates a clock signal based on the phase error signal obtained by the phase error detection unit, and a clock generation unit A synchronizing signal reproducing system, comprising: an HD synchronizing signal reproducing unit that counts the obtained clock signals and reproduces an HD synchronizing signal each time the count value reaches a predetermined value.