JPH0573272A - Digital data integrator - Google Patents

Abstract

(57) [Summary] [Configuration] The adder 1 adds the input data input to one input terminal and the output data of the register 2 input to the other input terminal. The register 2 latches the output of the adder 1 in synchronization with the clock and outputs it as lower data. The register 3 latches the carry output of the adder 1 in synchronization with the clock. The logical product circuit 5 outputs a logical product of the clock delayed by the buffer 4 by a predetermined amount and the output of the register 3. The counter 6 receives the output of the AND circuit 5, counts up, and outputs it as upper data. [Effect] Since a large number of adders used for high-order data processing are not required, if the data length of the input data is smaller than the data length of the output data, the number of parts, wiring amount, and power consumption can be reduced. It is possible to downsize the device and reduce power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data integrator, and more particularly to a digital data integrator effective when the data length of input data is smaller than the data length of output data.

[0002]

2. Description of the Related Art A conventional digital data integrator has six 4-bit adders 11 to 11 as shown in FIG. 2 when the output data length is 24 bits and the input data length is 4 bits, for example.
It is composed of 16 and 6 4-bit registers 21 to 26.

[0003]

As described above, since the conventional digital data integrator requires the number of adders and registers corresponding to the output data length, the number of parts is increased and the wiring amount and consumption are increased. Since the electric power also increases, it has a drawback that it is difficult to reduce the size and power consumption of the device.

An object of the present invention is to provide a digital data integrator capable of reducing the number of parts, downsizing the device and reducing power consumption.

[0005]

A digital data integrator of the present invention comprises an adder for adding input data input to one input terminal and data input to the other input terminal,
First to latch the output of this adder in synchronization with the clock
Register, a second register for latching the carry output of the adder in synchronization with the clock, a delay circuit for giving a predetermined delay to the clock, an output of the delay circuit and the second register. An AND circuit that outputs a logical product with the output and a counter that counts up by receiving the output of the AND circuit are provided, and the output of the first register is supplied to the other input terminal of the adder. At the same time, the output of the first register is used as the lower data of the integrated output, and the output of the counter is used as the higher data of the integrated output.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Output data length is 24 bits, input data length is 4
The figure shows the case of bits, and 4-bit adder 1 and 4
20-bit register 2 and 1-bit register 3
It is composed of a bit counter 4, a 2-input AND circuit 5, and a buffer 4 for delaying a clock.

Next, the operation will be described.

The adder 1 receives 4-bit input data synchronized with the clock at the input A terminal and at the same time adds the output data one clock before applied to the input B terminal. The register 2 latches the addition result of the adder 1 at the next clock and outputs it as lower data. If a carry occurs due to the addition of the adder 1, the register 3 latches the carry at the next clock.

The logical product circuit 5 sends the logical product of the clock delayed by the buffer 4 and the carry output output from the register 3 to the counter 6. The counter 6 receives the output of the AND circuit 5 at the clock terminal, detects the rising edge and counts up, and outputs the count result as 20-bit upper data.

As described above, the counter is operated only when a carry is generated from the lower order to generate higher order data of 20 bits, and is combined with the lower order data of 4 bits output from the register 2 to output an integrated output of 24 bits. To get

[0012]

As described above, the digital data integrator of the present invention adds lower data by using the data length of the input data as the data length of the lower data, and the addition of the lower data causes a carry. By providing a counter that operates only when the output data is high-order data, the large number of adders used to process high-order data in the past becomes unnecessary. If the data length of is small,
The amount of wiring and power consumption can be reduced, and the device can be downsized and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional digital data integrator.

[Explanation of symbols]

 1 adder 2, 3 register 4 buffer 5 AND circuit 6 counter

Claims (1)

[Claims] 1. An adder for adding input data input to one input terminal and data input to the other input terminal, and a first register for latching an output of the adder in synchronization with a clock. A second register for latching the carry output of the adder in synchronization with the clock, a delay circuit for giving a predetermined delay to the clock, and a logic of the output of the delay circuit and the output of the second register. A logical product circuit that outputs a product and a counter that counts up by receiving the output of the logical product circuit are provided, and the output of the first register is supplied to the other input terminal of the adder and A digital data integrator, wherein the output of the register 1 is the lower data of the integrated output and the output of the counter is the higher data of the integrated output.