JPH0573343A - Data transfer processor - Google Patents

Abstract

PURPOSE:To execute the data transfer normally by switching a fault line to a shape line in case of the occurrence of a fault in a data bus during the transfer of data. CONSTITUTION:In case an error is detected in a parity checker 6 from the data sent from a transmission circuit 1, the data transfer is performed using the spare line by a 1/n changeover circuit 8 from the O bit of the data in a microprocessor 10, to switch the data in the fixed fault position by a 1/2 changeover circuit 5. This operation is repeated in succession to perform the normal data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer processing device, and more particularly to a data transfer processing device for transmitting and receiving data on a bus line with parity.

[0002]

2. Description of the Related Art In a conventional data transfer processing device,
I only checked the parity error with the parity checker.

[0003]

Therefore, although the processing could be stopped, it could not be continued in a normal state.

An object of the present invention is to provide a data transfer processing device capable of transferring normal data and continuing processing even when a failure occurs in the bus.

[0005]

To achieve the above object, in a data transfer processing device according to the present invention, a parity checker, a data bus, a spare line, a driver / receiver, a 1 / n switching circuit, A data transfer processing device having a 1/2 switching circuit and a microprocessor, wherein a parity checker checks for the presence of a parity error, and a data bus transfers data and a parity check additional pit, respectively. The spare line is for transmitting data instead of when the data bus has failed, the driver / receiver is for transferring data to the data bus, and the 1 / n switching circuit is , To switch between data bus and spare line,
The 1/2 switching circuit switches between the data from the data bus and the data from the spare line, and the microprocessor selects 1 / n switching circuit or 1 / n switching circuit depending on the presence / absence of a parity error in the parity checker.
The control circuit controls the switching operation with the two switching circuits.

When an error is detected by the parity checker, the microprocessor checks for 0 bit of data.
To 1 / n switching circuit performs data transfer using a spare line, the 1/2 switching circuit switches to data at a fixed failure position, and this operation is sequentially repeated to perform normal data transmission.

[0007]

Function: A parity bit is added to the data.
When the parity checker receives this data and a parity error occurs, the data bus is sequentially switched to the spare line to transfer normal data.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, the device of the present invention has the following configuration. That is, the transmitting side circuit 1 for transmitting data and parity bits, the driver 2 for transmitting data from the transmitting side circuit 1 to the data bus 11, and the data to be transmitted connected to the data bus 11 are transmitted to the receiving side circuit 3.
A data signal from the data bus received by the receiver 4 in the receiving side circuit 3 by the 1/2 switching signal line 203 from the receiver 4 and the 1/2 selection flag register 9.
The 1 / n selection flag register 8 and the 1/2 selection flag register 9 are set by the control signal line 204 by the 1/2 switching circuit 5 for switching the data from the spare line 12 and the control signal line 201 from the parity checker 6. Microprocessor 10, 1 / n selection flag register 8
1 / n switching circuit 7 and 1/2 switching circuit 5 capable of selecting 1 bit from the data signal line 101 from the transmission side circuit 1 by the 1 / n switching signal line 202 from
The parity error check is performed by receiving the signal of the corrected data signal line 103 output from the data signal line 104.
And a parity checker 6 for outputting a signal to the control signal line 201.

When data is transmitted from the transmission side circuit 1 to the reception side circuit 3, the data is transmitted to the driver 2 and the 1 / n switching circuit 7 by the data signal line 101.

The data 101 sent to the driver 2 is output to the data bus 11 and input to the receiver 4 of the receiving side circuit 3.

The data 101 input to the 1 / n switching circuit 7 is controlled by the 1 / n switching signal line 202 from the 1 / n selection flag register 8 to be output to the spare line 12 and the receiver of the receiving side circuit 3. Input to 4.

The data bus 11 input to the receiver 4,
The data on the spare line 12 is output to the data signal lines 102 connected to the 1/2 switching circuit 5, respectively.

The data input to the 1/2 switching circuit 5 is controlled by the 1/2 switching signal line 203 from the 1/2 selection flag register 9 and output to the corrected data signal line 103.

The data from the corrected data signal line 103 is input to the parity checker 6 and subjected to a parity error check, and the data signal line 104 and the control signal line 2 are received.
It is output to 01.

The control signal line 201 is connected to the microprocessor 10 and sets the 1 / n selection flag register 8 and the 1/2 selection flag register 9 by the signal of the control signal line 201.

At the time of the first transmission, the 1/2 switching signal lines 203, 1 / from the 1/2 selection flag register 9 are sent.
1 / n switching signal line 2 from the n selection flag register 8
02 is all off, so corrected data line 1
03 has the same value as the data signal line 101.

When the data from the corrected data line 103 is input to the parity checker 6, the parity checker 6 determines whether the data has an error, and if there is no error, the value of the corrected data line 103 is determined. It is directly output to the data signal line 104.

If it is not detected by the parity checker 6, as shown in FIG. 2, the control signal line 201 remains off, and the processing is continued. When the parity checker 6 detects an error, the control signal line 201 notifies the microprocessor 10 of the error occurrence.

The microprocessor 10 which has recognized the occurrence of the error sets the 1 / n selection flag register 8 and the 1/2 selection flag register 9 via the control signal line 204.
By setting the 1 / n selection flag register 8 and the 1/2 selection flag register 9, 1 is set as shown in FIG.
The / n switching circuit 7 transmits the 0th bit data in the data bus 11 to the receiving side circuit 3 using the spare line 12.

In the receiving side circuit 3, the 1/2 switching circuit 5
Then, the 0-bit data and the data transmitted from the spare line 12 are switched and the corrected data is changed to the data line 1.
Output to 03. The data from the corrected data line 103 input to the parity checker 6 undergoes a parity check, and if no error is detected, the process is continued as shown in FIG.

When an error is detected again, the microprocessor 10 controls the data of the first bit to be transmitted through the spare line 12, and the 1/2 switching circuit 5
The data is switched by and output as corrected data.

If a parity error is detected even if the above operation is performed n-1 times, the data bus 11 is normal and it is considered that an error has occurred in another part, so the processing is interrupted. ..

[0024]

As described above, according to the present invention, when an error is detected by the parity checker, the microprocessor transfers data from the 0th bit of data using the 1 / n switching circuit using the spare bus. There is an effect that normal data transmission can be performed by sequentially repeating the operation of switching to the data at the fixed failure position by the two switching circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of the present invention.

[Explanation of symbols]

 1 Transmission Side Circuit 2 Driver 3 Reception Side Circuit 4 Receiver 5 1/2 Switching Circuit 6 Parity Checker 7 1 / n Switching Circuit 8 1 / n Selection Flag Register 9 1/2 Selection Flag Register 10 Microprocessor 11 Data Bus 12 Spare Line 101, 102, 104 Data signal line 103 Corrected data signal line 201, 204 Control signal line 202 1 / n switching circuit control signal line 203 1/2 Switching circuit control signal line

Claims (2)

[Claims] 1. A parity checker, a data bus, and
A data transfer processing device having a spare line, a driver / receiver, a 1 / n switching circuit, a 1/2 switching circuit, and a microprocessor, wherein a parity checker checks whether or not there is a parity error. , The data bus transfers the data and the additional pit for parity check respectively, the spare line sends data instead of when the data bus fails, and the driver / receiver sends data to the data bus. 1 / n switching circuit switches between the data bus and the spare line, and the 1/2 switching circuit switches data between the data bus and the spare line. The microprocessor checks whether the parity checker has A data transfer processing device, characterized in that it controls a switching operation between a 1 / n switching circuit and a 1/2 switching circuit depending on the presence or absence of a parity error. 2. When an error is detected by a parity checker, the microprocessor transfers data from 0 bit of data using a spare line by a 1 / n switching circuit, and data at a fixed failure position by a 1/2 switching circuit. 2. The data transfer processing device according to claim 1, wherein the data transfer processing device has a function of performing a normal data transmission by sequentially switching this operation and repeating this operation.