JPH0573348B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for selectively and self-aligningly covering electrode wiring of a semiconductor device with an insulating film. Regarding.

[Prior Art] Conventionally, a method called SELOCS is well known and used as a method for coating wiring with an insulating film in a self-aligned manner. This method uses the difference in oxidation rate between polycrystalline silicon doped with a large amount of impurities and the semiconductor substrate to perform thermal oxidation.
The wiring surface is covered with an oxide film.

[Problems to be Solved by the Invention] However, this method requires a high-temperature thermal oxidation process, is limited to cases where the wiring is made of silicon,
There are many problems, such as the fact that the resulting insulating film is an oxide film and not a phosphorous glass film, so it is susceptible to the effects of sodium and the like.

An object of the present invention is to solve the above-mentioned conventional problems, and to manufacture a semiconductor device capable of forming an insulating film with excellent characteristics in a self-aligned manner not only on wiring made of silicon but also on wiring made of materials other than silicon. The purpose is to provide a method.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses anisotropic etching to form a second insulating film on the sides of the first conductive film and the insulating film in a self-aligned manner. After forming the second
A conductive film is formed on the entire surface.

[Function] The first conductive film and the upper and side insulating films are
Since they are formed in different steps, both can be made thicker and the insulation from the second conductive film can be made sufficiently high. Further, since the second insulating film is formed in a self-aligned manner, the required area may be small.

[Example] Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a process diagram for explaining the configuration of the present invention. First, as shown in FIG. 1A, a layered pattern of electrode wiring 2a and an insulating film 3a is formed on a desired substrate 1a, and then an insulating film 3b is deposited as shown in FIG. 1B. Next, when the insulating film 3b is etched using a dry etching method with no (or less) side etching, such as a reactive sputter etching method, the etching occurs in the vertical direction (arrow Y) as shown in FIG. ) and not in the lateral direction (arrow X).
(Or progress is significantly slower than in the vertical direction)
(The dotted line C indicates the surface of the insulating film 3b before etching). Therefore, if the etching is stopped when the surface of the substrate 1a is exposed (the substrate 1a may also be etched if necessary), as shown in FIG. like,
The upper surface of the electrode wiring 2a can be selectively and self-aligned covered with the insulating film 3a and the side surface with the insulating film 3b.

In the present invention, the insulating films 3a and 3b
The electrode wiring 2a is formed using chemical vapor deposition method, physical vapor deposition method, etc.
Since desired materials such as oxides and nitrides deposited by methods other than chemical reactions can be used, the material for the electrode wiring 2a can be
In addition to materials that can form SiO ₂ films,
It has the advantage that metal or a material containing metal can be used, and the thickness of the insulating films 3a and 3b can be set without being restricted by other device dimensions. Due to these features, the present invention significantly contributes to improving the integration density, performance, and reliability of semiconductor devices, especially semiconductor integrated circuits.

Example 1 The present invention utilizes a well-known two-layer silicon gate n.
It is extremely effective when applied to the formation of interlayer insulating films for MOS memories. FIGS. 2A to 2E are process diagrams showing this embodiment. First, as shown in Figure 2A, p
A single-layer gate SiO ₂ is deposited on the active region of the type silicon substrate 1 using well-known MOS process technology.
After forming a film 21 and a single-layer gate polycrystalline silicon film 31, and further depositing a SiO ₂ film 41, which will become a part of an interlayer insulating film, by chemical vapor deposition, a parallel electrode plasma film was deposited using a photoresist film as a mask. SiO ₂ film 41 and polycrystalline silicon film 3 are etched using the etching method.
After selectively etching 1 into a desired shape, the photoresist film is removed. Next, as shown in FIG. 2B, another layer of the interlayer insulating film is formed by chemical vapor deposition.
A SiO ₂ film 42, which will become a part, is deposited on the entire surface. Afterwards, using parallel electrode plasma etching method,
The SiO ₂ film 42 is etched and further exposed.
The SiO ₂ film 21 is etched, and the etching is stopped when the surface of the silicon substrate 1 is exposed.
In this way, as shown in FIG. 2C, the single-layer gate polycrystalline silicon film 31 is selectively and self-alignedly covered with the chemical vapor deposited SiO ₂ films 41 and 42, completing the formation of the interlayer insulating film. do. next,
The silicon substrate 1 is thermally oxidized to form a two-layer gate SiO ₂ film 22 as shown in FIG. 2D. continue,
After implanting boron ions for threshold control into the surface of the substrate 1 directly under the two-layer gate SiO ₂ film 22, a two-layer gate polycrystalline silicon film 32 is deposited as shown in FIG. 2E. A source/drain, metal wiring, etc. are formed using well-known MOS process technology to complete a two-layer silicon gate n-MOS memory.

As is clear from the above embodiment, in the present invention, the interlayer insulating film (SiO ₂ films 41, 42) and the two-layer gate SiO ₂ film 22 are not formed simultaneously as in the well-known low-temperature selective oxidation method. Since each can be formed independently, the two-layer gate SiO ₂ film 22
interlayer insulating film (SiO ₂
The thickness of the films 41, 42) can be set. Therefore, for example, thin 2
When manufacturing an n-MOS memory having a layer gate SiO ₂ film 22, it is possible to maintain only the thickness of the interlayer insulating film and prevent an increase in interlayer capacitance and the list price of interlayer breakdown voltage, resulting in increased speed, manufacturing yield, and reliability. can be achieved at the same time. Furthermore, although the dielectric breakdown voltage of polycrystalline silicon oxide film is as low as 3 MV/cm,
The manufacturing process has advantages such as the dielectric strength voltage of the chemical vapor deposited SiO ₂ film being 5 MV/cm or more, and the stress in the interlayer insulating film at the edge of the single-layer crystalline silicon gate compared to the low-temperature selective oxidation method described above. This further contributes to improved retention and reliability. In the above embodiment, a PSG film (Phosphosilicate glass) may be used as the chemical vapor deposited SiO ₂ films 41 and 42.

Embodiment 2 The present invention can also be applied to the formation of self-aligned contacts, and can achieve high integration and high performance of the n-MOS memory of Embodiment 1, for example. Figure 3 A-C
is a process chart showing an example thereof. First, in accordance with Example 1, after forming the structure shown in FIG. 2E, PSG
A film 51 is deposited, and the PSG film 51 and polycrystalline silicon film 32 are etched in the same manner as in FIG. 2A (FIG. 3A). Thereafter, a high concentration arsenic implantation layer 6 is formed on the surface of the substrate 1, a PSG film 52 is deposited, and a photoresist mask 7 is formed (FIG. 3B). Next, the PSG film 52 is etched using a parallel electrode type plasma etching method, and the SiO ₂ film 22 is further etched. When the surface of the arsenic implantation layer 6 is exposed, the etching is stopped and the photoresist is etched.
When mask 7 is removed, 2
The layer gate polycrystalline silicon layer 32 is a PSG film 51,
A contact hole 8 to the arsenic implantation layer 7 is formed in a self-aligned manner while being covered with the arsenic implant layer 52 . continue,
Al electrode wiring, surface protection film, etc. are formed to obtain the desired n.
-Complete MOS memory. Although FIG. 3 shows only the memory cell portion, the self-aligned contacts of this embodiment can also be used in peripheral circuits if necessary.

[Effect of the invention] By the method shown in the above embodiment, n-MOS
Since the area of the drain diffusion layer 6 of the memory cell can be significantly reduced, it is possible to miniaturize the memory cell, and the parasitic capacitance of the data line is also significantly reduced, which also contributes to the miniaturization and reduction of parasitic capacitance of peripheral circuits. This will greatly contribute to improving integration density and performance.

Although the effects of the present invention are clear from the above examples, the method of the present invention can be used in a wider range of fields. As mentioned above, the electrode wiring 2a in FIG. 1 is made of SiO ₂ by thermal oxidation like polycrystalline silicon.
Not only materials that can form films, but also metals or materials containing metals can be used.
For example, in the embodiment shown in FIG. 2, a high fusion metal such as molybdenum or tungsten or silicide can be used in place of the two-layer gate polycrystalline silicon film 32, and as a result, the wiring resistance is reduced and further improved. It is possible to improve performance (speed up). Furthermore, it is also possible to selectively and self-align a multilayer structure such as an electrode, an insulating film, and an electrode, or to cover a convex portion of a silicon or other semiconductor substrate or a desired material with an insulating film.

Therefore, the present invention can be applied not only to MOS integrated circuits but also to bipolar integrated circuits, and can greatly contribute to higher performance and higher integration, as well as improved manufacturing yield and reliability. Furthermore, it can be applied to thin-film/thick-film integrated circuits and single devices, and its effects are remarkable.

Note that the dry etching method used in the present invention is not limited to the parallel electrode type plasma etching method, but also includes other plasma etching methods, sputter etching method, ion etching method, and other methods that do not have side etching ( or less)
Any desired method may be used. It goes without saying that desired treatments such as cleaning, impurity doping heat treatment, etching, etc. may be carried out without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for explaining the configuration of the present invention, and FIGS. 2 and 3 are process diagrams showing different embodiments of the present invention, respectively. 1a, 1...Substrate, 2a, 31... Wiring (polycrystalline silicon), 3a, 3b, 41, 42... Insulator.

Claims (1)

[Claims] 1. Forming a laminated film consisting of a first gate electrode and a second insulating film having a predetermined shape on a first insulating film formed on a semiconductor substrate, and forming a third insulating film on the entire surface. After that, the third insulating film is anisotropically etched to leave a portion of the third insulating film formed on the side of the laminated film and remove the other portion. forming a fourth insulating film on the exposed portion of the semiconductor substrate; and forming a second gate electrode having a predetermined shape extending from the second insulating film onto the fourth insulating film. A method of manufacturing a semiconductor device, the method comprising at least the step of forming a semiconductor device.