JPH0573350A - Microprocessor containing secondary input/output terminal - Google Patents

Abstract

PURPOSE:To omit the need of the loading of an IC socket for debugging, etc. CONSTITUTION:The signals of low levels are inputted to the terminals 5 and 7 together with no connection of a terminal 6. Under such conditions, the input/ output terminal of a microprocessor chip 10 is connected to a secondary input/ output terminal 4 via a buffer 3. That is, the signals of low levels are inputted to the buffers 101, 102, 201 and 202 respectively. Thus these buffers become inconductive and the output of a gate 71 has a high level. Then the output of a gate 72 or 74 is set at a high level by a signal 8. Therefore, a buffer 301 or 302 conducts and the terminal 4 can have a direct access to the chip 10. When the signals of low levels are inputted to the terminals 5 and 6 with no connection of the terminal 7, a main input/output terminal 9 is connected to the terminal 4 via a buffer 2. Then the terminal 4 can have direct access to an electronic circuit 11.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to microprocessors.

[0002]

2. Description of the Related Art Conventionally, in an electronic circuit in which a microprocessor is mounted, the microprocessor is attached via an IC socket or the like. Then, by replacing the microprocessor with a debugging tool such as an in-circuit emulator, if necessary, debugging of the micro program that drives the microprocessor, monitoring of microprocessor operation for adjustment and inspection of electronic circuits, Direct access to the peripheral circuits of the microprocessor is performed.

[0003]

That is, since the conventional microprocessor has only one input / output terminal for one signal, in order to perform the above-mentioned debugging, the microprocessor must be an IC. It is necessary to mount it with a socket. However, the use of such an IC socket causes problems such as a decrease in reliability due to an increase in electrical contacts, an increase in cost, and an increase in man-hours due to replacement with a debug tool. Further, when the debugging is performed by replacing the debugging tool with the debugging tool, the microprocessor is not mounted after that. Therefore, if there is a failure in the microprocessor, there is a problem that the discovery is delayed.

An object of the present invention is to solve such problems and to provide a microprocessor having a sub input / output terminal which does not need to be mounted using an IC socket for debugging or the like.

[0005]

According to the present invention, in a microprocessor having a microprocessor chip incorporated in a predetermined package, main input / output terminals respectively corresponding to the input / output terminals of the microprocessor chip are provided. And sub-input / output terminals respectively corresponding to the input / output terminals of the microprocessor chip, and the first control signal controls the signal transmission direction and whether or not the signal is transmitted. A first direction control buffer connecting an input / output terminal of the chip and the main input / output terminal; and a second control signal for controlling the signal transmission direction and whether or not the signal is transmitted. A second direction control buffer connecting the input / output terminal and the sub input / output terminal;
A third control signal controls the signal transmission direction and whether or not to transmit the signal, and connects the input / output terminal of the microprocessor chip to the sub input / output terminal.
Direction control buffer, a first control terminal corresponding to the first direction control buffer, a second control terminal corresponding to the second direction control buffer, and a third direction control buffer. Based on a third control terminal, a first control circuit that generates the first control signal based on a signal input from the first control terminal, and a signal input from the second control terminal. A second control circuit for generating the second control signal, and a third control circuit for generating the third control signal based on a signal input from the third control terminal. Is characterized by.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a microprocessor having a sub input / output terminal according to the present invention. The microprocessor 12 includes a microprocessor chip 10 and
A main input / output terminal 9 and a sub input / output terminal 4
The input / output terminal of the processor chip 10 is connected to the main input / output terminal 9 by the direction control buffer 1 and is connected to the sub input / output terminal 4 by the direction control buffer 3. The main input / output terminal 9 and the sub input / output terminal 4 are connected by the direction control buffer 2. micro·
The processor 12 also includes sub input / output control terminals 5 to 7 corresponding to the direction control buffers 1 to 3, respectively.

The terminal 5 is connected to one input terminal of the inverting gates 51 and 52, the output terminal of the gate 51 is connected to the control terminal of the buffer 101 constituting the direction control buffer 1, and the output terminal of the gate 52 is direction control. It is connected to the control terminal of the buffer 102 that constitutes the buffer 1.

The terminal 6 is connected to the input terminal of the inverting gate 61, and the output terminal of the gate 61 is AND gates 62 and 64.
Connected to one of the input terminals. The output terminal of the gate 62 is connected to the control terminal of the buffer 201 forming the direction control buffer 2, and the output terminal of the gate 64 is connected to the control terminal of the buffer 202 forming the direction control buffer 2.

The terminal 7 is connected to the input terminal of the inverting gate 71, and the output terminal of the gate 71 is AND gates 72 and 74.
Connected to one of the input terminals. The output terminal of the gate 72 is connected to the control terminal of the buffer 301 forming the direction control buffer 3, and the output terminal of the gate 74 is connected to the control terminal of the buffer 302 forming the direction control buffer 3.

Reference numeral 8 is a signal for controlling the signal transmission direction of each of the buffers 1 to 3, which is directly input to the other input terminal of each of the gates 51, 62 and 72, and the inverting gates 53, 63 and 73 through gates 52, 64,
It is input to the other input terminal of 74, respectively.

Pull-up resistors are connected to the terminals 4 to 7, and the potentials of the terminals are kept at a high level when these terminals are not connected in the normal operating state of the microprocessor. Reference numeral 11 denotes an electronic circuit in which the microprocessor 12 is mounted, and the microprocessor 12 is connected to the electronic circuit 11 through the main input / output terminal 9.
It should be noted that although the figure shows a portion related to one input / output terminal of the microprocessor chip 10, in actuality, a direction control buffer, a main input / output terminal, and a sub input / output terminal are provided for each main input / output terminal. Is provided.

Next, the operation will be described. In a normal operating state, all terminals 4, 5, 6, 7 are unconnected. At this time, the outputs of the gates 72 and 74 are fixed to the low level, so that the buffer 3 becomes non-conductive, and the gates 62 and 64
Since the output of is also fixed to the low level, the buffer 2 also becomes non-conductive. Since one of the inputs of the gates 51 and 52 is at the high level, when the signal 8 is at the high level, the output of the gate 51 is at the high level and the buffer 101 becomes conductive, while the signal 8 is at the low level. At this time, the output of the gate 52 becomes high level and the buffer 102 becomes conductive. That is, in this case, the chip 10 and the main input / output terminal 9 are connected through the buffer 1.

Input a low level signal to terminals 5 and 7,
When the terminal 6 is not connected, the chip 10 and the sub input / output terminal 4 are connected through the buffer 3. That is,
Low-level signals are input to the control terminals of the buffers 101, 102, 201, and 202, so that these buffers become non-conductive, while the output of the gate 71 becomes high-level. Output is signal 8
One of them becomes high level. Therefore, one of the buffers 301 and 302 becomes conductive. In this state, the microprocessor chip 10 can be directly accessed from the terminal 4.

Input a low level signal to terminals 5 and 6,
When the terminal 7 is not connected, the main input / output terminal 9 and the sub input / output terminal 4 are connected through the buffer 2. In this case, the buffers 1 and 3 are rendered non-conductive, and one of the buffers 201 and 202 forming the buffer 2 is rendered conductive in accordance with the logic level of the signal 8. In this state, the electronic circuit 11 can be directly accessed from the sub input / output terminal 4, and a predetermined control circuit can be connected to the terminal 4 to access the electronic circuit 11 for adjustment and inspection.

When a low-level signal is input to the terminals 6 and 7 and the terminal 5 is left unconnected, the microprocessor chip 10 is connected to the main input / output terminal 9 through the buffer 1 and is normally connected. The terminal 4 is connected to the input / output terminal of the microprocessor chip 10 and the main input / output terminal 9 through the buffers 2 and 3,
Through this, it becomes possible to monitor the operating state of the microprocessor.

FIG. 2 shows the microprocessor 12 incorporated in a PGA type microprocessor package. The terminals 21 provided on the lower surface of the package are main input / output terminals such as the terminals 9, and the terminals 20 provided on the upper surface of the package are sub input / output terminals such as the terminals 4 to 7 and sub input / output control terminals. By providing the sub input / output terminal and the sub input / output control terminal on the upper surface of the package as described above, connection to these terminals becomes easy in a state where the microprocessor is mounted on the electronic circuit. In addition,
It is also effective to provide the sub input / output terminal and the sub input / output control terminal on the side portion of the package, and in that case, the same effect can be obtained.

[0017]

As described above, according to the present invention,
In the processor, a micro
It is provided with sub-input / output terminals connected to the input / output terminals and main input / output terminals of the processor chip, through which the microprocessor chip or the electronic circuit in which the microprocessor is mounted can be directly accessed. Therefore, it is not necessary to replace the microprocessor with a debug tool such as an in-circuit emulator for debugging or the like, and therefore it is not necessary to mount the microprocessor through the IC socket. Therefore, the IC socket is not necessary, and it is possible to solve all the problems such as the decrease in reliability due to the increase in electrical contacts, the increase in cost, and the increase in man-hours due to the replacement with the debug tool. It also solves the problem of delaying the failure detection of the microprocessor.

[Brief description of drawings]

FIG. 1 is a diagram showing a micro-device having a sub input / output terminal according to the present invention.
It is a circuit diagram which shows an example of a processor.

FIG. 2 FIG. 1 incorporated into a PGA type package.
3 is an external view showing the microprocessor of FIG.

[Explanation of symbols]

1-3 Direction control buffer 4 Sub input / output terminal 5-7 Sub input / output control terminal 9 Main input / output terminal 10 Microprocessor chip 11 Electronic circuit 20,21 Terminal 51,52,62,64,72,74 AND gate 53, 63, 71, 73 Inversion gate 101, 102, 201, 202, 301, 302 Buffer

Claims (3)

[Claims] 1. A microprocessor comprising a microprocessor chip incorporated in a predetermined package, wherein main input / output terminals respectively corresponding to the input / output terminals of the microprocessor chip, and the microprocessor chip. Sub-input / output terminals respectively corresponding to the input / output terminals, and the first control signal controls the signal transmission direction and whether or not the signal is transmitted. First to connect with main input / output terminals
Direction control buffer for controlling the signal transmission direction and whether the signal is transmitted or not, and a second direction control for connecting the main input / output terminal and the sub input / output terminal. A buffer and a third control signal control a signal transmission direction and whether or not the signal is transmitted, and connect the input / output terminal of the microprocessor chip and the sub input / output terminal to each other.
Direction control buffer, a first control terminal corresponding to the first direction control buffer, a second control terminal corresponding to the second direction control buffer, and a third direction control buffer. Based on a third control terminal, a first control circuit that generates the first control signal based on a signal input from the first control terminal, and a signal input from the second control terminal A second control circuit for generating the second control signal, and a third control circuit for generating the third control signal based on a signal input from the third control terminal. And a microprocessor having a sub-input / output terminal. 2. The micro-device having a sub-input / output terminal according to claim 1, wherein the sub-input / output terminal and the first to third control terminals are arranged on an upper surface of the package. Processor. 3. The micro with sub-input / output terminal according to claim 1, wherein the sub-input / output terminal and the first to third control terminals are arranged on a side portion of the package. -Processor.