JPH0573360A - Watchdog timer - Google Patents

Abstract

PURPOSE:To improve the reliability for the fault detecting operations of a watchdog timer which detects the fault detecting operations of a microcomputer. CONSTITUTION:A means containing a switching circuit 108 is provided to input an external clock phiO which is never affected by a system clock phiI of a microcomputer 103 as a count clock phiW to be applied to a counter 104. Thus a watchdog timer 101 can carry out the normal operation even if the microcomputer 103 has a fault owing to its clock phiI. Thus the reliability is improved to the fault detecting operations of the timer 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer, and more particularly to a watchdog timer for a microcomputer.
The present invention relates to a counter operation clock circuit of a timer.

[0002]

2. Description of the Related Art In a microcomputer, as means for detecting program runaway or system abnormality,
A watchdog timer is used.

This watchdog timer is a function for detecting runaway or deadlock of a program. A program is designed by inserting an instruction to clear the watchdog timer for each module of the program, and a watchdog When a timer interrupt occurs, it detects that a program or system is operating abnormally.

A conventional microcomputer including this type of watchdog timer has a structure as shown in FIG. 5, and includes a watchdog timer 501, an oscillation circuit (hereinafter referred to as OSC) 102, and a central processing unit ( Below CP
U) 103, internal oscillation control terminals X1 and X2, and external output terminal WDTO. The watchdog timer 501 includes a timer counter 104, an AND logic gate 105, an OR logic gate 106, and a mode register 10.
It is composed of 7.

As shown in FIG. 2, the OSC 102 has inverters 30 and 31 and a resistor 32. By connecting a crystal oscillator 201 to internal oscillation control terminals X1 and X2, terminals OS1 and X2 are connected. Internal system clock φI according to the input signal Are being created. C
The PU 103 operates by the internal system clock φ _I output from the OSC 102, and sends the clear signal CL of the timer counter 104 to the watchdog timer 501.
It outputs R and an operation set signal RUN that permits the operation of the watchdog timer 501.

Next, the internal operation of the watchdog timer 501 will be described. The timer counter 104 is the internal system clock signal φI of the microcomputer.
By the clear signal CLR or the watchdog timer 50, which is counted up by the CPU 103 and output from the CPU 103.
Although it is cleared by the operation set signal RUN which permits the operation of No. 1, when the clear operation by the clear signal CLR or the operation set signal RUN is not performed until the count-up and overflow, the overflow signal O
Output VF.

The mode register 107 is composed of a flip-flop circuit and is reset by a system reset signal RESET in the microcomputer, and the CPU 10
It is set by the operation set signal RUN output from the device 3. When the mode register 107 is set, the timer counter 10 is activated by the data output of the mode register 107.
4 overflow signal OVF to external output terminal WDTO
By outputting to, the program or system abnormality is output to the outside.

[0008]

The above-mentioned conventional watchdog timer 501 detects a program runaway or deadlock, but the program runaway or deadlock may be caused by an abnormality in the internal system clock. .. As described above, when the abnormal operation of the program is caused by the internal system clock, the operation of the watchdog timer 501 may be abnormal, and the abnormal operation of the microcomputer is accurately detected. There was a problem that it did not exist.

The object of the present invention is to solve the conventional problems,
It is to provide a watchdog timer that ensures high reliability for operation.

[0010]

SUMMARY OF THE INVENTION According to the structure of the present invention, in a watchdog timer of a microcomputer that uses an oscillation output of an oscillator as an operation clock, a counter that counts a periodic signal and is cleared by an input signal, and a set / reset A logic circuit which incorporates a flip-flop circuit capable of inputting an output signal of the flip-flop circuit and an overflow signal of the counter, and the counter is externally different from the timing signal generated from the oscillation output of the oscillator. It is characterized by comprising means for operating with the periodic input signal of.

[0011]

1 is a block diagram showing a watchdog timer according to a first embodiment of the present invention.

Referring to FIG. 1, the microcomputer of this embodiment comprises a watchdog timer 101 and an OSC 10.
2, CPU 103, internal oscillation control terminals X1 and X2, external clock input terminal CKIN, and external output terminal WDTO.

Here, the watchdog timer 101
Is a timer counter 104, an AND logic gate 10
5, an OR logic gate 106, a mode register 107, and an operation clock switching circuit 108.

The OSC 102 has a structure as shown in FIG. 2, and by connecting the crystal oscillator 201 to the internal oscillation control terminals X1 and X2, the internal system clock φ _{I is} generated according to the signals input from the terminals X1 and X2. Are being created. The CPU 103 operates by the internal system clock φ _I output from the OSC 102,
To the timer 101, the clear signal CLR of the timer counter 104, the operation set signal RUN that permits the operation of the watchdog timer 101, and the clock switching signal 110 are output.

Next, the internal operation of the watchdog timer 101 will be described. The timer counter 104 is counted up by the watchdog timer internal clock signal φ _w , and is cleared by the clear signal CLR output from the CPU 103 or the operation set signal RUN which permits the operation of the watchdog timer 101, but it is counted up. When the clear operation by the clear signal CLR or the operation set signal RUN is not performed until the overflow, the overflow signal OVF is output.

The mode register 107 is composed of a flip-flop circuit and is reset by a system reset signal RESET in the microcomputer, and the CPU 1
It is set by the operation set signal RUN output from 03. When the mode register 107 is set, the overflow signal OVF of the timer counter 104 is output to the external output terminal W by the data output of the mode register 107.
By outputting to the DTO, a program or system abnormality is output to the outside.

The watchdog timer 101 operates in accordance with the timing of the watchdog timer internal clock signal φ _w , and the watchdog timer internal clock signal φ _w is output by the operation clock switching circuit 108. The operation clock switching circuit 108 uses the external clock φ _o input from the external clock input terminal CKIN.
And internal system clock in microcomputer φ _I
Is inputted to output a watchdog timer internal clock signal φ _w , which is a switch circuit as shown in FIG.

This switch circuit uses the clock switching signal 110 output from the CPU 103 to set the watchdog timer internal clock signal φ _w to the external clock φ _o input from the external clock input terminal CKIN.
The internal system clock φ _I in the microcomputer can be selected to be selected.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

In FIG. 4, the present microcomputer comprises a watchdog timer 401, OSC 102, C
It is configured to include a PU 103, internal oscillation control terminals X1 and X2, and an external output terminal WDTO.

The watchdog timer 101 has a timer counter 104, an AND logic gate 105, an OR logic gate 106, a mode register 107, and an operation clock switching circuit 108. Hereinafter, description of the same parts as those shown in the first embodiment will be omitted.

Watchdog timer 401 of this embodiment
Is the internal system clock φ in the microcomputer
_I is set as the watchdog timer internal clock φ _w , or the input signal of the internal oscillation control terminal X1 is set as the watchdog timer internal clock signal φ _w.
It is configured to select whether to operate the timer.

[0023]

As described above, the configuration of the watchdog timer of the present invention is different from that of the other parts inside the microcomputer due to the more reliable operation clock different from the system clock inside the microcomputer. By having a means to operate completely separately, it becomes possible for the watchdog timer to operate without being affected by the operation of parts other than the watchdog timer in the microcomputer at all. The reliability with respect to the detection of abnormalities and the like is improved, and it is possible to have higher reliability than ever.

[Brief description of drawings]

FIG. 1 is a block diagram showing a watchdog timer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the oscillator circuit of FIG.

FIG. 3 is a circuit diagram showing a switching circuit of FIG.

FIG. 4 is a block diagram showing a watchdog timer according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional microcomputer.

[Explanation of symbols]

101 watchdog timer 102 oscillator circuit 103 CPU 104 timer counter 105 AND logic gate 106 OR logic gate 107 operation mode register 108 switching circuit φ _I , φ _o , φ _w clock signal CLR watchdog timer clear signal RUN watchdog timer Operation set signal RESET System reset signal WDTO External output terminal X1, X2 Internal oscillation control terminal CKIN External clock input terminal

Claims (1)

[Claims] 1. A watchdog timer of a microcomputer using an oscillation output of an oscillator as an operation clock, comprising a counter that counts a periodic signal and is cleared by an input signal, and a flip-flop circuit that can be set and reset. A logic circuit that receives the output signal of the flip-flop circuit and the overflow signal of the counter is provided, and the counter operates by means of an external periodic input signal different from the timing signal created from the oscillation output of the oscillator. A watchdog timer characterized by being provided.