JPH057338A - Video image processor - Google Patents

Abstract

PURPOSE:To offer a video display device which has a title inserting function but can save power consumption. CONSTITUTION:On the reception of a command from a microprocessor, an MPU interface 92 generates and holds a stop signal S. This signal S is outputted to a memory control circuit 91, an oscillation circuit 96, a horizontal address counter circuit 93, and a vertical address counter circuit 94. Each circuit is stopped by this signal S, and the power consumption is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing device, and more particularly to a video processing device such as an integrated video camera for synthesizing and recording (monitoring and displaying) a title image on a general image.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram centering on a title control circuit 88 of an integrated video camera 10 as a specific example of a video processing apparatus. As the method of combining the title image 50 with the general image 60 in the video camera 10, two types of methods are mainly put into practical use. In the first method, the image 60 is recorded on the video tape by the recording circuit 20, the video tape is rewound and reproduced, the title image 50 is photographed while confirming the reproduced image of the image 60, and the image 6 is reproduced.
The title image 50 is combined with 0. This method has the advantage that you can superimpose and edit the appropriate title image at any time after you have shot and checked the recorded content, but at the moment it is expensive, so for enthusiasts Limited to the device.

In the second method, first, the title image 50 is photographed, digitized as a still image, and then the SRAM 30 is temporarily stored.
When the image 60 is photographed, the title image stored in the SRAM 30 is read out and superposed on the image 60 and recorded. Although this method is less expensive to edit but less expensive, it is becoming popular in almost all devices for general users. Therefore, the following description will be given by taking a video camera adopting the second method as a specific example. This video camera 1
0 has a title control circuit 88. Around this circuit 88, a microprocessor 40 for monitoring and controlling the entire video camera, an SRAM for storing a title image 50, and a video image by combining the title image 50 with the image 60 It has a recording circuit 20 for recording on a tape.

First, referring to the block diagram of FIG. 4, the operation of storing the title image 50 in the SRAM 30 will be described. The title image 50 is taken by an imaging unit (not shown) of the video camera 10, converted into digital information, and sent to the title control circuit 88 as a title input signal I. Therefore, the title control circuit 88 receives an instruction according to the MPU signal B from the microprocessor 40 according to the operation of the photographer, generates the address signal A and the data signal D from the title input signal I, and uses the memory control signal M. The SRAM 30 is controlled and the title image 50 is stored in the SRAM 30. In this way, the title image 50 is S
By storing it in the RAM, the title can be inserted at any time thereafter.

Next, while the image 60 is being photographed, the title image 5
The operation for superimposing 0 will be described. When the photographer presses the title insertion switch while a signal (not shown) of the image 60 is sent to the recording circuit 20 and recorded on the video tape, the microprocessor 40 responds to this operation by the title insertion switch. Image reading instruction is MP
Output as U signal B. In response to this instruction, the title control circuit 88 synchronizes with the signal of photographing the image 60,
The address signal A is generated and S is generated by the memory control signal M.
The RAM 30 is controlled, the data of the title image 50 stored in the SRAM 30 is read from the SRAM 30 as a data signal D, and the title output signal G restored and generated from this data is sent to the recording circuit 20. In response to this, the recording circuit 20 synthesizes this signal G with the signal of the image 60 and records it on the video tape.

FIG. 3 is a block diagram showing the configuration of the title control circuit 88. The title control circuit includes an oscillation circuit 86, a memory control circuit 81, an MPU signal buffer 82, a horizontal address counter circuit 83, and a vertical address counter circuit 84. The oscillator circuit 86 is
It is composed of capacitors C1 and C2, a coil L1, and a NOT gate (NAND gate of the same signal input in the figure) 85, and generates a dot clock C for determining the scanning timing in the horizontal direction.

The horizontal address counter circuit 83 is shown in FIG.
As shown in detail in (b), it has a counter 83a, receives the horizontal synchronizing signal H included in the title input signal I at the reset signal input terminal RST of the counter 83a, and receives the dot clock C as the clock of the counter 83a. The signal is received by the signal input terminal CLK, the counting is started in synchronization with the horizontal synchronizing signal H, and the subsequent dot clock C is counted to generate the horizontal address Q forming a part of the address signal A. As shown in detail in FIG. 2B, the vertical address counter circuit 84 has a counter 84a, and counters the vertical synchronizing signal V included in the title input signal I.
The reset signal input terminal RST of a receives the horizontal synchronizing signal H at the clock signal input terminal CLK of the counter 84a, the counting is started in synchronization with the vertical synchronizing signal V, and the horizontal synchronizing signal H after that is counted, Generate a vertical address P. The address signal A composed of the vertical address P and the horizontal address Q is output to the SRAM 30, and the SRAM 30 receives the address signal A.
A storage area in 30 to be accessed is designated.

The MPU signal buffer 82 receives the MPU signal B from the microprocessor 40, regenerates it for noise reduction and drive capability addition, and sends it as a titler control signal E to the memory control circuit 81. . By thus passing through the MPU signal buffer 82, the microprocessor 40 causes the title control circuit 88 to store the title image 50 in the SRAM 30 and the SRAM.
It is possible to instruct to read from 30.

The memory control circuit 81 receives the horizontal address Q and the vertical synchronizing signal V and the horizontal synchronizing signal H included in the title input signal I and determines its own operation timing. Then, upon receiving the titler control signal E, this signal E
If the instruction from the microprocessor 40 via the is to store the title image 50 in the SRAM 30, the title image signal T included in the title input signal I is input,
This signal T is converted into data of a form suitable for the SRAM 30 and outputted as a data signal D, and the memory 30 is controlled by the memory control signal M to store the data of the title picture 50. If the instruction from the microprocessor 40 via the signal E is to read the title image 50 from the SRAM 30, the SRAM 30 is controlled by the memory control signal M, and the stored data of the title image 50 is read as the data signal D. put out. From the read signal, the data of the title image 50 is converted into data of a shape suitable for the recording circuit 20, and a title output signal G is generated and output. Here, the title output signal G includes pattern information of the title image 50, color information associated with the pattern information, and a framing pattern for the pattern of the title image 50.
The vertical address P and the horizontal address Q are generated in synchronism with the vertical synchronizing signal V and the horizontal synchronizing signal H of the signal obtained by capturing the image 60, and the SRAM 30 is accessed using these addresses, so that the title image 50 is an image. The data is sent to the recording circuit 20 in synchronism with 60, and is combined and recorded on a video tape.

As described above, the data signal D may be sent from the SRAM 30 to the memory control circuit 81, as opposed to the case where data is sent from the memory control circuit 81 to the SRAM 30, and both the memory control circuit 81 and the SRAM 30. Since it is driven, it is driven by a three-state (tri-state) buffer and receives a signal drive current from the power supply Vcc through the pull-up resistor R.

[0011]

As described above, in video cameras and the like, a title image inserting function for superimposing a title image on a general image is rapidly spreading. On the other hand, in a device that uses a battery as a supply source of driving power, such as an integrated video camera,
It is important to reduce the power consumption in the circuit in order to effectively use the limited power. However, it is reasonable that power consumption increases if a circuit is added for a new function, and it is difficult to achieve both function addition and low power consumption. Further, there is a problem that if a part of the circuit is changed for a new function, the circuit wiring board is also changed. An object of the present invention is to solve the above-mentioned problems of the prior art, and the power consumption hardly increases even if a title control circuit and an SRAM etc. having a title image inserting function are added to the circuit. In addition, the present invention provides a video processing device having a circuit capable of expanding functions without changing the wiring board.

[0012]

In order to achieve this object, the structure of the image display device of the present invention is such that the signal from the microprocessor is replaced by an MPU signal buffer.
The interface receives and the MPU interface sends a stop signal to the memory control circuit of the title control circuit, the oscillation circuit, the horizontal address counter circuit, and the vertical address counter circuit. The MPU interface of the present invention receives a command in accordance with the MPU signal from the microprocessor, generates a control signal necessary in the title control circuit from the command and holds it, and sends it to each circuit in the title control circuit on behalf of the microprocessor. It is what is output. As one of these signals, instead of sending a stop signal directly to each circuit from the microprocessor by generating and holding the stop signal, the held stop signal is stored in the memory control circuit of the title control circuit, the oscillation circuit, or the horizontal circuit. It is sent to the address counter circuit and vertical address counter circuit.

The memory control circuit receives the stop signal, and when the stop signal is significant, puts the data signal in the output state, controls the SRAM by the memory control signal, and puts the state of the SRAM in the standby mode. The oscillation circuit uses a NAND gate instead of a NOT gate, and the first input terminal of this NAND gate is connected to the terminal of the passive element to form a loop required for oscillation. Then, the second input terminal receives the stop signal, and the dot clock is transmitted from the output terminal. The vertical address counter circuit receives the horizontal synchronizing signal at the clock input terminal and receives the logical sum of the vertical synchronizing signal and the stop signal instead of directly receiving the vertical synchronizing signal at the reset input terminal and outputs the counter value to the vertical address. Output as. The horizontal address counter circuit
The clock input terminal receives the dot clock, the reset input terminal does not receive the horizontal synchronizing signal directly, but receives the logical sum of the horizontal synchronizing signal and the stop signal and outputs the counter value as a horizontal address. The MPU
The interface, the memory control circuit, the gate element of the oscillation circuit, the horizontal address counter circuit, and the vertical address counter circuit are all integrated in one IC (title control IC).

[0014]

According to the above-mentioned structure, it is shown below that even when the apparatus is in operation, when the title insertion function is not used, the circuit which performs this function consumes almost no power. Memory control circuit and SRAM controlled thereby
In SRA, when the title insertion function is not used,
Since the data of M is not required, when the significant stop signal is received, the memory control circuit controls the SRAM via the chip select included in the memory control signal to put the state of the SRAM in the standby mode. Then, general-purpose CMO
Taking the SRAM of S as an example, the power consumption of 50 mA during operation can be reduced to 20 μA. Further, at this time, by setting the memory control circuit to output the data signal, the signal line of the data signal is always driven by the memory control circuit or the SRAM. As a result, the data signal line will not be in an open state, noise will be picked up by the open state, and there is no danger of the SRAM being destroyed by this noise. Therefore, the pull-up resistor R can be omitted, and the power consumed by this resistor can be saved. Moreover, since the number of elements is reduced, the cost is also reduced.

In the oscillator circuit, a NAND gate is used in the signal loop required for oscillation, and the first NAND gate is used.
The signal forming the signal loop is received at the input terminal of
Although the stop signal is received at the second input terminal of the AND gate, when the stop signal is not significant, oscillation is performed as usual and a dot clock is generated. However, when the stop signal received at the second input terminal of the NAND gate is significant, NA
The output value of the ND gate is fixed. Therefore, the oscillation is stopped, and the power consumed by the NAND gate and the parasitic resistance in the oscillation circuit can be saved.

In the vertical address counter circuit and the horizontal address counter circuit, the reset input terminal of the counter in the circuit receives the logical sum of the stop signal and the other signal, so that the stop signal is not significant. , The counter remains reset and does not count. Therefore, if the circuit is configured mainly by using the CMOS element that consumes power only at the time of switching, the switching is not performed during the operation stop due to the stop signal, so that the power is hardly consumed.

Further, the stop signal is sent to, for example, the title control I.
There is also a method in which the microprocessor directly outputs a reset signal to C to control the title control circuit to realize the power saving as described above, but it is necessary to change the wiring board of the entire circuit. Not preferable. On the other hand, in the present invention, the MPU interface receives a command from the microprocessor and sends a stop signal on behalf of the microprocessor. In this way, when a circuit having a title insertion function is configured by using an IC-based title control circuit by using an external instruction as a command, even if the title control circuit is changed, the function may be expanded. The circuit can be changed only by changing the inside of the title control IC, and it can be handled by an IC having compatibility such as pin arrangement. Therefore, by only changing the software and replacing the IC, it is possible to easily realize a device capable of coping with functional expansion such as improvement of the present invention for saving power consumption without changing the wiring board of the entire circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. 1 is a block diagram of a title control circuit 99 of an embodiment of a video processing apparatus of the present invention, which corresponds to FIG. 3 showing a conventional example. The title control circuit 99 includes an oscillation circuit 96, a memory control circuit 91, an MPU interface 92, a horizontal address counter circuit 93, and a vertical address counter circuit 94. The passive element C of the oscillation circuit 96 is included in the title control circuit 99.
It is integrated as the title control IC 90 except for the portion constituted by 1, C2 and L1. Oscillation circuit 96
Is composed of capacitors C1 and C2, a coil L1 and a NAND gate 95, and generates a dot clock C for determining the scanning timing in the horizontal direction. A stop signal S is connected to one of the input terminals of the NAND gate 95, and the signal S can stop the oscillation.

The vertical address counter circuit 93 (horizontal address counter circuit 94) is different from the conventional example shown in FIG. 2B, as shown in FIG.
The reset signal input terminal RST of (94a) is configured to receive the output of the negative logic OR gate 96 which receives the vertical synchronizing signal V (horizontal synchronizing signal H) and the stop signal S as inputs. By using such a configuration, when the value "L" is received from the negative logic stop signal S, the counter 93a (9
4a) stops operating, and the power consumption of the counter 93a (94a) is saved.

The MPU interface 92 is a circuit composed of a bus receiver, a bus driver, an address decoder, a latch, a register, etc., and receives a command according to the MPU signal B from the microprocessor 40 and sends it to the memory control circuit 81. In addition to generating the control signal E, the stop signal S is generated and held, and this signal S is output to the memory control circuit 91, the oscillation circuit 96, the horizontal address counter circuit 93, and the vertical address counter circuit 94.
This signal S puts each circuit in a state of saving power consumption.

The memory control circuit 91 finely drives the data signal D to eliminate the timing at which neither the memory control circuit 91 nor the SRAM 30 drives the data signal D. Therefore, in the circuit configuration of the present invention of FIG. 3, the pull-up resistor R for protecting the SRAM from noise is omitted, which also saves power consumption.

[0022]

As described above, according to the present invention, it is possible to easily deal with the function expansion of the title control circuit and display the title only by changing the local circuit (in the IC) and the program. When not doing, there is no increase in power consumption compared to before with the title insertion function,
There is an effect that a video display device having a title insertion function can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a title control circuit in an embodiment of a video processing device of the present invention.

FIG. 2A is a diagram around a counter of the vertical (horizontal) address counter circuit of the present invention. (B) is a diagram around a counter of a vertical (horizontal) address counter circuit having a conventional configuration.

FIG. 3 is a block diagram of a title control circuit having a conventional configuration.

FIG. 4 is a block diagram centering on a title control circuit of a video camera which is a video processing device.

[Explanation of symbols]

10 video cameras 20 recording circuit 30 SRAM 40 microprocessors 50 title pictures 60 images 81 Memory control IC 82 MPU signal buffer 83 Horizontal address counter circuit 84 Vertical Address Counter Circuit 85 NOT gate 86 oscillator 88 title control circuit 90 Title control IC 91 Memory control IC 92 MPU interface 93 Horizontal address counter circuit 94 Vertical Address Counter Circuit 95 NAND gate 96 oscillator circuit 99 title control circuit

Claims (4)

[Claims] 1. An oscillation circuit for generating a dot clock that determines timing in the horizontal direction, a horizontal address counter circuit that is initialized by receiving a horizontal synchronization signal, counts the dot clock, and generates a horizontal address, and a vertical synchronization. A vertical address counter circuit, which is initialized by receiving a signal, counts the horizontal synchronizing signal and generates a vertical address, receives an address signal composed of the vertical address and the horizontal address, and outputs digital value title image data. When a control signal is received from the SRAM to be held and the microprocessor and the control signal is writing, the data of the title image is input, the data signal corresponding to the SRAM is output to the SRAM, and the SRAM is controlled. Then, the data is stored in the address indicated by the address signal, and the control is performed. And a memory control circuit that controls the SRAM to read the data held in the SRAM, restore the title image data, and output the read image data. When the stop signal is received from the microprocessor, the data signal is set to the output state, and the SRA
An image processing device characterized by controlling M to put the SRAM in a standby mode. 2. An oscillation circuit for generating a dot clock that determines timing in the horizontal direction, a horizontal address counter circuit that is initialized by receiving a horizontal synchronization signal, counts the dot clock, and generates a horizontal address, and a vertical synchronization. A vertical address counter circuit, which is initialized by receiving a signal, counts the horizontal synchronizing signal and generates a vertical address, receives an address signal composed of the vertical address and the horizontal address, and outputs digital value title image data. When a control signal is received from the SRAM to be held and the microprocessor and the control signal is writing, the data of the title image is input, the data signal corresponding to the SRAM is output to the SRAM, and the SRAM is controlled. Then, the data is stored in the address indicated by the address signal, and the control is performed. And a memory control circuit for controlling the SRAM to read the data held in the SRAM, restore the title image data, and output the read image data. An image processing device characterized by stopping oscillation when receiving a stop signal from a processor. 3. An oscillation circuit for generating a dot clock that determines timing in the horizontal direction, a horizontal address counter circuit that is initialized by receiving a horizontal synchronization signal, counts the dot clock, and generates a horizontal address, and a vertical synchronization. A vertical address counter circuit, which is initialized by receiving a signal, counts the horizontal synchronizing signal and generates a vertical address, receives an address signal composed of the vertical address and the horizontal address, and outputs digital value title image data. When a control signal is received from the SRAM to be held and the microprocessor and the control signal is writing, the data of the title image is input, the data signal corresponding to the SRAM is output to the SRAM, and the SRAM is controlled. Then, the data is stored in the address indicated by the address signal, and the control is performed. In the video processing device, the horizontal address counter circuit and the memory control circuit for controlling the SRAM to read the data held in the SRAM, restore the data of the title image, and output the data. A video processing device, wherein either one of the vertical address counter circuits resets a counter of its own circuit when receiving a stop signal from the microprocessor. 4. An oscillator circuit for generating a dot clock that determines timing in the horizontal direction, a horizontal address counter circuit that is initialized by receiving a horizontal synchronizing signal, counts the dot clock, and generates a horizontal address, and a vertical synchronizing circuit. A vertical address counter circuit, which is initialized by receiving a signal, counts the horizontal synchronizing signal and generates a vertical address, receives an address signal composed of the vertical address and the horizontal address, and outputs digital value title image data. When a control signal is received from the SRAM to be held and the microprocessor and the control signal is writing, the data of the title image is input, the data signal corresponding to the SRAM is output to the SRAM, and the SRAM is controlled. Then, the data is stored in the address indicated by the address signal, and the control is performed. When the signal is read, in a video processing device including a memory control circuit that controls the SRAM to read the data held in the SRAM, restores the data of the title image, and outputs the data, the command is issued in accordance with a signal from the microprocessor. The MPU interface (microprocessor interface) that receives the control signal and outputs the control signal instead of the microprocessor is provided.
The interface, the memory control circuit, the gate element of the oscillation circuit, the horizontal address counter circuit, and the vertical address counter circuit are all integrated into one IC, and the memory control circuit, the oscillation circuit, the horizontal address counter circuit, The stop signal sent to any one of the vertical address counter circuits receives the command according to the signal from the microprocessor, and the MPU receives the command.
An image processing device characterized in that an interface generates, holds, and outputs.