JPH0573408A - Memory control system - Google Patents

Abstract

PURPOSE:To automatically select a memory in which a supplementary program is stored. CONSTITUTION:When a power source is turned on, an MPU 1 sets a memory selector signal 9 to a Logical '1' state, an address decoder 2 outputs a memory select signal 10 in order to execute an actuation program and a select signal 12 to a memory A 3 is outputted, and an actuation program 15 stored in the memory A 3 is executed by the MPU 1. By the actuation program 15, the contents of a memory B 4 are read, compared with a predefined value, and whether the memory B 4 is loaded or not is decided. When the MPU 1 decides that the memory B 4 is loaded by the actuation program 15, the MPU 1 sets the memory select signal 9 to logical '0'. Thereafter, when the MPU 1 executes a control program 16, a memory select signal 11 is outputted by the address decoder 2, and a memory select signal 13 is out-putted by an OR circuit 7, therefore, and the-improved control program 16 stored in the memory B 4 is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory control system,
In particular, it relates to a control method for selecting a plurality of memories.

[0002]

2. Description of the Related Art A conventional memory control system of this type is shown in FIG.
As shown in, microprocessor unit (MPU)
1, an address decoder 2, a memory A3, and a memory B
4 and a memory select switch 18 are provided.

The memory A3 has a control program for controlling the device and a data section. When the device is controlled only by the memory A3, the memory select switch 18 is turned off and the address decoder 2 to the memory A3. The select signal 12 is output.

Next, when the control program in the memory A3 is defective, but only the data part in the memory A3 is valid, the memory B4 containing only the improved control program is mounted, Memory select switch 18
Is turned on manually, and the address decoder 2 to the memory B4
To output the select signal 13 to.

[0005]

In this conventional memory control system, when the control program in the memory A3 is defective as shown in FIG. 4, the memory B4 is mounted and the control program in the memory B4 is installed. However, there is a problem in that it is necessary to manually switch the memory selector switch 18 in the case of operating with.

[0006]

A memory control system of the present invention is a memory control system having a microprocessor unit, wherein a memory storing a start-up program, a first control program and a data section, and the first memory are stored. A complementary memory for storing a second control program for compensating for a defect in the control program, and a judgment program for judging whether or not the complementary memory is mounted is provided in the startup program. The second
It has a control means for executing the control program.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a memory control system according to an embodiment of the present invention, FIG. 2 is a memory map diagram of a memory A in this embodiment, and FIG. 3 is a start-up stored in the memory A in this embodiment. It is a flow chart of a program.

In FIG. 1, in this embodiment, a microprocessor unit (MPU) 1 controls the whole of this embodiment, and an address decoder 2 allocates an address bus 8 output from the MPU 1 to a memory A3 and a memory B4. The memory select signals 10 and 11 are output, and in the memory A3, as shown in the memory map diagram of FIG. 2, a startup program 15 that operates at power-on, a control program 16 that controls the entire normal device, and these programs. Has a character data section 17 having independent data, the memory B4 stores a control program that compensates for the defect of the control program 16 in the memory A3, and the AND circuit 5 logically sums with the memory select signal 10. The logical product with the output of the circuit 6 is taken to produce the memory select signal 12 for the memory A3, and the logical sum circuit 7 Constitute a circuit for making a select signal 13 to the memory B4 taking the logical sum of the memory selection signal 11 and the memory select signals 9.

Next, the operation of this embodiment will be described with reference to FIGS.
And it demonstrates using FIG.

Now, assuming that the apparatus to which this embodiment is applied is powered on, the MPU 1 sets the memory select signal 9 to the logic "1" state, and the address decoder 2 executes the start program 15 to select the memory select signal 10. Is output to output the select signal 12 to the memory A3, and the start program 15 stored in the memory A3 causes the MPU1 to operate.
Executed by.

As shown in the flow chart of FIG. 3, the start-up program 15 reads the contents of the memory B4 (S11) and compares it with a predetermined value to judge whether the memory B4 is mounted (S12). When the MPU 1 determines that the memory B4 is mounted by the startup program 15, the MPU 1 sets the memory select signal 9 to the logic "0". Then M
When the PU 1 executes the control program 16, the address decoder 2 outputs the memory select signal 11,
Since the memory select signal 13 is output by the OR circuit 7, the improved control program stored in the memory B4 is executed.

On the other hand, when the MPU 1 does not recognize the mounting of the memory B4 from the boot program 15, the MPU 1 sets the memory select signal 9 to the logic "1". Then M
Control program 16 stored in memory A3 by PU1 16
Similarly, the address decoder 2 outputs the memory select signal 11 and the OR circuit 6 outputs the memory select signal 12.

[0014]

As described above, according to the present invention, whether or not the startup program stored in the first memory has the second memory in which another improved control program is stored. By having a control means for inputting the judgment program and automatically selecting the second memory containing the improved control program by the control of the microprocessor unit, the control program can be automatically controlled without manual selection from the outside. Has the effect that can be selected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of a memory A in this embodiment.

FIG. 3 is a flowchart of a boot program stored in a memory A according to the present embodiment.

FIG. 4 is a block diagram showing an example of a conventional memory control method.

[Explanation of symbols]

 1 Microprocessor unit (MPU) 2 Address decoder 3 Memory A 4 Memory B 5 Logical product circuit 6 Logical sum circuit 7 Logical sum circuit 8 Address bus 9 Memory select signal 10 Memory select signal 11 Memory select signal 12 Select signal 13 Select signal 14 Data bus 15 Startup program 16 Control program 17 Character data section 18 Memory select switch

Claims (1)

[Claims] 1. A memory control method having a microprocessor unit, comprising: a memory storing a start program, a first control program and a data section; and a second control program for compensating for a defect in the first control program. Complementary memory for storing, a control program for determining whether or not the complementary memory is mounted is provided in the boot program, and a control means for executing the second control program when the complementary memory is mounted by the determination program. A memory control method characterized by having.