JPH11224197A - Program download system for digital signal receiver - Google Patents

Abstract

(57) [Summary] [Problem] To automatically switch the program memory after downloading by a simple operation, and to start without having to check whether the information in the program memory is insufficient. To select the program memory for A device for receiving a digital signal has a plurality of program storage areas for storing a program of a microprocessor, means for reading desired data from the program storage area before the microprocessor is started, and holding the read data, and Means for selecting a program storage area to be used for starting the microprocessor based on a logical determination (logical product) of the value of the data thus obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program download system in a digital signal receiving device such as a digital broadcast receiving device, a data broadcast receiving device, and a data receiving terminal via a communication line.

[0002]

2. Description of the Related Art First, a configuration of a conventional digital broadcast receiver will be described with reference to FIG. In the figure, reference numeral 39 denotes a CPU which controls the entire system. The CPU program is stored in the program memory 42. The digital broadcast signal received from the CS antenna 31 is demodulated by the tuner 32. The demodulated transport stream signal (TS) is separated into a video / audio stream, program information, and the like by the DEMUX unit 33, and supplied to each block. In other words, video and audio streams are MPEG
After being decoded by the decoder 34, the video signal is converted from an RGB signal to a video signal by a video encoder 35 and output from an output terminal 36. The audio signal is converted into an analog signal by a D / A converter 37 and output from an output terminal 38. The program information is stored in the work memory 40.
Is converted into OSD (on-screen display) data such as a program table by the CPU 39 as necessary.
The video signal is synthesized by the EG decoder. The DEMUX unit 33 has a built-in memory controller, and the connected work memory 40 also has a function as a main memory of the CPU and a stream buffer for video and audio.

A digital broadcast receiver has a built-in C
Since the function changes depending on the PU program, a method of downloading the program from a broadcast in order to improve the function or correct a bug may be considered. According to this method, the program to be downloaded is mixed with the video / audio stream and the program information and transmitted by broadcasting. Therefore, the receiving side must extract and extract the program from the broadcast wave and store it in the program memory. No.

Next, the configuration of the download-compatible receiver will be described. In FIG. 3, download data mixed with a broadcast wave and sent is separated by a DEMUX 33 in the same manner as program information and the like, and
0 is stored.

FIG. 4 shows the CPU 39 and the CPU 39 shown in FIG.
FIG. 9 is a configuration example of a conventional receiving device in a case where a portion including the program memory 42 is adapted to download;
The other parts such as DEMUX are connected by an address bus and a data bus. In this case, the CPU 11 has two program memories, a program memory A13 and a program memory B14, one of which is used as an effective program memory, and the other is used for storing download data. When the download is completed normally, the effective program memory A13 or B
By switching 14, the downloaded program can be used. The mechanical switch 29 is connected to the selector 15 and the selector 16. The two selectors 15 and 16 are connected to the chip select signal (CS) of the program memory generated from the address decoder 12.
1, CS2). For example,
CS1 is a chip select signal of a valid program memory, CS2 is a chip select signal for download, and the mechanical switch 29 determines which program memory to supply them to.

Referring to FIG. 4, the download operation will be described for the case where the mechanical switch 29 is tilted to the low level. Since the selectors 15 and 16 select and output the A-input chip select signal, a valid program memory chip select signal (CS1) is stored in the program memory A13, and a download chip select signal (CS2) is stored in the program memory B14. Are supplied respectively. Therefore, in this case, the CPU 11 starts the operation by the program in the program memory A13 after the reset.

At the time of download, the CPU 11
The download data is read from the work memory 40 (FIG. 4) via the UX unit 33 and is read from the program memory B.
Write to 14. If the download is completed normally, the user is notified on the on-screen display or the like that "The download has been completed, disconnect the power outlet, switch the mechanical switch, and then plug the power outlet again". The user can unplug the power outlet, switch the mechanical switch, and then plug in the power outlet again to start and use the downloaded program. At this time, the program memory B14 is an effective program memory, and the program memory A13 is for downloading.

[0008]

In the conventional method, since a mechanical switch is used, when switching the program memory after downloading, the power outlet is once disconnected to prevent the receiver from breaking down, and the mechanical switch is used. Switching, and plugging in the power outlet again required a complicated operation. Further, if the mechanical switch is switched twice, it returns to the original state. Therefore, it is necessary to switch the mechanical switch only once, and a complicated operation that is difficult for the user to understand is required.

[0009]

According to a first aspect of the present invention, there is provided a program download system in a digital signal receiving apparatus, wherein a plurality of program storage areas for storing a program of a microprocessor, and the plurality of program storage areas are stored before the microprocessor is started. A program download system for a digital signal receiving apparatus, comprising: means for reading predetermined data from a program storage area of the above and holding the same, and means for selecting a program storage area to be used for starting the microprocessor based on the held data. It is.

According to a second aspect of the present invention, in the digital signal receiving apparatus according to the first aspect, the means for selecting the program storage area is used for starting the microprocessor by logically determining the value of the held data. 1 is a system for downloading a program in a digital signal receiving apparatus for selecting a program storage area to be executed.

According to a third aspect of the present invention, there is provided a program download system in a digital signal receiving apparatus,
A plurality of program storage areas for storing microprocessor programs, and a plurality of flip-flop circuits for reading and holding predetermined data from the plurality of program storage areas before starting the microprocessor;
A program download system in a digital signal receiving apparatus, comprising: an AND circuit to which data held in the plurality of flip-flop circuits is supplied; and a selector for selecting a program storage area to which an output of the AND circuit is supplied. .

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a program download system in the digital signal receiving apparatus of the present invention. Here, the description of the same parts as those of the conventional download system shown in FIG. 4 will be omitted, and only different parts will be described. The clock signal (CLOCK) is transmitted to the CPU 11 and the counter 22.
, And are used as respective basic clocks. The reset signal (RESET) is supplied to the counter 22 and is used together with the clock signal to generate timing until the CPU starts operating. Counter 2
2 is supplied to the logic circuit 23, where the timing signals (CSA_S, CSB_S,
RESET2) is created.

In FIG. 2, a counter output (COUNT)
[2: 0]) is 0 while the reset signal (RESET) is at the low level, and thereafter the reset signal (RE
SET) rises and the clock signal (CLOC)
The counter becomes 1 at the rise of K), and becomes 2 at the next rise of the clock signal, and the counter is stopped. That is, control is performed so that the counter is stopped when the counter value becomes 2. The CSA_S signal is a low-level pulse when the counter value is 0, and a high-level pulse otherwise.
The RESET2 signal is a high-level pulse when the counter is 2, and a low-level pulse otherwise.

As shown in FIG. 1, the RESET2 signal is
The signals are supplied to the CPU 11 and the selectors 17 and 18, and are used to delay the start of the operation of the CPU and to switch the control signal of the program memory before the start of the CPU operation. The CSA_S signal is connected to the selector 17 and the flip-flop.
It is supplied to the flop circuit 19 and used as a chip select signal for reading data from the program memory A13 before the start of the CPU operation and as a clock signal for holding the read signal in the flip flop circuit 19. Similarly, the CSB_S signal is supplied to the selector 18
Are supplied to the flip-flop circuit 20 and used as a chip select signal for reading data from the program memory B14 before the start of the CPU operation and as a clock signal for holding the read signal in the flip-flop circuit 20. You. An original chip select signal to be used after the operation of the CPU 11 is supplied to the B inputs of the selectors 17 and 18. The A input is selected when the RESET2 signal is at a low level, and the B input is selected when the RESET2 signal is at a high level. A13 and B14.

On the other hand, for example, the most significant bit of the data bus is supplied to the flip-flop circuits 19 and 20.
The data read from the program memories A13 and B14 before the operation of the CPU 11 is held and supplied to the AND circuit 21. In the AND circuit 21, the logical product of the two is calculated, and the result is supplied to the selectors 15, 16 to determine an effective program memory. Program memory A13, B14
In the most significant bit of the most significant address, information for determining which program memory to use at the time of startup is written. For example, if 0 is written, the program memory A13 is written, and if 1 is written, the program memory B is written.
14 will be designated.

Before starting the CPU operation (during reset), the CP
Although the address output of U11 is in a high impedance state, the address bus is pulled up by the resistor 24, so that all become high level, and the program memories A13, B
This means that the 14 highest addresses are specified. When the power is turned on, first, when the value of the counter 22 is 0, the signal of the program memory A13 is read and held in the flip-flop circuit 19. Next, the value of the counter 22 becomes 1
At this time, the signal of the program memory B14 is read and held in the flip-flop circuit 20. The data held in the flip-flop circuit 19 and the flip-flop circuit 20 is subjected to AND operation in the AND circuit 21, and the result is supplied to the selectors 15 and 16.

With such a circuit configuration, C
Before the PU 11 starts operating, the program memory A13,
Information for determining which program memory to use at startup is read from B14, and the program memory to be used at startup is selected by its logical product. As a result, the CPU is started normally and operates normally.

Next, when the download is performed and completed normally, and the user specifies to use the downloaded program, the program memory A1 is used.
The program of the CPU is designed to invert the most significant bit of the most significant address of 3, B14, and then notify the user of the content such as "Please unplug the power plug". If the CPU has a self-reset function, a method of inverting the most significant bit of the highest address of the program memories A13 and B14 and then using the self-reset function may be considered. In that case, since the CPU has a reset output terminal, it is used in combination with a normal reset signal.

Next, the reason for logically determining data read from a plurality of program memories will be described. In order to rewrite the contents of the rewritable memory (flash memory) used as the boot program memory, it is necessary to perform block erasing and then write. In the state where the block is erased, the data is all 1s. When this block is erased, AC
If the operation of the CPU 11 is stopped due to, for example, an unplug, the updating of information necessary for activation will be insufficient. However, since this information is written in a plurality of program memories, it can be avoided. For example, if the CPU stops in a state where the program memory A is erased, the data in the erased block is always 1 and the data in the other program memory to which normal information is written is stored. Normal information can be extracted by performing a logical product with the AND.
That is, there is no need to check whether the information in the program memory is insufficient, and the program memory for startup can be selected only by performing a logical product.

In this embodiment, a configuration is used in which a plurality of program memories are used. However, a configuration in which one memory is divided into a plurality of memories may be used. Here, the digital broadcast receiving device is described as an example, but the present invention is applicable to all devices that receive digital signals, such as a data broadcast receiving device and a receiving terminal of a communication line.

[0021]

According to the first aspect of the present invention, an effective program storage area is automatically selected from a plurality of program storage areas before the microprocessor is started, although the configuration is simple, and the microprocessor operates normally. Since it is activated, there is no need for a mechanical switch, and when switching the program memory after downloading, disconnect the power outlet once to prevent the failure of the receiver, switch the mechanical switch, plug in the power outlet again, etc.
No complicated operation is required. In addition, in a configuration using a mechanical switch, if the switching is performed twice, the state returns to the original state. Therefore, it is difficult for the user to understand, for example, the switching must be performed only once. However, in the present invention, an easy-to-understand operation can be realized.

According to another aspect of the present invention, when the information for selecting the program storage area is updated, for example, when the user turns off the power supply by performing an erroneous operation, the information for selecting the program storage area is updated. Even if the update is insufficient or one of the information for selecting the program storage area is broken, which program memory is selected to determine logically the data read from multiple program memories. Automatically determine whether
The microprocessor can be started normally.

[Brief description of the drawings]

FIG. 1 is an embodiment of a program download system in a digital signal receiving device of the present invention.

FIG. 2 is a timing chart of signals used in a program download system of the digital signal receiving device of the present invention.

FIG. 3 is a conventional digital signal receiving device.

FIG. 4 is a program download system in a conventional digital broadcast receiver.

[Explanation of symbols]

11 CPU, 12 address decoder, 13, 14 ...
Program memory, 15, 16, 17, 18 ... selector, 19, 20 ... flip-flop circuit, 21 ... AN
D circuit, 22 ... Counter, 23 ... Logic circuit, 24 ...
Resistor, 29 mechanical switch, 31 CS antenna, 3
2 Tuner, 33 DEMUX unit, 34 MPEG decoder, 35 Video encoder, 36, 38 Output terminal, 37 D / A for audio, 39 CPU, 40 Work memory, 42 Program memory.

Claims (3)

[Claims] 1. A program download system in a digital signal receiving apparatus, comprising: a plurality of program storage areas for storing a program of a microprocessor; and reading predetermined data from the plurality of program storage areas before starting the microprocessor. And a means for selecting a program storage area to be used for activating the microprocessor based on the stored data. 2. The digital signal receiving device according to claim 1, wherein the means for selecting the program storage area includes a program storage area used for activating a microprocessor based on a logical determination of a value of the held data. A program download system in a digital signal receiving apparatus, wherein the program is selected. 3. A program download system in a digital signal receiving apparatus, comprising: a plurality of program storage areas for storing a program of a microprocessor; and reading predetermined data from the plurality of program storage areas before starting the microprocessor. And a plurality of flip-flop circuits holding data supplied to the plurality of flip-flop circuits.
A program download system in a digital signal receiving device, comprising: an ND circuit; and a selector for selecting a program storage area to which an output of the AND circuit is supplied.