JPH0573430A - Ram data monitoring circuit - Google Patents

Abstract

PURPOSE:To easily cope with a change of the number of bits of check data or its generating method by replacing a check data generating circuit with a ROM in which the check data is stored. CONSTITUTION:A RAM 1 is connected to an address bus 5 and a data bus 6, and a ROM 3 in which check data is stored inputs data of the data bus 6 as an address. In a check memory 2 connected to the same address bus 5 as the RAM 1, check data read out of the ROM 3 at the time of writing the data to the RAM 1 is written, a check data comparing circuit 4 compares the check data read out of the ROM 3 at the time of reading out the data from the RAM 1 with the check data read out of the check memory 2 and when they do not coincide with each other, an alarm is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a RAM (Random).
Access Memory) data monitoring circuit,
RAM for monitoring errors in data stored in RAM
Data monitoring circuit

[0002]

2. Description of the Related Art A conventional RAM data monitoring circuit includes, for example, as shown in FIG. 2, a RAM 21 for storing data, a check memory 22 for storing check data, and a check data generating circuit 23 for generating check data. ,
Check data comparison circuit 24 for comparing check data
, An address bus 25 commonly connected to the RAM 21 and the check memory 22, and a data bus 2 commonly connected to the RAM 21 and the check data generation circuit 23.
It consisted of 6 and 6.

In such a conventional RAM data monitoring circuit, when writing data to the RAM 21, the check data generating circuit 2 is based on the data on the data bus 26.
The check data is generated in 3, and is written in the check memory 2 so that the generated check data has the same address as the address where the data is written in the RAM 21.

When reading data from the RAM 21, check data is generated by the check data generating circuit 23 based on the data on the data bus 26 read from the RAM 21, and the generated check data and R
The check data comparison circuit 24 compares the address at which the data is read from the AM 21 with the check data at the same address in the check memory 22. If the two check data do not match, the check data comparison circuit 24 outputs an alarm (ALM) to notify that there is an error in the data.

[0005]

In this conventional RAM data monitoring circuit, when the number of check data bits and the generation method are determined, the hardware of the check data generation circuit 23 is determined accordingly. If the number of bits of the check data or the generation method is changed, the hardware of the check data generation circuit 23 must be changed accordingly.

In view of the above points, an object of the present invention is to replace the check data generating circuit, which has conventionally generated the check data, with a ROM in which the check data is stored in advance, and to change the bit number of the check data or the generation method. It is to provide a RAM data monitoring circuit that can be easily dealt with.

[0007]

SUMMARY OF THE INVENTION A RAM data monitoring circuit according to the present invention is a RAM connected to an address bus and a data bus, a ROM for storing check data and inputting data on the data bus as an address, and the RAM.
A check memory connected to the same address bus as that for writing check data read from the ROM when writing data to the RAM, and check data read from the ROM when reading data from the RAM And a check data comparison circuit for generating an alarm when the check data read from the check memory are compared with each other and they do not match.

[0008]

In the RAM data monitoring circuit of the present invention, the RAM is connected to the address bus and the data bus, the ROM storing the check data inputs the data of the data bus as an address, and is connected to the same address bus as the RAM. The check memory is written with the check data read from the ROM when writing the data to the RAM,
The check data comparison circuit compares the check data read from the ROM with the check data read from the check memory when reading the data from the RAM, and generates an alarm when they do not match.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a RAM data monitoring circuit according to an embodiment of the present invention. The RAM data monitoring circuit of this embodiment is an RA for storing data.
M1 and check memory 2 for storing check data
And a check data generation ROM (ReadOnlyMe) in which the check data generated in advance is written.
memory) 3, a check data comparison circuit 4 for comparing the check data read from the ROM 3 with the check data read from the check memory 2, and a RAM.
1 and the check memory 2, the address bus 5 commonly connected, the data input terminal of the RAM 1 and the ROM 3
And a data bus 6 commonly connected to the address input terminals of the.

Next, the R of this embodiment constructed as described above is used.
The operation of the AM data monitoring circuit will be described.

When data is written in the RAM1, the write data becomes an address input of the ROM3, the check data stored at that address is read, and the read data is the address at which the data is written in the RAM1. Is written in the checking memory 2 so that the address becomes the same.

When reading data from the RAM 1, the data on the data bus 6 read from the RAM 1 becomes an address input of the ROM 3, and the check data stored at that address is read, and at the same time, the check memory is read. The check data of the corresponding address is also read from 2. Check data comparison circuit 4
Compares both check data and outputs an alarm (ALM) if they do not match to notify that there is an error in the data.

[0014]

As described above, according to the present invention, the check data generating circuit which has conventionally generated the check data is replaced with the ROM in which the check data is stored in advance. This has the effect of eliminating the need for circuit hardware.

Further, the bit width of the check data stored in the ROM can be any bit width within the maximum bit width. Therefore, by exchanging the ROM, the number of bits and the generation method of the check data differ. This has the effect of enabling data check.

Furthermore, by designing the structure of the check data comparison circuit according to the maximum bit width of the check data of the ROM, there is an effect that the versatility of the peripheral circuit of the ROM is enhanced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a RAM data monitoring circuit according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an example of a conventional RAM data monitoring circuit.

[Explanation of symbols]

 1 RAM 2 Check memory 3 Check data generation ROM 4 Check data comparison circuit 5 Address bus 6 Data bus

Claims (1)

[Claims] 1. A RAM connected to an address bus and a data bus, a ROM for storing check data and inputting data of the data bus as an address, and a RAM connected to the same address bus as the RAM.
Check memory to which check data read from the ROM is written when writing data to the ROM, and check data read from the ROM and read from the check memory when reading data from the RAM A RAM data monitoring circuit comprising: a check data comparing circuit which compares check data and generates an alarm when they do not match.