JPH02210687A - Refresh address generation circuit - Google Patents

Abstract

PURPOSE:To perform the refresh of a memory larger more in capacity by generating a high-order real refresh address from the most significant bit of a refresh address outputted from a refresh controller. CONSTITUTION:A refresh address generation circuit is provided with FFs 11 and 12. The most significant address information A8 out of address information A1-A8 of eight bits outputted from the refresh controller incorporating a microprocessor is supplied to the data input terminal of the FF 11, and logic output 18 in which a memory read signal 15 supplied from the microprocessor and a refresh request signal 16 supplied from the refresh controller are passed through an OR circuit 17 is supplied to a clock input terminal. The FF 12 inputs the Q output of the FF 11, and sets the Q output of the FF 12 as data input. The Q output of the FF 12 goes to the most significant address information A9 as additional address information, which enables the refresh of the memory large in capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh address generation circuit that refreshes a DRAM using a refresh controller built in a microprocessor.

[Conventional technology]

Relatively small capacity DRAM (dynamic random
If the access memory is to be refreshed, a refresh controller built into the microprocessor can be used to refresh it. However, when relatively large capacity DRAMs are used, it is no longer possible to refresh the entire area of the memory using only the address information output from the refresh controller built in the microprocessor.

Therefore, when using a relatively large-capacity DRAM, all pits of the refresh address output from the refresh controller are decoded, and the carries are used to create higher addresses. This was used to refresh the DRAM.

FIG. 3 shows such a conventionally used refresh address generation circuit.

This refresh address generation circuit generates address information for the 9th most significant bit to be added based on the 8-bit address information for refresh.

This refresh address generation circuit includes two stages of flip-flops 11 and 12. The data input terminal of the first-stage flip-flop 11 is supplied with a logic output 14 obtained by logically multiplying 8-bit address information A1 to A8 output from a built-in microprocessor controller (not shown) in an AND circuit 13. be done. Further, the clock input terminal of the first stage flip-flop 11 is connected to an OR circuit 17 which performs the logical sum of the memory read signal 15 supplied from the microprocessor and the refresh request signal 16 supplied from the refresh controller. The logical output 18 taken is provided.

The second-stage flip-flop 12 uses the Q output of the first-stage flip-flop 11 as a clock input, and receives the d output of the second-stage flip-flop 12 as data. A reset signal 19 is supplied to the clear terminals of the first and second stage flip-flops 11 and 12.

In such a conventional refresh address generation circuit, the Q output of the second stage flip-flop 12 becomes the highest address information A9 as additional address information.

Figure 4 shows 8-bit address information A1 output from the refresh controller built into the microprocessor.
.about.A8 and address information A9 created by the refresh address generation circuit of FIG. 3. As shown in this figure, in the conventional refresh address generation circuit, from address “000” (Y) to “OFF”
” (II), address information A9 becomes “l” and from now on “IFF” (II)
When the address space is incremented to 0, addressing of the entire address space of the DRAM is completed.

[Problem to be solved by the invention]

However, in such a conventional refresh address generation circuit, all the lower address information A1 to A8 are "1".
” In the next step, the upper address information A9 is changed to “
Since the address information is switched to "1", an AND circuit is required to detect that all of the lower address information becomes "1".

In this example, all of the lower address information is composed of 8 bits, but a multi-input AND circuit is required to perform the logical product of such a large number of addresses. For this reason,
There is a problem in that the circuit scale of the refresh address generation circuit increases.

Therefore, when a design change is made such as replacing the memory of a device from a small-capacity DRAM to a large-capacity DRAM, major problems often occur in the mounting area on the board and pattern wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a refresh address generation circuit that does not require a multi-input AND circuit.

[Means to solve the problem]

In the present invention, (i) refresh information output from a refresh controller built in a microprocessor;
(ii) a latch means for inputting and latching the most significant bit of an address; and (ii) generating a higher-order real refresh address necessary for refreshing the relatively largest memory based on the latch output of this latch means. A refresh address generation circuit is provided with an upper refresh address generation means.

That is, the present invention focuses on the fact that the DRAM address space is divided into blocks, and all bits of address information output from the refresh controller are all "1".
By changing the higher-order bits to "1" when the refresh controller reaches 1, it is no longer necessary to AND the address information output by the refresh controller.

〔Example〕 The present invention will be described in detail below with reference to Examples.

FIG. 1 shows a refresh address generation circuit in one embodiment of the present invention. This refresh address generation circuit also creates address information of the ninth most significant bit to be added based on the 8-bit address information for refresh.

This refresh address generation circuit includes two stages of flip-flops 11 and 12. The data input terminal of the first stage flip-flop 11 is supplied with the most significant address information A8 among the 8-bit address information A1 to A8 output from a refresh controller built in a microprocessor (not shown). Also, this first
At the clock input terminal of the flip-flop 11 of the stage, there is a logical output obtained by ORing the memory read signal 15 supplied from the microprocessor and the refresh request signal 16 supplied from the refresh controller using an OR circuit 17. 18 is supplied.

The second-stage flip-flop 12 uses the Q output of the first-stage flip-flop 11 as a clock input, and receives the output of the second-stage flip-flop 12 as data. A reset signal 19 is supplied to the clear terminals of the first and second stage flip-flops 1L12.

In such a refresh address generation circuit, the second
The Q output of the flip-flop 12 of the stage becomes the highest address information A9 as additional address information.

Figure 2 shows 8-bit address information A1 output from the refresh controller built into the microprocessor.
.about.8 and address information A9 created by the refresh address generation circuit of FIG. 1. As shown in this figure, unlike the conventional refresh address generation circuit, addressing is not performed continuously from address "000'" (II) to "IFF" (I()), but it is necessary to refresh the DRAM. The entire address space can be addressed.

On the right, in the embodiment, the flip-flop is configured in two stages, but if a flip-flop is added as necessary after the second stage flip-flop 12, it is possible to create an even higher-order real refresh address. Furthermore, a large capacity memory can be refreshed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to generate one or more bits of a refresh address using only the most significant bit of the refresh address output by the refresh controller and with the minimum required circuit configuration. . Therefore, even in a device using a large-capacity DRAM, the entire refreshment address space can be addressed using a conventional refresh controller.

[Brief Description of the Drawings] Figure 1 right and Figure 2 are for explaining one embodiment of the present invention. FIG. 3 is a block diagram of a conventional refresh address generation circuit, and FIG. 4 is an explanatory diagram showing the addressing state of the conventional circuit. 11... First stage flip-flop, 12...
...Second stage flip-flop, 17...
OR circuit, A8...The highest address information output from the refresh controller, A9...Address information one level above A8.

Claims (1)

[Claims] Latch means for inputting and latching the most significant bit of a refresh address output from a refresh controller built into a microprocessor; 1. A refresh address generation circuit comprising upper refresh address generation means for generating a higher-order real refresh address necessary for refreshing a memory.