JPH0574109B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a board selection method for selecting circuit elements on an expansion board in a line controller or the like.

[Conventional technology]

FIG. 2 is a schematic diagram of a line controller employing a conventional board selection method. In the figure, a main board 1 and two sub-boards 2a, 2b are sequentially connected by connectors 13a, 13b.
Here, a central processing unit (hereinafter referred to as CPU) 3 and a decoder 4 are installed on the main board 1.
is adapted to send an address signal to the decoder via the address bus 6. An interface circuit 5a and a selection circuit 12a are mounted on the sub-board 2a, and an interface circuit 5b and a selection circuit 12b are similarly mounted on the sub-board 2b. Of these, interface circuits 5a and 5b
has data input/output terminals D ₀ to _{D 7} and a control terminal, and the data input/output terminals are connected to CPU 3 and decoder 4.
A control terminal is connected to an output terminal CS of a selection circuit, which will be described later. In addition, the selection circuits 12a and 12b have data terminals A and B, a control terminal, SE and an output terminal CS.
Of these, the data terminal A is connected to the decoder 4.
The data terminal B is connected to the output line 8 derived from the output terminal A of the decoder 4, and the data terminal B is connected to the output line 9 derived from the output terminal B of the decoder 4, and both control terminals are grounded. The control terminal SE of the selection circuit 12a is connected to the pull-up resistor junction of the setting switch 14a by line 10a, and the output terminal CS is connected to the line 11.
A is connected to a control terminal of the interface circuit 5a. Similarly, the control terminal SE of the selection circuit 12b is connected to the line 10b.
It is connected to the pull-up resistor junction of the setting switch 14b, and the output terminal CS is connected to the control terminal of the interface circuit 5b by a line 11b.

FIG. 3 shows a state in which the main board 1 and the sub-boards 2a and 2b are sequentially connected by connectors 13a and 13b, and the sub-boards 2a and 2b can be added to the main board 1.

The next operation will be explained with reference to the chart showing truth values in FIG. When transferring data from the CPU 3 to the interface circuit 5a, first
The CPU 3 sends address data indicating the interface circuit 5a onto the address bus 6. When the decoder 4 reads the address data of the interface circuit 5a, it makes the output line 8 connected to the output terminal A active "L".

Here, as shown in FIG. 4, the selection circuits 12a and 12b output the state of the input terminal A to the terminal CS when the control terminal SE is "L", and input the state when the control terminal SE is "H". The state of terminal B is output to output terminal CS.

In this case, the setting switch 14a is turned on and the control terminal SE of the selection circuit 12a is at "L". Further, the setting switch 14b is turned off, and the control terminal SE of the selection circuit 12b is at "H".
Therefore, the selection circuit 12a inputs the signal of the output line 8 of the decoder 4 and outputs it to the output terminal CS,
The selection circuit 12b receives the signal from the output line 9 of the decoder 4 and outputs it to the output terminal CS. In this way, the output terminal CS of the selection circuit 12a becomes "L".
, this signal is sent to the interface circuit 5a.
is applied to the control terminal of the interface circuit to activate the interface circuit. Similarly, when the output terminal CS of the selection circuit 12b becomes "L", this signal is applied to the control terminal of the interface circuit 5b, putting this interface circuit into an operating state.

As mentioned above, when the CPU 3 sends address data indicating the interface circuit 5a, the output line 8 of the decoder 4 becomes "L";
Since the output line 9 remains "H", the control terminal of the interface circuit 5a is "L" and the control terminal CS of the interface circuit 5b is "H".
It is. Therefore, the interface circuit 5a
This interface circuit 5a can exchange data with the CPU 3 via the data bus 7 and communicate with the outside.

On the other hand, when the CPU 3 selects the interface circuit 5b, if the address data of the interface circuit 5b is sent onto the address bus 6, the decoder 4 inputting this data will be connected to the output line connected to the output terminal B. 9 is set to active "L" and the data terminal B of the selection circuit 12b is set to "L", thereby setting the control terminal of the interface circuit 5b to "L" and putting it into an operating state. Therefore, the interface circuit 5b can exchange data with the CPU 3 via the data bus 7, and can communicate with the outside.

Thus, in this line controller, by simply sending the address data of the sub-board to be added to the main board 1 to the decoder 4, it is possible to select the desired board and exchange data and communicate with the outside. .

[Problem that the invention seeks to solve]

In the conventional board selection method described above, the setting switches 14a, 14b are installed on the expansion boards 2a, 2b.
However, there was a problem in that all operations other than keeping the setting switch 14a in the on state and the setting switch 14b in the off state result in malfunctions, and setting errors are likely to occur.

This invention was made in order to solve the above problems, and its purpose is to provide a board selection method that can reliably prevent malfunctions caused by incorrect switch settings when adding sub-boards. do.

[Means for solving problems]

In the board selection method according to the present invention, each of the sub-boards connected to the main board is provided with a pull-up means for maintaining a high control signal input to the control terminal of the selection circuit, and each sub-board is connected to the main board via a connector. In this case, only the control terminal of the selection circuit on one sub-board is released from the pull-up state.

[Effect]

In this invention, by simply connecting two sub-boards to the main board, the control terminal of the selection circuit on one sub-board becomes "L", and the control terminal of the selection circuit on the other sub-board becomes "H". This makes it possible to reliably prevent malfunctions caused by incorrect switch settings.

〔Example〕

FIG. 1 shows an example of the configuration of an apparatus for carrying out the present invention, and in the figure, the same reference numerals as in FIG. 2 indicate the same elements. In Fig. 2, a setting switch is provided on the sub-boards 2a and 2b, one end of which is grounded and the other end connected to the positive pole of the power supply via a pull-up resistor, and the other end of this setting switch is connected to the selection circuit. It was connected. On the other hand, here, the first and second selection circuits, for example, the selection circuit 12 mounted on the first and second sub-boards, for example, the sub-boards 15a and 15b having the same circuit configuration.
From each control terminal SE of a, 12b to line 16a,
16b, and connect pull-up resistors 17a and 17b, one end of which is connected to a +5 (V) power supply, to these lines, and connect the sub-board 15a to the main board 1 via the connector 13a. At this time, the line 16a connected to the pull-up resistor 17a is connected to the ground point of the main board 1, but
Another sub-board 15 via the connector 13b
Even if b is connected to the main board 1, the pull-up resistor 17b
Provision is made so that the line 16b connected to is not grounded. In addition, the control terminal of the selection circuit 12a
SE is referred to as a first control terminal, and control terminal SE of the selection circuit 12b is referred to as a second control terminal.

Therefore, the main board 1 has sub-boards 15a and 15b.
The control terminal of the selection circuit 12a can be changed by simply connecting the
SE is held at the "L" level control signal, and conversely, the control terminal SE of the selection circuit 12b is held at the "H" level.

As a result, the CPU 3 sends the address data of the sub-board 15a onto the address bus 6, and the decoder 4
When the interface circuit 5a makes the output line 8 active "L", the interface circuit 5a becomes operational, and can exchange data with the CPU 3 and communicate with the outside via the data bus 7. On the other hand, when the CPU 3 sends the address data of the sub-board 15b onto the address bus 6 and the decoder 4 makes the output line 9 active "L", the interface circuit 5b enters the operating state and communicates with the CPU 3 via the data bus 7. It becomes possible to exchange data and communicate with the outside world.

In addition, in the above embodiment, the sub-board 15 is provided on the main board 1.
a, 15b, the control terminal SE of the selection circuit 12a is connected to the ground point of the main board 1 and becomes "L".
However, if only the control terminal of the selection circuit on one sub-board can be released from the pull-up state, the same operation as described above can be performed even if other means are adopted. can.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, simply by connecting two identical sub-boards to the main board, the control signal of the control terminal of the selection circuit of one sub-board becomes "L". Since the control signal at the control terminal of the selection circuit on the other sub-board becomes "H", it is possible to reliably prevent malfunctions due to incorrect switch settings.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an apparatus implementing the present invention, FIG. 2 is a schematic configuration diagram of a line controller that employs a conventional board selection method, and FIG. 3 is a side view showing the board assembly state of this line controller. FIG. 4 is a chart showing truth values for explaining the operation of this line controller. 1...Main board, 3...Central processing unit, 4...Decoder, 5a, 5b...Interface circuit,
12a, 12b... selection circuit, 15a, 15b...
...Subboard, 17a, 17b...Pull-up resistor,
In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A main board having a decoder, and a main board connected to the main board and selectively taking in any of the output signals of the decoder depending on the logic level of a control signal applied to a first control terminal. a first sub-board having a first selection circuit to output; and a first sub-board connected to the first sub-board and selectively selecting one of the output signals of the decoder depending on the logic level of a control signal applied to a second control terminal. a second sub-board having a second selection circuit for inputting and outputting data into the main board, the first sub-board is connected to the main board, and the second sub-board is connected to the first sub-board. A board selection method characterized in that the control signals of the first control terminal and the second control terminal are set to complementary logic levels. 2 The first control terminal and the second control terminal are each connected to the anode of the DC power supply via a resistor, and connect the first sub-board to the main board and connect the second sub-board to the first sub-board. 2. The board selection method according to claim 1, wherein either the first control terminal or the second control terminal is grounded via the main board.