JPH0574149A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to prevent a malfunction and a decrease in operation margin of a multi-bit semiconductor memory device having a flash write function without increasing an occupied area of a cell array. .. A sense amplifier SA connected to the bit line performs a cell information read operation and a memory holding operation for the memory cell C based on the cell information read from the memory cell C to a bit line BL and a bar BL. By operating the flash write transistor Trf that is selected and activated by the flash write control circuit 6, a flash write function of collectively rewriting cell information of a large number of memory cells C is provided, and the transistor Trf activates the sense amplifier. From the digitizing circuit 4 to the sense amplifier SA on the low potential side power source N
A source is connected to a power supply line for supplying SG, a drain is connected to the bit line, and a gate is connected to the flashlight control circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a flash write function.

One type of DRAM is a dual port memory having a built-in serial access memory, which is particularly used as an image memory. Since such a DRAM is required to operate at high speed, it has a flash write function that allows the cell information of the memory cells connected to the same word line to be collectively rewritten. Also in DRAMs, high integration and miniaturization of chips are required.

[0003]

DRAM having a flash write function
An example will be described with reference to FIG. 7. Many pairs of bit lines B
A large number of memory cells C each composed of one transistor and one capacitor are connected to L and bar BL, and N channel MOS transistors Tr1 and Tr2 and P channel are provided for each pair of bit lines BL and bar BL. Sense amplifiers SA composed of MOS transistors Tr3 and Tr4 are connected to each other. Further, a reset circuit 1 is connected to each bit line BL and bar BL, and a reset voltage VPR of 1/2 Vcc is supplied from the reset voltage supply circuit 2 to the reset circuit 1 and the reset circuit 1 is at the H level. When the reset signal BRS is input, the bit lines BL, B
L is reset to the reset voltage VPR.

A sense amplifier activation circuit 4 is connected to each sense amplifier SA, and when the H level activation signal LE is input to the sense amplifier activation circuit 4, the N-channel MOS transistor Tr1 of each sense amplifier SA, The low-potential-side power supply NSG is supplied to the source of Tr2, and the P-channel MO
The high-potential-side power supply PS is connected to the sources of the S transistors Tr3 and Tr4.
G is supplied.

A reset circuit 5 is connected to each sense amplifier SA, the reset voltage VPR of 1/2 Vcc is supplied from the reset voltage supply circuit 2 to the reset circuit 5, and the sense amplifier activation circuit 4 is set to an H level. When the H level reset signal BRS is input to the reset circuit 5 while the activation signal LE is not input, the low potential side power supply NSG and the high potential side power supply PSG are reset to the reset voltage VPR.

A drain of a flash write transistor Trf composed of an N channel MOS transistor is connected to each bit line BL and bar BL, and a source of the transistor Trf is connected to a low potential side power source Vss.
The gate of the transistor Trf connected to one bit line BL of each pair of bit lines has the flash write control circuit 6 via the flash write word line FW0.
, And the gate of the transistor Trf connected to the other bit line bar BL is connected to the flash write control circuit 6 via the flash write word line FW1.

Therefore, when either of the flash write word lines FW0 and FW1 is pulled up to the H level by the flash write control circuit 6, the transistor Trf is concerned.
Is turned on and either the bit line BL or the bar BL is pulled down to the L level.

A normal read operation of the DRAM thus configured will be described with reference to FIG. 8. First, prior to the read operation, the reset signal BRS is pulled down to the L level to stop the operation of the reset circuits 1 and 5, and then the reset circuit BRS is stopped. When one of the word lines WL is selected by the row decoder and pulled up to the H level, cell information is read from the memory cell C connected to the word line WL and the bit line B is read.
A slight potential difference occurs between L and bar BL.

In this state, the activation signal LE is input to the sense amplifier activation circuit 4 and the sense amplifier SA is supplied with the power supply Vss.
The low-potential-side power supply NSG of the level and the high-potential-side power supply PSG of the power supply Vcc level are supplied to activate the sense amplifier SA, the potential difference between the bit lines BL and bar BL is enlarged, and its cell information is transferred to the data bus (illustrated in the figure). No.) and the cell information refresh operation is performed on the memory cell C based on the bit line potential.

Then, the selection of the word line WL is stopped and pulled down to the L level, and the sense amplifier activation signal LE is generated.
Is pulled down to the L level to stop the power supply to the sense amplifier SA, the reset signal BRS is pulled up to the H level, and the low potential side power source NSG and the high potential side power source PS are supplied.
G, the bit line BL, and the bar BL are reset to the reset potential VPR of 1/2 Vcc, and wait for the next operation.

On the other hand, the flash write operation of the DRAM will be described with reference to FIG.
Is lowered to the L level, then one of the word lines WL is selected and the cell information read from the memory cell C causes a slight potential difference between the bit lines BL and BL.

In this state, when the flash write control circuit 6 selects, for example, the flash write word line FW0 and raises it to H level, the transistor Trf connected to the flash write word line FW0 is turned on and the bit line BL is set to L level. Can be lowered to a level.

Then, the activation signal LE is input to the sense amplifier activation circuit 4, the low potential side power source NSG and the high potential side power source PSG are supplied to the sense amplifier SA, the sense amplifier SA is activated, and the bit line is activated. The potential difference between BL and BL is enlarged, and the cell information of all memory cells C connected to the word line selected based on the bit line potential is rewritten.

Then, the selection of the word line WL is stopped and pulled down to the L level, and the flash write word line F
W0 is pulled up to L level, the sense amplifier activation signal LE is pulled down to L level, power supply to the sense amplifier SA is stopped, and the reset signal BRS is pulled up to H level, so that the low-potential-side power source NSG and high The potential-side power supply PSG and the bit lines BL and BL are reset to the reset potential VPR of 1/2 Vcc, and the next operation is awaited.

Conventionally, as shown in FIG. 10, a memory cell array corresponding to one input / output I / O is formed for one cell array. However, in recent dual port memories, the number of bits has been increased and one Memory cells corresponding to a large number of input / output circuits I / O are formed in the cell array 7. For example, as shown in FIG.
It is divided into parts corresponding to one input / output I / O 0 to I / O 3. There are a total of four cell arrays 7, corresponding to I / O 0 to I / O 15, each column decoder 8 and row decoder 9
In some cases, each input / output I / O 0 to I / O 15 can output an output signal of 16 bits, one bit at a time. In such a cell array 7, if the row decoder 9 is provided for each input / output I / O, the circuit area increases, so that the common row decoder 9 selects the memory cell corresponding to each input / output I / O. ing.

Therefore, the multi-bit DR as described above is used.
The flashlight function part in AM has the following configuration. That is, as shown in FIG. 12, for example, the bit lines BL1 and BL1 correspond to the input / output I / O 0, the bit lines BL2 and BL2 correspond to the input / output I / O 1, and to the bit lines BL1 and BL1. The gate of the connected flash write transistor Trf is connected to the flash write control circuit 6a via the flash write word lines FW00 and FW01, and the gate of the flash write transistor Trf connected to the bit lines BL2 and BL2 is the flash. It is connected to the flash write control circuit 6b via the write word lines FW10 and FW11, and the respective flash write control circuits 6a and 6b are controlled so as to operate independently and the respective input / output I / O 0 and I / O are controlled. The flash write operation can be performed for each one.

The flash write operation will be described with reference to FIG. 13. First, the reset signal BRS is pulled down to L level, then one of the word lines WL is selected and the bit line BL1 is selected by the cell information read from the memory cell C. , BL1 and BL2, BL2 generate a slight potential difference.

In this state, if only the flash write control circuit 6a is operated to perform flash write to the memory cell corresponding to the input / output circuit I / O 0 and the word line FW00 for flash write is pulled up to the H level, the flash concerned is flashed. The transistor Trf connected to the write word line FW00 is turned on, and the bit line BL1 is pulled down to L level.

Then, the activation signal LE is input to the sense amplifier activation circuit 4, the low potential side power source NSG and the high potential side power source PSG are supplied to the sense amplifier SA, the sense amplifier SA is activated, and the bit line is activated. The potential difference between BL1 and BL1 is enlarged, and the cell information of the memory cell C connected to the word line WL selected based on the bit line potential is rewritten.

[0020]

However, in the above-described operation, the transistor Trf connected to the flash write word line FW00 is turned on and the bit line BL1 is turned on.
Bit line B in the process of falling to the L level.
When the potential of L1 falls below the potential of the bit line bar BL1 by the threshold value Vth of the N-channel MOS transistor Tr1 in the sense amplifier SA, the transistor Tr1 is turned on and reset to the 1/2 Vcc level. Lowers NSG. Then, each sense amplifier SA is activated prior to the activation signal LE, and the input / output circuit I / O 1 that does not perform the flash write operation is activated.
Before the cell information is surely read from the storage cell selected by the bit line BL2, bar BL2 corresponding to, the sense amplifier SA corresponding to the bit line BL2, bar BL2 starts to operate.

Therefore, the sense amplifier SA connected to the bit lines BL2 and BL2 is connected to the bit lines BL2 and BL.
The operation margin may be reduced by amplifying the unstable potential difference of No. 2 or the cell information of the selected memory cell may be destroyed due to the malfunction of the sense amplifier SA.

On the other hand, a sense amplifier SA is provided for each input / output.
Although the above problem can be solved by using a separate power source as the power source, there is a problem that the separate power source for each input / output circuit increases the number of power source wirings and increases the circuit area.

An object of the present invention is to prevent malfunction and reduction in operation margin of a multi-bit semiconductor memory device having a flash write function without increasing the area occupied by the cell array.

[0024]

FIG. 1 illustrates the principle of the present invention. That is, a predetermined memory cell C is selected by selecting the bit line BL, bar BL and the word line WL, and the bit line is read based on the cell information read from the memory cell C to the bit line BL, bar BL. A sense amplifier SA connected to BL and bar BL performs a read operation of the cell information and a memory holding operation to the memory cell C, and a flash write transistor Trf is connected to each bit line BL and bar BL. The flash write transistor Trf is connected to the flash write word line FW.
The flash write control circuit 6 has a flash write function of collectively rewriting cell information of a large number of storage cells C connected to the selected word line WL by selecting and activating the flash write control circuit 6 via the flash write control circuit. The transistor Trf has a source connected to the power supply line for supplying the low-potential-side power supply Vss from the sense amplifier activation circuit 4 to the sense amplifier SA, and a drain connected to the bit line BL, bar BL
And the gate was connected to the flashlight control circuit 6.

The flash write transistor Trf has a drain connected to a power supply line for supplying a high potential side power supply Vcc from the sense amplifier activation circuit 4 to the sense amplifier SA, and a source connected to the bit lines BL and BL. Alternatively, the gates may be connected to the flashlight control circuit 6.

[0026]

The flash write transistor Trf selected by the flash write control circuit 6 operates at the same time as the activation of the sense amplifier SA so that the potentials of the bit lines BL and bar BL connected to the transistor Trf are changed to the sense amplifier SA.
Of the low-potential-side power source NSG or high-potential-side power source P
Move to SG level.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
~ It demonstrates according to FIG. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 2, the bit lines BL1 and BL1 correspond to the input / output I / O0, the bit lines BL2 and BL2 correspond to the input / output I / O1, and the respective bit lines BL1 to BL2. The source of the flash light transistor Trf connected to is connected to each sense amplifier SA at the low potential side power supply NS.
It is connected to a power supply line that supplies G. The drain and source of each transistor Trf are connected in the same manner as in the conventional example.

Now, during the normal read operation of the DRAM thus constructed, all the flash write transistors Trf are turned off, so that the read operation is the same as that of the conventional example as shown in FIG.

On the other hand, the flash write operation will be described with reference to FIG. 4. First, the reset signal BRS is pulled down to the L level, then one of the word lines WL is selected, and the bit line is read according to the cell information read from the memory cell C. A slight potential difference is generated between BL1, bar BL1 and BL2, bar BL2.

In this state, when only the flash write control circuit 6a is operated to perform flash write to the memory cell corresponding to the input / output I / O 0, and the flash write word line FW00 is pulled up to the H level, the flash write is performed. The transistor Trf connected to the word line FW00 is turned on. However, in this state, the drain and the source of the transistor Trf are both maintained at the reset potential and have the same potential, so that the drain current does not flow in the transistor Trf.

Next, the activation signal LE is input to the sense amplifier activation circuit 4, the low potential side power source NSG and the high potential side power source PSG are supplied to the sense amplifier SA, and the sense amplifier SA is activated. At the same time, the source potential of the transistor Trf is lowered, so that the drain current flows through the transistor Trf and the potential of the bit line BL1 is lowered.
The potential difference between the bit lines BL1 and BL1 is expanded by the operation of the sense amplifier SA based on the potential difference of 1, and the cell information of the memory cell C connected to the word line WL selected based on the bit line potential is rewritten. Be done.

Therefore, as shown in FIG. 5, the flash write transistor Trf is connected to the sense amplifier SA by the flash write operation on the bit lines BL1 and BL1 corresponding to the input / output I / O 0, and the sense amplifier SA is connected. Is activated at the same time that the transistor Trf is turned on and the bit line BL1
Is at the L level and the bar BL1 is at the H level, the potential difference is enlarged. Further, since the flash write transistor Trf is not turned on in the bit lines BL2 and BL2 corresponding to the input / output I / O 1, only the bit lines BL2 and BL2 are connected to the sense amplifier SA as shown in FIG. Then, the low-potential-side power supply NSG and the high-potential-side power supply PSG are supplied to the sense amplifier SA based on the sense amplifier activation signal LE to perform the refresh operation of the selected memory cell.

As described above, in this DRAM, a large number of sense amplifiers S that output cell information to different input / output circuit I / Os.
For the sense amplifier SA which outputs cell information corresponding to the input / output I / O which does not perform flash write even when the power source of A is common, only on the low potential side based on the sense amplifier activation signal LE. Since the power supply NSG and the high-potential-side power supply PSG can be supplied, it is possible to prevent a decrease in the operation margin or the occurrence of malfunction in the sense amplifier SA.

In the above embodiment, the source of the flash write transistor Trf is connected to the power supply line for supplying the low-potential-side power supply NSG to the sense amplifier SA, and the drain is connected to the bit lines BL and BL to flash. Based on the operation of the write transistor Trf, the bit line BL,
Although the potential of the bar BL is lowered, the drain of the flash light transistor Trf is connected to the sense amplifier S.
A is connected to a power supply line that supplies a high-potential-side power supply PSG, the source is connected to the bit lines BL and bar BL, and the potentials of the bit lines BL and bar BL are raised based on the operation of the flash write transistor Trf. Such a configuration may be adopted.

[0036]

As described above in detail, according to the present invention, in a semiconductor memory device having a multi-bit structure having a flash write function, it is possible to prevent the malfunction and the decrease of the operation margin without increasing the occupied area of the cell array. Exhibits excellent effects that can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing a normal operation of one embodiment.

FIG. 4 is a waveform diagram showing a flash write operation according to an embodiment.

FIG. 5 is an equivalent circuit diagram showing a connection state of a sense amplifier and a flash write transistor during a flash write operation according to an embodiment.

FIG. 6 is an equivalent circuit diagram showing a connection state between a sense amplifier and a flash write transistor in a normal operation according to an embodiment.

FIG. 7 is a circuit diagram showing a conventional example.

FIG. 8 is a waveform diagram showing a normal operation of a conventional example.

FIG. 9 is a waveform diagram showing a flash write operation of a conventional example.

FIG. 10 is a layout diagram showing a cell array of a 4-bit DRAM.

FIG. 11 is a layout diagram showing a cell array of a 16-bit DRAM.

FIG. 12 is a circuit diagram showing a conventional multi-bit DRAM.

FIG. 13 is a waveform chart showing an operation of a conventional multi-bit DRAM.

[Explanation of symbols]

 4 Sense amplifier activation circuit 6 Flash write control circuit BL, bar BL Bit line WL Word line C Storage cell Trf Flash write transistor FW Flash write control circuit SA Sense amplifier NSG Low potential side power source PSG High potential side power source

Claims (2)

[Claims] 1. A predetermined memory cell (C) is selected by selecting a bit line (BL, bar BL) and a word line (WL), and the bit line (BL, bar B) is selected from the memory cell (C).
L), the bit line (B
A sense amplifier (SA) connected to L, bar BL) performs a read operation of the cell information and a memory holding operation for the memory cell (C), and a flash write to each bit line (BL, bar BL). Transistor (Trf)
To connect the flashlight transistor (Tr
A large number of memory cells (C) connected to the selected word line (WL) by selecting and activating f) by the flash write control circuit (6) via the flash write word line (FW). Is a semiconductor memory device having a flash write function of collectively rewriting the cell information of the above, wherein the source of the flash write transistor (Trf) is a low potential from the sense amplifier activation circuit (4) to the sense amplifier (SA). A semiconductor memory device characterized by being connected to a power supply line for supplying a side power supply (NSG), a drain being connected to a bit line (BL, bar BL), and a gate being connected to a flash write control circuit (6). 2. A predetermined memory cell (C) is selected by selecting a bit line (BL, bar BL) and a word line (WL), and the bit line (BL, bar B) is selected from the memory cell (C).
L), the bit line (B
A sense amplifier (SA) connected to L, bar BL) performs a read operation of the cell information and a memory holding operation for the memory cell (C), and a flash write to each bit line (BL, bar BL). Transistor (Trf)
To connect the flashlight transistor (Tr
A large number of memory cells (C) connected to the selected word line (WL) by selecting and activating f) by the flash write control circuit (6) via the flash write word line (FW). Is a semiconductor memory device having a flash write function of collectively rewriting the cell information of the above, wherein the flash write transistor (Trf) has a drain of a high potential from the sense amplifier activation circuit (4) to the sense amplifier (SA). A semiconductor memory device, characterized in that it is connected to a power supply line for supplying a side power supply (PSG), a source is connected to a bit line (BL, bar BL), and a gate is connected to a flash write control circuit (6).