JPH0574193A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect, in a test mode, a defective mode due to an interference between data buses at the inside or an interference between a plurality of memory cell arrays. CONSTITUTION:A data write bus changeover circuit 13 supplies a test data from a data input buffer 18 to internal write data buses WB1 to WB4. A test data control circuit 11 decides whether a test data conversion circuit 12 supplies a test data to four memory cell arrays 1a as it is according to the logic level of a most significant address bit Amsb in a test mode or whether it supplies a test data in a reverse phase to an adjacent memory cell array 1a. When the test data in the reverse phase is written in the adjacent memory cell array 1a, whether an interference exists or not can be judged by a test data judgment circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a test circuit capable of simultaneously testing more data than the number of external input / output data.

[0002]

2. Description of the Related Art A semiconductor memory device having a conventional test circuit has a structure as shown in FIG. 5. In this conventional example, the number of external input / output data is 1, and the number of data which can be tested simultaneously is 4. Is an example of. Here, 1 is a memory cell array section, and this memory cell array section 1 is divided into four memory cell arrays 1a. Each memory cell array includes a large number of memory cells. Each memory cell array has a row decoder 16, a column decoder, and a sense amplifier 1C. 2 is a data read / write amplifier section, 3 is a data bus switching circuit, 4 is a test mode control circuit, 5 is a test data determination circuit, 6 is a data bus selection circuit, and 7 is controlled by an external control signal WE (overline). A write control circuit, 8 is a data input buffer for converting an external data input to an internal data bus level,
A data output buffer 9 outputs the data on the internal data bus to the outside as a data output.

(RWB1, RWB1B), (RWB2,
RWB2B), (RWB3, RWB3B), (RWB
4, RWB4B) is a set of four internal data bus pairs for exchanging data with four memory cell arrays 1a, (RWB4B).
0, RWB0B) are selectively connected to the above-mentioned four data bus pairs via the data bus switching circuit 3, and an internal data bus pair for connecting the data input buffer 8 and the data output buffer 9 to the data bus switching circuit 3. , RWS1, RWS
2, RWS3 and RWS4 are data bus selection signals for selectively switching the four sets of data buses to the internal data bus pair RWB0 and RWB0B. The data bus switching circuit 3 includes N-channel MOS transistors (Q11, Q12), (Q21,
Q22), (Q31, Q32), (Q41, Q42), and the data bus selection signal RWS is applied to each gate.
1, RWS2, RWS3, RWS4 are input.

ΦTEST is an internal test mode control signal output from the test mode control circuit 4, φWE is an internal write control signal, φTF is an output from the test data determination circuit 5, and controls the data output buffer 9.

FIG. 6 shows a conventional test data decision circuit, in which φTD is a test data decision result signal.

Next, the operation of the conventional example will be described. It is the test mode control circuit 4 that switches between the normal operation and the test mode operation (internal multiple data test operation). There are cases where the test mode is specified by applying a voltage higher than the external power supply to a certain external terminal from the outside, or the test mode is specified by the combination of the states of the external control signals. Will be omitted.

First, the operation in the normal operation will be described. In this case, the internal test mode control signal φTEST is "0", and the portions related to the test mode operation such as the test data determination circuit 5 are inactivated. First, an external address is input to the semiconductor memory device, and a specific memory cell in the memory cell array section 1 is selected by the row decoder 16 and the column decoder 1C. At this time, in each of the four memory cell arrays 1a, one memory cell having the same address is selected. The data bus selection circuit selects one of the simultaneously selected 4-bit memory cells, and the data bus selection circuit 6 receives the address signal and outputs one memory cell array 1
4 internal data bus pairs (RWB1, R
One bit of memory cells is selected by selectively connecting any one of (WB1B) ... (RWB4, RWB4B) to the internal data bus pair (RWB0, RWB0B).

During a write operation, the input data input is activated with φWE set to "1", and the internal data bus pair (RWB0, RWB0 is passed through the data input buffer 8).
B) (If the data input is “1”, RWB
0 is "1" and RWB0B is "0"). Now, assuming that only the data bus selection signal RWS1 is at high level,
The N-channel MOS transistors Q11 and Q12 are turned on, and the internal data bus pair (RWB0, RWB0B) and (RWB0
WB1, RWB1B) and the selected memory cell in the leftmost memory cell array 1 has φWE =
Data is written through the data read / write amplifier 2 that has been set to the write operation at “1”. At this time, the data output buffer 9 is inactivated by φWE.

On the other hand, during the read operation, φWE = “0”
And the data input buffer 8 is deactivated,
The data output buffer 9 is activated to read / read data.
The write amplifier 2 performs a read operation.

In the read operation, the data of the four memory cells selected at the same time is the data read / write amplifier 2
Via four internal data bus pairs (RWB1, RWB
1B) ... (RWB4, RWB4B).
If only the data bus selection signal RWS1 is at a high level as in the case of the above-described write operation, the internal data bus pair (RWB1, RWB1B) becomes the internal data bus pair (RWB1).
WB0, RWB0B), and the data of the memory cell selected from the leftmost memory cell array 1a is transferred to the data output buffer 9 and output to the outside. If RWB0 = "1" and RWB0B = "0", the data output becomes "1".

Next, the write and read operations in φTEST = "1", that is, the test mode operation will be described. Basically, it is the same as the above-described normal operation. First,
The write operation will be described. φWE = “1” and φTEST
= “1”, the data bus selection circuit 6 receives the data bus selection signals RWS1 ... RWS regardless of the address signal.
4 are all set to a high level, and all the MOS transistor pairs (Q11, Q12) ... (Q4
1, Q42) is turned on, and (RWB) on the internal data bus pair is turned on.
0, RWB0B) data into four data bus pairs (RW
B1, RWB1B) ... (RWB4, RWB4B). Then, the same data is written in four memory cells on different memory cell arrays 1a that are simultaneously selected.

The read operation is φWE = “0” and φTEST =
Start with "1". The data bus selection circuit 6 sets only the data bus selection signal RWS1 to a high level regardless of the address signal, and turns on the MOS transistor pair (Q11, Q12) of the data bus switching circuit 3. Therefore, the data of the internal data bus pair (RWB1, RWB1B) is transmitted to the internal data bus pair (RWB0, RWB0B) and input to the data output buffer 9. At the same time, the internal data bus pair (RWB2, RWB2B), (RWB3, RWB3
The data on (B) and (RWB4, RWB4B) are supplied to the test data determination circuit 5 via the data bus lines RWB1, RWB2, RWB3, RWB4 and it is determined whether or not all the data are the same. This is because the data written in the test mode should be the same in the 4-bit memory cell selected as described above, and the test data determination circuit 5 outputs the output signal φTF indicating the match or the mismatch. Table 1 shows a test data judgment table in the test mode operation.

[0013]

[Table 1]

As shown in Table 1, if the internal data bus lines RWB1 to RWB4 have the same logic level, the judgment is "match".
The output signal .phi.TF is "0", and the data output has its logic level determined based on the data input to the data output buffer 9. However, internal data bus line RWB
If even one of 1 to 4 has a different logic level, the determinations do not match, the output signal .phi.TF is "1", and the output of the data output buffer 9 is Hi-Z (inactive state, high impedance state).

By performing a test mode operation capable of simultaneously testing a larger number of data than the number of external input / output data as in the conventional example, the time required for testing the memory cell array can be shortened. In this example, the read / write time of all memory cells is 1/4 in the test mode operation as compared with the normal operation. However, in the test mode operation like the conventional example, the same data is always written and read for all 4 bits, so that the interference between the internal data buses and the interference between different memory cell arrays are detected only by the test mode operation. I can't.

[0016]

In this conventional semiconductor memory device, the same data is written / read to / from all the memory cells being tested at the same time during the test mode operation in which a large number of data are simultaneously tested internally. Therefore, there is a problem in that interference between internal data buses and interference between different memory cell arrays cannot be reliably detected.

[0017]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a plurality of memory cell arrays, write means for simultaneously writing input data to selected memory cells in each memory cell array, and selected memory cells in each memory cell array. Output means for selecting and outputting output data simultaneously read from the cells, and judging the logical state of the output data simultaneously read from the selected memory cells in each memory cell array to judge the presence or absence of a failure. In the semiconductor memory device having a test means, the write means is a test data conversion circuit which supplies a plurality of memory cell arrays in a non-inverted state or selectively inverts a logical level of input data in response to a control signal. It is to have a circuit.

[0018]

When the control signal is at the first predetermined level and the input data is supplied, the input means writes the input data to the plurality of memory cell arrays whose logic levels are inverted by the test data conversion circuit. The output data read from the plurality of memory cell arrays is judged by the test means.

When the control signal is at the second predetermined level and the input data is supplied, the input means inputs the input data selectively inverted by the test data conversion circuit and the non-inversion input data to the plurality of memory cell arrays. The supplied and read output data is judged by the test means.

[0020]

An embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a test data conversion circuit, FIG. 3 is a circuit diagram of a test data control circuit, and FIG. 4 is a test data determination circuit. FIG.

In the conventional example, the internal data buses are paired, and four sets of write and read buses (RWB1, RWB) are provided.
1B) to (RWB4, RWB4B) are commonly used for writing and reading, but in this embodiment, as shown in FIG. 1, four internal write buses WB1'-
It is provided with WB4 'or WB1 to WB4 and four internal read buses RB1 to RB4, and one of these is connected to each memory cell array 1a.

To cope with this, the data read / write amplifier 10 of the present embodiment corresponds to each memory cell array 1a.
Data is transferred to and from the data bus pair 1e for input / output, and one data write bus can be transferred and / or converted to / from the data bus pair 1e at the time of writing, and each data bus pair 1e can be transferred at the time of reading. Data can be transferred to one data read bus. In this embodiment, the output data is a data write bus W for sending input data from the data input buffer 18 to each of the four memory cell arrays 1e via one data write bus WB0.
B1 to WB4 and WB1 'to WB4' are selectively transferred, and in order to control this transfer, a data write bus switching circuit 13 and a data write bus selection circuit 15 are provided. Data write bus selection signals WS1 to WS4 are supplied to the gates of the channel MOS transistors Q11 to Q41.

Data sent from the four memory cell arrays 1a are read from the data read buses RB1 to RB4,
One data read bus R to the data output buffer 19
A data read bus switching circuit 14 and a data read bus selection circuit 16 are provided for selective selection via B0. N channel MOS transistors Q12 to Q42 of the data read bus switching circuit 14
Receives data read bus selection signals RS1 to RS4 from the data read bus selection circuit 16.

The data write bus selection circuit 15 and the data read bus selection circuit 16 are supplied with the test mode control signal φTEST from the test mode control circuit 4 and controlled by the internal read / write control signal φWE and the highest address signal Amsb. It

A test data conversion circuit 12 is provided between the data write buses WB1 to WB4 and the data write buses WB1 'to WB4'. The test data conversion circuit 12 is an output of the test data control circuit 11. It is controlled by the test data control signal φTS. The test data control signal φTS is controlled by the highest address Amsb and the test mode control signal φTEST.

Further, the test data judgment circuit 17 is controlled by the test data control signal φTS, and the test data judgment signal φTF output from the judgment circuit 17 controls the data output buffer 19.

Hereinafter, the normal operation of this embodiment (φTEST =
“0”) and the test mode operation (φTEST = “1”) will be described. Here, the operation of the memory cell array unit 1 is assumed to be the same as the conventional one. First, normal operation (φTEST = "0")
In the write operation (φWE = “1”), the data input buffer 18 and the data write bus selection circuit 15 are activated by the internal read / write control signal φWE, and the data read / write amplifier 10 enters the write state.
On the other hand, the data output buffer 19 and the data read bus selection circuit 16 are deactivated.

When φTEST = “0”, the test data control circuit 11 sets the test data control signal φTS to “1” as shown in Table 2, and the test data conversion circuit 12 is shown in Table 3. WB1 = WB1 ', WB2 = W
B2 ′, WB3 = WB3 ′, and WB4 = WB4 ′.
In this state, the data input buffer 18 level-converts and supplies the input data from the external data input terminal 21 to the internal data bus WB0, and the internal data bus WB0 is supplied with the internal data bus WB1 by the data write bus selection signals WS1 to WS4. To WB4. As a result, the input data is written in any of the memory cells selected simultaneously in each memory cell array 1a.

[0029]

[Table 2]

[0030]

[Table 3]

On the other hand, in the read operation (φWE = “0”) in the normal operation (φTEST = “0”), the data output buffer 19 and the data read bus selection circuit 16 are activated by the internal write / read control signal WE, Data read /
The write amplifier 10 is in a read state. On the other hand, the data input buffer 18 and the data write bus selection circuit 15
Is deactivated. Data of four memory cells simultaneously selected in the memory cell array 1a is read / read.
Data read bus RB1 through write amplifier 10
To RB4, the data read bus selection circuit 16
Indicates the internal read buses RB1 to RB according to the address signal.
Any one of 4 is connected to the internal read bus RB0.
The internal read bus RB0 inputs the selected data to the data output buffer 19 and outputs it to the external data output terminal 22. At this time, as shown in Table 2, φTEST =
Since φTF = “0” at “0”, the operation of the data output buffer 19 is not hindered.

Next, the test mode operation (φTEST =
In the write operation (φWE = “1”) in “1”), the data input buffer 18 and the data write bus selection circuit 15
Is activated, and the data output buffer 19 and the data read bus selection circuit 16 are deactivated. Since φTEST = “1”, the data write bus selection circuit 15 selects the data write bus selection signals WS1 to WS regardless of the address signal.
All 4 are set to an active level (high level), and all N-channel MOS transistors Q11 to Q41 are turned on. As a result, the internal write data bus WB0 is connected to all the internal write buses WB1 to WB4. The test data control circuit 11 is activated, and the test data control signal φTS is issued by the highest address signal Amsb input to it.

In the test mode operation, the highest address signal Amsb is not used for memory cell selection in the memory cell array section 1. In this embodiment, as shown in Table 2, if the highest address Amsb is "0", then φTS
= “0”. At this time, as shown in Table 3, the test data conversion circuit 12 has WB0 = WB1 = WB2 =
If WB3 = WB4 = “0”, then WB1 ′ = “0”,
WB2 '= "1", WB3' = "0", WB4 '=
Adjacent data write buses WB1 'to "1"-
The data is converted so that WB4 'has an opposite phase.
On the other hand, if the highest address signal Amsb is "1", φTS
= “1”, and as shown in Table 3, WB1 ′ =
WB2 ′ = WB3 ′ = WB4 ′ = “0”, and they all operate in phase. Each data is written in the selected four memory cells through the data read / write amplifier 10 in the write state. As described above, in this embodiment, the four data to be written in the four selected memory cells to be written in the test mode operation are transferred via the test data control signal φTS controlled based on the highest address signal Amsb. Logic level can be selected.

In the read operation (φWE = “0”) in the test mode operation (φTEST = “1”), the data write bus 15 and the data input buffer 18 are deactivated, and the data read bus selection circuit 16 and the data output buffer are provided. 19 is activated, the data read / write amplifier 10 enters the read state, and the data from the memory cell selected from each memory cell array 1a is read data bus RB1.
~ Read to RB4. In the test mode operation, the data read bus selection circuit 16 sets only the selection signal RS1 to the high level regardless of the address signal, and the N channel MOS
The transistor Q12 is turned on, the internal read data buses RB0 and RB1 are connected, and the read data is input to the data output buffer 19.

The test data determination circuit 17 to which the data on the read data buses RB1 to RB4 is input operates as follows. For example, when the most significant address signal Amsb is “0”, φTS = “0”, and WB0 = “0”, when the data written in the test mode operation is read, the relationship between the read data bit and the read data bus Is RB1 = "0", RB2 = "1", RB3 = "0",
RB4 should be "1". When inputting them to the test data judgment circuit 17 shown in FIG. 4, φTS = “0”
Therefore, RB1 ′ = RB2 ′ = RB3 ′ = RB4 ′
= “0”, the determinations match as shown in Table 4, and φTF = “0”.

[0036]

[Table 4]

In this case, the data output buffer is set to 19
Through this, “0” is output to the external terminal 22. However, if the test data judgment circuit as described above is different from the expected data (RB1 '= RB2' = RB3 '= RB
If it is not 4 '), as shown in Table 4, the determinations do not match, φTF = "1", the data output buffer 19 is deactivated, and the external terminal 22 is Hi-Z (high impedance state). become.

The highest address signal Amsb is "1", φTS
= “1”, when WB0 = “0” and the data written in the test mode operation is read, RB1 = R
When B2 = RB3 = RB4 = “0” is input to the test data determination circuit 17, since φTS = “1”, RB1 ′ = RB2 ′ = RB3 ′ = RB4 ′ = “0”.
Therefore, as shown in Table 4, the judgments are in agreement,
φTF = "0". Then, the data output buffer 19
“0” is output to the external terminal 22 through. Of course, also in this case, if RB1 ′ to RB4 ′ are not the same data, the judgments will not match as shown in Table 4, and φTF
= “1”, and the data output terminal 22 becomes Hi-Z.

As described above, in this embodiment, the test mode writing / reading can be performed while controlling the logic level of the data supplied to the memory cell by the logic level of the address signal Amsb which is not used in the test mode state. it can. Therefore, a defective mode due to interference between internal data buses, interference between cell arrays, etc., which cannot be detected by the conventional test mode operation, can be detected.

In this embodiment, only the test mode operation of the external 1-bit and internal 4-bit operation has been described. However, the present invention is an external 1-bit, internal 8-bit test mode operation, external 4-bit, internal 16-bit test. It can be applied to many cases such as mode operation.

[0041]

As described above, according to the present invention,
Since the test data conversion circuit can write the selectively inverted input data to the plurality of memory cell arrays, it has an effect of being able to detect a failure mode due to interference between internal data buses and interference between the plurality of memory cell arrays. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a test data conversion circuit in one embodiment.

FIG. 3 is a circuit diagram of a test data determination circuit according to an embodiment.

FIG. 4 is a circuit diagram of a test data determination circuit according to an embodiment.

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is a circuit diagram of a conventional test data determination circuit.

[Explanation of symbols]

1 Memory Cell Array Section 2 Conventional Data Read / Write Amplifier 3 Data Bus Switching Circuit 4 Test Mode Control Circuit 5 Conventional Example Test Data Judgment Circuit 6 Data Bus Selection Circuit 7 Write Control Circuit 8 Data Input Buffer 9 Data Output Buffer 10 Data read / write amplifier of one embodiment of the invention 11 Test data control circuit 12 Test data conversion circuit 13 Data write bus switching circuit 14 Data read bus switching circuit 15 Data write bus selection circuit 16 Data read bus selection circuit 17 Test Data Judgment Circuit of Example 18 Data Input Buffer of One Example of the Present Invention 19 Data Output Buffer (RWB0, RWB0B) to (RWB4, RWB4B) of One Example of the Present Invention
Internal data bus pair RB0, RB1, RB1 'to RB4, RB4' Internal read data bus WB0, WB1, WB1 'to WB4, WB4' Internal write data bus RWS1 to RWS4 Data bus selection signal RS1 to RS4 Data read bus selection signal WS1 ~ WS4 Data write bus selection signal φWE Internal read / write control signal φTEST Test mode control signal φTF Test data determination signal φTS Test data control signal Q11 to Q12 N-channel MOS transistor 20 WE (overline) (external read / write control signal terminal) 21 External data input terminal 22 External data output terminal

Claims (2)

[Claims] 1. A plurality of memory cell arrays, write means for simultaneously writing input data to selected memory cells in each memory cell array, and output data read simultaneously from the selected memory cells in each memory cell array. In a semiconductor memory device comprising an output means for selecting and outputting and a test means for judging the presence / absence of a failure by judging a logical state of output data simultaneously read from a selected memory cell in each memory cell array The semiconductor memory is characterized in that the writing means has a test data conversion circuit which supplies a plurality of memory cell arrays in a non-inverted state or selectively inverts a logical level of input data in response to a control signal. apparatus. 2. The semiconductor memory device according to claim 1, wherein when the data conversion circuit selectively inverts the logic level of the input data, the input data having mutually opposite phases are supplied to the adjacent memory cell arrays.