JPH0574199A - Test data creation device and test data creation method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a test data generation device, and devises a model of a read-only storage element or a storage element that can be read / written at any time, and inspects the storage element including the storage element by using a logic simulation. The purpose is to automatically create test data for testing the target peripheral circuit. [Structure] Storage means 11 for storing various data DIN, D1, D2, D3, DOUT relating to creation of test data DOUT of the object 16 to be inspected, and data creating means 12 for generating test data DOUT of the object 16 to be inspected. A data processing means 14 for connecting the adding means 13 relating to the signal input / output of the object 16 to be inspected, and a control means 15 for controlling the input / output of the storage means 11, the data creating means 12 and the data processing means 14. The control means 15 includes a read-only storage element ROM or a read / write storage element RA at any time.
The test data DOUT is controlled based on the assumed faults set in the inspection target 16 including M.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIGS. 11 and 12) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 3) Action Example (1) First Implementation Description of Example (FIGS. 4 to 7) (2) Description of Second Embodiment (FIGS. 8 to 10)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test data creating apparatus and a test data creating method, and more specifically, to a read-only storage element (ROM) or a read / write as needed.
The present invention relates to an apparatus and method for creating test data relating to a semiconductor integrated circuit in which writable storage elements (RAM) are mixed.

In recent years, as semiconductor integrated circuit (hereinafter simply referred to as “LSI”) devices have become highly integrated and highly densified, in the LSI design field, logic for automatically creating test data for logical failure inspection of newly developed LSI devices. A simulation device is used.

According to this, a hypothetical fault portion is set in an object to be inspected for a combinational circuit which does not include a memory element, and then an additional circuit is connected to the circuit to generate a test pattern in which the hypothetical fault is set. Data to be tested is supplied to the circuit, and test data is automatically created based on the data. However, the object to be inspected is a combinational circuit that does not include a memory element.

Therefore, it is possible to perform read / write at any time, which makes it difficult to continuously simulate read-only memory elements and data write / read processing in which it is difficult to develop a simulation model for logic failure processing in a logic simulation. It is not possible to create test data for testing a peripheral circuit to be inspected including a memory element and the like.

Therefore, a model of a read-only memory element or a memory element that can be read / written at any time is devised, and automatic generation of test data for testing a peripheral circuit to be inspected including the memory element by using a logic simulation. What is desired is an apparatus and method that can do the above.

[0007]

2. Description of the Related Art FIGS. 11 and 12 are explanatory views according to a conventional example. FIG. 11 is an explanatory diagram of a test data creating method according to a conventional example, and FIGS. 12 (a) to 12 (c) are supplementary explanatory diagrams thereof, respectively.

For example, a logic simulation apparatus for automatically creating test data DOUT of an object 4 to be inspected for a combinational circuit which does not include a memory element as shown in FIG. 1, a data processing auxiliary editor 2 and a CPU (central processing unit) 3.

The function of the device is that when the test data DOUT for the logic failure test of the semiconductor integrated circuit device is created,
For example, as shown in the control flowchart of the CPU 3,
First, in step P1, input processing of the inspection object 4 is performed,
Set the assumed failure part. At this time, the LSI circuit data D1 is read from the memory unit 1 via the data processing auxiliary editor 2 and the CPU 3, and, for example, a hypothetical failure portion is set in the input portion of the two-input OR circuit of the inspection object 4. ..

Next, in step P2, an additional circuit is connected to the object to be inspected 4 in which the assumed failure portion is set, and the test pattern generating circuit 6 is prepared. At this time, the fault inserter 5A sets a hypothetical fault in the hypothetical fault portion of the inspection object 4 through the data processing auxiliary editor 2, and the input searcher 5B is connected to the input portion of the inspection object 4. Further, an output inspector 5C is connected to the output part of the inspection object 4, and the fault inserter 5A, the input searcher 5B and the output inspector 5 are connected.
The synchronous controller 5D is connected to C.

Then, in step P3, the data to be tested DIN is supplied to the test pattern generation circuit 6 in which the assumed failure is set. At this time, the data under test DIN is read from the memory unit 1 via the data processing auxiliary editor 2 and the CPU 3, and the input search unit 5 of the test pattern generation circuit 6 is read.
It is supplied to B and the data DIN is input to the test pattern generation circuit 6.

After that, in step P4, the test data DOUT is detected based on the detection processing of the presence or absence of a hypothetical failure of the inspection object 15.
Create the process. At this time, the test pattern generation circuit 6 outputs the result data affected by the assumed failure to the output inspector 5C, the data processing auxiliary editor 2 processes the result data, and the result data is output as the test data DOUT. It

As a result, the test data DOUT for testing the peripheral circuit of the combinational circuit not including the memory element is automatically created based on the LSI circuit data DIN. It should be noted that the method using this logic simulation apparatus achieves 10 times or more speedup as compared with a test pattern generation system that depends on software on a general-purpose large-scale computer.

[0014]

By the way, according to the automatic generation method of the test data DOUT using the conventional logic simulation apparatus, the CPU 3 in step P1 tests the combination circuit which does not include the storage element. The target 4 is input, the hypothetical failure portion is set therein, and in step P2, an additional circuit is connected to the object 4 to be inspected,
The test pattern generation circuit 6 in which the assumed failure is set in 3 is supplied with the data under test DIN.

Therefore, the test data DOUT for testing the peripheral circuits of the object 4 to be inspected including the read-only memory element (hereinafter also simply referred to as ROM) and the memory element which can be read / written at any time (hereinafter simply referred to as RAM). I can't make it.

This is an RO that can generally handle logic failures.
Difficult to develop M model and writing / writing data
This is because it is difficult to simulate the continuous operation of the RAM that performs the read process on the logic simulation. Here, the logical failure processing of the ROM model is, when a signal input to the ROM is involved in a failure, an output value of the ROM based on the failure input value and an output value of the ROM based on a normal input value having no failure. And means that the logical failure output values are different. This requires the ROM model to have a function of transmitting the logic fault output value.

For example, as a model of the ROM, a ROM pattern (RO of 0 or 1) for a normal input value is used.
ROM for the fault input value based on the contents of M)
A method of creating a model in which a pattern is created and a failure output value corresponding to the failure input value is output can be considered.

However, the ROM pattern for the failure input value must be created for each ROM of each type, which may complicate the data processing. Further, when the data writing process is performed in the RAM and then the data reading process is continuously performed in the RAM, two processing operations are required in the logic simulation, which are not equivalent. , It is not possible to simultaneously generate a test pattern for writing and a test pattern for reading.

Therefore, it becomes difficult to automatically generate the test patterns of the ROM-containing test pattern generating circuit and the RAM-containing test pattern generating circuit. As a result, the circuit data for the model of the ROM capable of logical failure processing is inevitably changed, and the time required to create the test pattern is significantly increased.

The present invention was created in view of the problems of the conventional example, and devises a model of a read-only storage element or a storage element that can be read / written at any time, and the storage element is created by using a logic simulation. It is an object of the present invention to provide a test data creating apparatus and a test data creating method capable of automatically creating test data for testing a peripheral circuit to be inspected including the test data.

[0021]

FIG. 1 is a principle view of a test data creating apparatus according to the present invention, and FIG. 2 (a)-(c).
FIG. 3 is a principle diagram (1) of the test data creating method according to the present invention, and FIGS. 3A to 3C show principle diagrams (2) of the test data creating method according to the present invention. There is.

As shown in FIG. 1, the test data creating apparatus of the present invention is an apparatus for automatically creating test data DOUT for performing a logical failure test of an object 16 to be tested of a semiconductor integrated circuit device. Various data DIN, D1, D2, D related to creation of test data DOUT of the object 16 to be inspected
3, storage means 11 for storing DOUT, and data creation means 12 for generating test data DOUT of the inspection object 16
And an addition means 1 for inputting / outputting a signal to / from the inspection target 16.
Data processing means 14 for connecting 3 and the storage means 1
1, a control means 15 for controlling the input / output of the data creating means 12 and the data processing means 14, and the control means 1
5 controls the generation of the test data DOUT on the basis of a hypothetical failure set in the device under test 16 including a read-only memory element ROM or a memory element RAM that can be read / written at any time.

In the test data generating device,
The control means 15 develops a memory element RAM that can be read / written at any time into two memory elements RAM1 and RAM2, and controls connection of the signal pass line GL between the two memory elements RAM1 and RAM2. (See FIG. 2A).

Further, in the test data generating device,
The control means 15 controls the connection of the address condition determination means 13E for determining the validity of the address value ADD designated in the two storage elements RAM1 and RAM2 (see FIG. 2 (b)).

Further, in the test data creating apparatus, the control means 15 inputs the first input means 12A for inputting the normal value of the data under test DIN and the second input for inputting the failure value of the data under test DIN. Means 12B, a first storage element ROM1 for storing a normal value of the data under test DIN,
The read-only storage element ROM is provided for the second storage element ROM2 for storing the failure value of the data under test DIN and the output means 12C for outputting the normal value or the failure value of the data under test.
Is controlled (see FIG. 3A).

Further, in the test data creating device,
The control means 15 inserts a hypothetical fault into an arbitrary hypothetical fault occurrence portion of the inspection object 16, and a hypothetical fault insertion means 13A,
Input means 13B for supplying the data under test DIN, output means 13C for detecting the presence or absence of the assumptive fault, and synchronization control means 13D for controlling input / output of the assumptive fault inserting means 13A, input means 13B and output means 13C. It is characterized by controlling the connection with (see FIG. 2 (b) and FIG. 3 (b)).

In the test data creating device,
A data input / output unit 17 for assisting input / output of the storage unit 11, the data creation unit 12, the data processing unit 14, and the control unit 15 is provided (see FIG. 1).

A first test data creating method of the present invention is a method for automatically creating test data DOUT for performing a logical fault test of a semiconductor integrated circuit device, and at least:
As shown in the flow chart of FIG. 2 (c), first, in step P1, the occasional read / write operation included in the inspection target 16 is performed.
The writable storage element RAM is internally expanded, and then the internally expanded storage element R is processed in step P2.
The process of setting a hypothetical fault is performed on an arbitrary hypothetical fault occurrence portion of the test subject 16 including the AM, and then the test data D is set on the test subject 16 to which the hypothetical fault is set in step P3.
IN is supplied, and thereafter, in step P4, the test data DOUT is created based on the detection process of the presence or absence of the assumed failure of the object 16 to be inspected (FIG. 2).
(See (b)).

In the first test data creating method, the internal expansion processing is performed by expanding the storage element RAM, which is included in the inspection object 16 and can be read / written at any time, into the two storage elements RAM1 and RAM2. However, the connection processing of the signal passing line GL is performed between the two expanded storage elements RAM1 and RAM2 (see FIG. 2A).

In the first test data creating method, the process of supplying the test data DIN of the test object 16 and the process of detecting the presence or absence of a hypothetical fault are performed by two storage elements R.
It is characterized in that it is carried out based on the same address value ADD designated in AM1 and RAM2.

Further, in the first test data creating method, two storage elements R are provided in the hypothetical fault occurrence portion.
It is characterized in that the peripheral positions at which simultaneous faults occur simultaneously are selected for AM1 and RAM2.

Further, in the first test data generating method, two storage elements RAM are used for the process of detecting the presence or absence of the hypothetical failure in step P4A of the flowchart of FIG. 2 (c).
1 and RAM2 includes a process for determining the validity of the specified address value ADD.

Furthermore, the second test data creating method of the present invention is a method for automatically creating test data DOUT for performing a logical fault test of a semiconductor integrated circuit device, and at least the flow chart of FIG. First, as shown
In step P1, internal conversion processing of the read-only storage element ROM included in the inspection object 16 (see FIG. 3A).
Then, in step P2, a process of setting a hypothetical fault is performed on an arbitrary part of the hypothetical fault that has occurred in the inspected object 16 including the storage element ROM subjected to the internal conversion process.
In step 3, the test data DIN is supplied to the test object 16 in which the hypothetical failure is set, and thereafter, in step P4, the test data DOUT is created based on the detection process of the presence or absence of the hypothetical failure in the test object 15. It is characterized by performing processing (see FIG. 3B).

In the second test data generation method, in the memory element ROM which has undergone the internal conversion processing in step P4A of the flowchart of FIG. 3C, the data under test DIN is separated into a normal value and a failure value. Processing, and thereafter, in step P4B, based on the separation processing, the data under test DIN
In order to achieve the above-mentioned object, the normal value storing process and the failure value storing process of the data under test DIN are performed.

[0035]

According to the test data preparation apparatus of the present invention, the storage means 11, the data preparation means 12, the data processing means 14, the control means 15 and the data input / output means 17 are provided, and the control means 15 is a read-only storage element. The creation control of the test data DOUT is performed based on the assumed failure set in the inspection target 16 including the ROM or the storage element RAM that can be read / written at any time.

For example, when the LSI circuit data D1 including the storage element RAM that can be read / written at any time via the data input / output means 17 is read out from the storage means 11, the control means 15 controls the storage element. RAM
Is expanded into the two storage elements RAM1 and RAM2, and the signal passing line GL is connected between the two storage elements RAM1 and RAM2 (see FIG. 2A).

Further, the addition means 13 relating to the signal input / output of the object 16 to be inspected is connected to the data processing means 14 via the control means 15. At this time, the additional circuit data D2 is read from the storage means 11, and as the addition means 13, the hypothetical fault insertion means 13A, the input means 13B,
The output means 13C and the synchronization control means 13D are connected by the control means 15 (see FIG. 2B).

Incidentally, a hypothetical fault is inserted into an arbitrary hypothetical fault occurrence portion of the inspection object 16 through the hypothetical fault insertion means 13A, and the control means 15 causes, for example, the synchronous control means 12D to address condition determination means 13E. Are connected (Fig. 2
(See (b)).

Therefore, the test data D of the object 16 to be inspected
OUT is automatically generated by the data creating means 12. For example, the input means 13 for the inspected object 16 for which the assumed failure is set
The data under test DIN is shown in B as the control means 15 and the synchronization control means.
When supplied via 13D, the output means 13C detects the presence or absence of a hypothetical failure of the inspected object 16. At this time,
The validity of the address value ADD designated in the two storage elements RAM1 and RAM2 is determined.

As a result, the test data DOU is generated by the data creating means 12 based on the assumed failure set in the inspection target 16 including the storage element RAM which can be read / written at any time.
It is possible to automatically create T. The test data DOUT is stored in the storage means 11 in some cases (the first test data creation process of the present invention, see FIG. 2).

Further, when the LSI circuit data D1 relating to the inspection object 16 including the read-only memory element ROM is read from the memory means 11, the memory element ROM is controlled by the control means 15 to the first and second input means 12A. , 12B, first,
It is converted into the second memory elements ROM1 and ROM2 and the output means 12C (see FIG. 3A).

Further, the addition means 13 relating to the signal input / output of the inspection object 16 is connected to the data processing means 14 via the control means 15. At this time, the additional circuit data D2 is read from the storage means 11, and as the addition means 13, the hypothetical fault insertion means 13A, the input means 13B,
The output unit 13C and the synchronization control unit 13D are connected via the control unit 15 and the data processing unit 14 (see FIG. 3B).

A hypothetical fault is inserted into an arbitrary hypothetical fault occurrence portion of the inspection object 16 through the hypothetical fault insertion means 13A (see FIG. 3B). Therefore, the inspection target 16
The test data DOUT is automatically generated by the data creating means 12. For example, the inspection target 1 for which the assumed failure is set
When the data under test DIN is supplied to the input means 13B of No. 6 through the control means 15 and the synchronization control means 13D, the output means 13C detects the presence or absence of a hypothetical failure of the inspected object 16.

At this time, the normal value of the data under test DIN is input to the first input means 12A and the failure value thereof is input to the second input means 12B.
And the values of both are stored in the first and second storage elements ROM1 and ROM2, respectively, and as a result,
The normal value or the failure value of the data under test DIN is output from the output means 12C to the output means 13C.

As a result, the test data DOUT can be automatically created by the data creating means 12 based on the assumed failure set in the object 16 to be inspected including the read-only memory element ROM. The test data DOUT is stored in the storage means 11 in some cases (the second test data creation process of the present invention, see FIG. 3).

Further, according to the first test data creating method of the present invention, as shown in the flow chart of FIG.
Storage element RA that can be read / written at any time in step P2
The hypothetical fault is set in any hypothetical fault occurrence portion of the test object 16 in which M is internally developed, and then the test data DIN is supplied to the test object 16 for which the hypothetical failure is set in step P3. ..

For example, the storage element RAM which is included in the inspection object 16 and which can be read / written at any time is time-developed at two times, and the two storage elements RAM1 and RAM subjected to the development processing.
The signal passing line GL is connected between the two (hereinafter also referred to as a RAM expansion circuit).

Therefore, the data D to be tested of the object 16 to be tested is based on the same address value ADD designated in the RAM expansion circuit reconfigured as one circuit data as a whole.
IN supply processing and detection processing for the presence or absence of assumed failure are performed. Two storage elements RAM
For 1 and RAM2, the peripheral position where the contingencies simultaneously occur is selected.

From this, in step P4A of the flowchart of FIG. 2C, for example, two storage elements RAM1,
The presence / absence of a hypothetical failure is detected based on the determination process of the validity of the address value ADD designated in RAM2. Therefore,
By supplying the data to be tested DIN once to the RAM expansion circuit, a continuous operation relating to the writing process of the data to be tested DIN to the expansion circuit and the reading process of the data under test DIN is simulated on the logic simulation. It becomes possible.

The two processing operations are performed by the signal passing line G.
L makes them equivalent on the logic simulation,
It is possible to simultaneously generate a test pattern for writing and a test pattern for reading.

As a result, the test data DOUT for testing the peripheral circuit to be inspected including the readable / writable memory element and the like can be automatically created in step P4 (see FIG. 2B). ).

Further, according to the second test data creating method of the present invention, as shown in the flowchart of FIG. 3C, the read-only memory element ROM of the object 16 to be inspected is internally converted in step P2. The hypothetical fault is set in an arbitrary hypothetical fault occurrence portion, and then the data under test DIN is supplied to the inspected object 16 for which the hypothetical fault is set in step P3.

Therefore, as in the conventional example, a ROM pattern for the fault input value is created based on the ROM pattern for the normal input value (contents of the ROM of 0 or 1), and the fault output value for the fault input value is created. RO that outputs
Compared with the M model, the test data DOUT can be automatically created in a short time based on the detection process of the presence or absence of the assumed failure of the inspection object 15 in step P4.

At this time, for example, the storage element R which has been internally converted in step P4A of the flowchart of FIG. 3C.
In the OM, the data under test DIN is separated into a normal value and a failure value, and thereafter, in step P4B, the normal value of the data under test DIN is stored based on the separation processing, and the failure value of the data under test DIN is stored. It is processed (see FIG. 3B).

As a result, it becomes possible to automatically generate the test data based on the ROM-containing test pattern generating circuit by only slightly changing the circuit data. Further, there is no need to create a ROM pattern for the ROM failure input value for each product type, and the data processing is simplified. Furthermore, it is possible to significantly reduce the time required for creating the test pattern.

[0056]

Embodiments of the present invention will now be described with reference to the drawings. 4 to 10 are diagrams for explaining a test data creating apparatus and a test data creating method according to an embodiment of the present invention.

(1) Description of the First Embodiment FIG. 4 is a block diagram of a test data creation device according to each embodiment of the present invention, and FIG. 5 is a test data according to the first embodiment of the present invention. 6 and 7 are supplementary explanatory diagrams thereof, respectively.

For example, an apparatus for automatically creating the test data DOUT of the object 16 to be inspected, including the RAM and the ROM as shown in FIGS. 6A and 9A, based on the data DIN to be tested is shown in FIG. , Circuit data memory 21A, simulation data memory 21B, test data memory 21C, data creation editor 22, data conversion editor 23, data expansion editor 24, CPU (central processing unit) 2
5, a keyboard 26A, a display device 26B and a system bus 27.

That is, the circuit data memory 21A constitutes a part of the storage means 11 and stores the LSI circuit data D1 relating to the inspection object 16. The LSI circuit data D1 includes the combination circuit data D11 relating to a newly developed LSI and a storage element (hereinafter referred to as R
RAM data D3 and ROM data D4 relating to a read-only storage element (hereinafter referred to as ROM).

The simulation data memory 21B constitutes a part of the storage means 11, and includes additional circuit data D2 of the object 16 to be inspected, other control data D5 and data D to be tested.
It remembers IN. The additional circuit data D2 includes hypothetical fault inserter data D21, input searcher data D22, output checker data D23, and synchronization controller data D24. The other control data D5 includes failure point setting data D51 and signal line connection data D52.

The test data memory 21C constitutes a part of the storage means 11 and stores test data (test pattern data) DOUT necessary for the logical failure inspection of the object 16 to be inspected.

The data creation editor 22 is an embodiment of the data creation means 12 and creates the test data DOUT of the object 16 to be inspected based on the LSI circuit data D1, the additional circuit data D2 and the data under test DIN. ..

Further, the data development editor 23 constitutes a part of the data processing means 14, and is exclusively used for the test data creation processing according to the first embodiment of the present invention.
The RAM included in the object 16 to be inspected has two storage elements RAM.
1 and RAM2, and the signal pass line GL is connected between the storage elements (hereinafter also referred to as the write processing circuit A) RAM1 (hereinafter also referred to as the read processing circuit B) RAM2 (FIG. 6). (See (b)).

The data development editor 23 is shown in FIG.
As shown in (a), the assumption fault inserter 23A, the input searcher 23B, the output checker 23C, and the synchronization controller 23D, which are an example of the adding means 13, are connected to the RAM expansion circuit.

The hypothetical fault inserter 23A is an example of the hypothetical fault insertion means 13A and inserts a hypothetical fault into a test pattern generation circuit including a RAM expansion circuit. The input searcher 23B is an example of the input means 13B and supplies the data under test DIN. The output inspector 23C is an example of the output means 13C and detects the presence or absence of a hypothetical failure. The synchronization controller 23D is an example of the synchronization control means 13D, and controls the input / output of the hypothetical fault inserter 23A, the input searcher 23B, and the output checker 23C.

The data conversion editor 24 constitutes a part of the data processing means 14 and is exclusively used for the test data creation processing according to the second embodiment of the present invention and is included in the ROM 16 to be inspected. ROM as a failure processing ROM
Input converter (normal value) 22A, ROM Input converter (fault value) 22B, normal input value ROM22C, fault input value ROM22
The D / ROM output converter 22E performs conversion.

Here, the ROM input converter (normal value) 22A
Is an example of the first input means 12A, and is for inputting a normal value of the data under test DIN on the logic simulation. The ROM input converter (fault value) 22B is an example of the second input means 12B, and inputs the fault value of the data under test DIN.

The normal input value ROM 22C is an example of the first storage element ROM1 and stores the normal value of the data under test DIN. The fault input value ROM 22D is an example of the second storage element ROM2 and stores the fault value of the data under test DIN. The ROM output converter 22E is an example of the output means 12C and outputs a normal value or a failure value of the data under test DIN (see FIG. 9 (c)).

Further, the data conversion editor 24 has a hypothetical fault inserter 23A and an input searcher 23 which are examples of the adding means 13.
B, output inspector 23C and synchronous controller 23D
It is connected to M (see FIG. 10 (a)).

The CPU 25 is an embodiment of the control means 15, and includes a circuit data memory 21A, a simulation data memory 21B, a test data memory 21C, a data creation editor 22, a data expansion editor 23, a data conversion editor 24, a keyboard 26A and a display. The input / output of the device 26B and the like is controlled.

For example, in the test data creating process according to the first embodiment, the CPU 25 controls the expansion of the RAM included in the object 16 to be inspected into the two storage elements RAM1 and RAM2. Signal pass line G between RAM2
The connection control of L and the connection control of the address condition determiner 23E which determines the validity of the address value ADD designated in the storage elements RAM1 and RAM2 are performed.

Further, in the test data creating process according to the second embodiment, the CPU 25 sets the ROM included in the object 16 to be inspected to the ROM input converter (normal value) 22A, the ROM input converter (fault value) 22B, The conversion is performed by the normal input value ROM 22C, the failure input value ROM 22D and the ROM output converter 22E.

Further, in the first and second embodiments, the CPU 25 controls the connection of the hypothetical fault inserter 23A, the input searcher 23B, the output inspector 23C and the synchronization controller 23D to the RAM expansion circuit or the fault processing ROM. Alternatively, the test data DOUT is controlled based on the assumed failure set in the inspection object 16 including the ROM or the RAM.

The keyboard 26A is an example of the data input / output means 17, and when the operator activates the test data creating apparatus, the external input data D6 such as a control statement is input.
Is to be entered. Further, the display device 26B is an example of the data input / output means 17, and displays the circuit pattern and the additional circuit of the inspection target 16 as needed based on the display data D7.

The system bus 27 is the circuit data memory 21.
A, a data memory 21B for simulation, a test data memory 21C, a data creation editor 22, a data expansion editor 23, a data conversion editor 24, a CPU 25, a keyboard 26A, a display device 26B, etc. are connected and each data D1 to D7 is transmitted. Is.

As described above, according to the test data generating apparatus according to each embodiment of the present invention, as shown in FIG. 4, the circuit data memory 21A and the simulation data memory 21 are used.
B, test data memory 21C, data creation editor 22,
Data expansion editor 23, data conversion editor 24, C
A PU 25, a keyboard 26A and a display device 26B are provided, and the CPU 25 controls the generation of the test data DOUT based on the assumed failure set in the inspection object 16 including the ROM or the RAM.

For example, when the LSI circuit data D1 relating to the object 16 to be inspected including the RAM is read from the circuit data memory 21A via the keyboard 26A, the RAM is expanded by the CPU 25 into the two storage elements RAM1 and RAM2. The signal passing line GL is connected between the two storage elements RAM1 and RAM2 (see FIG. 6B).

Further, a hypothetical fault inserter 23A, an input searcher 23B, an output inspector 23C relating to signal input / output of the object 16 to be inspected.
The synchronous controller 23D is connected to the data expansion editor 23 via the CPU 25. At this time, assuming fault inserter data D21, input searcher data D22, as additional circuit data D2 from the simulation data memory 21B,
The output inspector data D23 and the synchronization controller data D24 are read out and, for example, on the inspected object 1 in the memory area.
Assumed fault inserter 23A, input searcher in RAM expansion circuit 6
23B, the output inspector 23C, and the synchronization controller 23D are connected (see FIG. 7A).

It should be noted that a hypothetical fault is inserted into an arbitrary hypothetical fault occurrence portion of the inspection object 16 via the hypothetical fault inserter 23A, and the CPU 25 allows, for example, a synchronous controller.
The address condition determiner 23E is connected to 23D (see FIG. 7).
(See (a)).

Therefore, the test data D of the object 16 to be inspected
OUT is automatically generated by the data creation editor 22.
For example, when the data to be tested DIN is supplied to the input searcher 23B of the inspected object 16 in which the assumed failure is set through the CPU 25 and the synchronous controller 23D, the presence or absence of the inferred failure of the inspected object 16 is output checked. 23C. At this time, the validity of the address value ADD designated in the two storage elements RAM1 and RAM2 is determined by the address condition determiner 23E.

As a result, the inspection target 16 including the RAM is
Data creation editor 2 based on the assumed failure set in
2 makes it possible to automatically create the test data DOUT. The test data DOUT is stored in the test data memory 21C.
The first test data creation processing of the present invention will be described in detail with reference to FIG.

Further, when the LSI circuit data D1 relating to the inspection object 16 including the ROM is read from the circuit data memory 21A, the ROM is read by the CPU 25 and the data conversion editor 24 and the ROM input converter (normal value) 22A,
ROM input converter (fault value) 22B, normal input value ROM22
C, the fault input value ROM 22D and the ROM output converter 22E are converted (see FIG. 9C).

Further, a hypothetical fault inserter 23A, an input searcher 23B, and an output inspector 23C relating to signal input / output of the object 16 to be inspected.
The synchronization controller 23D is connected to the data conversion editor 23 via the CPU 25. At this time, assuming fault inserter data D21, input searcher data D22, as additional circuit data D2 from the simulation data memory 21B,
The output inspector data D23 and the synchronization controller data D24 are read out, and, for example, in the memory area, the inspection target 1
Assumed fault inserter 23A, input searcher in fault processing ROM 6
23B, the output inspector 23C, and the synchronization controller 23D are connected (see FIG. 10 (a)).

A hypothetical fault is inserted into an arbitrary hypothetical fault occurrence portion of the inspection object 16 via the hypothetical fault inserter 23A (see FIG. 10A). Therefore, the test data DOUT of the object 16 to be inspected is automatically generated by the data creation editor 22. For example, the data under test DIN is stored in the CPU 25 in the input searcher 23B of the device under test 16 in which the assumed failure is set.
When supplied via the synchronous controller 23D, the output inspector 23C detects the presence / absence of a hypothetical failure of the inspected object 16.

At this time, the normal value of the data under test DIN is R
OM input converter (normal value) 22A, the failure value is ROM
When input to the input converter (fault value) 22B,
Both values are normal input value ROM22C, failure input value ROM22
Each of them is stored in D, and as a result, the normal value or the failure value of the data under test DIN is output from the ROM output converter 22E to the output inspector 23C.

As a result, the test data DOUT can be automatically created by the data creating means 12 based on the assumed failure set in the device under test 16 including the read-only memory element ROM. The test data DOUT is stored in the test data memory 21C, and the second test data creating process of the present invention will be described in detail with reference to FIG. ..

Next, a test data creating method according to the first embodiment of the present invention will be described with supplementing the operation of the apparatus. FIG. 5 is a flowchart for creating test data according to the first embodiment of the present invention, and FIGS. 6 and 7 show supplementary explanatory diagrams thereof.

For example, when the test data DOUT of the test object 16 including the RAM as shown in FIG. 6A is automatically created based on the test data DIN, as shown in the flow chart of FIG. At P1, input processing of the LSI circuit pattern of the inspection object 16 including the RAM is performed (see FIG. 6A).

At this time, external input data D such as a control statement
When 6 is input via the keyboard 26A, the test data creating device is activated. In addition, the circuit data memory 21
The LSI circuit data D1 such as the combination circuit data D11 and the RAM data D3 related to the inspection object 16 are read from A. The circuit pattern and the additional circuit of the inspection object 16 are displayed on the display device 26B based on the display data D7 as needed.

Further, in step P2, the internal expansion processing of the RAM included in the inspection object 16 is performed. At this time, in the internal expansion processing, the RAM included in the inspection object 16 is expanded into the storage elements RAM1 and RAM2 associated with the second time. Here, the RAM included in the object 16 to be inspected by the data development editor 23 via the CPU 25 has two storage elements RAM.
1, ram2 expanded (copied), signal line connection data D52
Based on the above, the signal passing line GL is connected between the write processing circuit A and the read processing circuit B of the RAM expansion circuit composed of both the storage elements RAM1 and RAM2 (see FIG. 6B).

Thereafter, in step P3, the RAM expansion circuit is connected to the additional circuit. At this time, the additional circuit data D2 such as the assumed fault inserter data D21, the input searcher data D22, the output checker data D23, and the synchronization controller data D24 are read from the simulation data memory 21B via the CPU 25. In addition, the data development editor 23
The input searcher 23B, the output checker 23C, and the synchronization controller 23D as shown in FIG. 7A are connected to the RAM expansion circuit via the.

Next, in step P4, a process of setting a hypothetical fault is performed on an arbitrary part of the hypothetical fault that has occurred in the inspected object 16 including the RAM subjected to the internal expansion process. At this time, in the hypothetical fault occurrence portion, the peripheral positions where the hypothetical faults occur at the same time are always selected for the two storage elements RAM1 and RAM2. Here, a hypothetical fault is inserted by the hypothetical fault inserter 23A into the test pattern generation circuit including the RAM expansion circuit based on the fault point setting data D51.

Then, in step P5, the data to be tested DIN is supplied to the object 16 to be inspected for which the assumed failure has been set. At this time, the process of supplying the test data DIN of the test object 16 is performed by designating the same address value ADD to the two storage elements RAM1 and RAM2.

For example, the data under test DIN based on the fault simulation program is supplied by the input searcher 23B via the synchronous controller 23D, and the output inspector 23C detects the presence or absence of a hypothetical fault.

Thereafter, in step P6, the test data DOUT is detected based on the detection processing of the presence or absence of a hypothetical failure of the inspection object 16.
Create the process. At this time, the detection process of the presence or absence of a hypothetical failure of the inspection object 16 is performed by the two storage elements RAM1 and RAM2.
Is performed by designating the same address value ADD to each of the storage elements ram1 and ram2
Is judged by the address condition judging unit 23E.

As a result, the test data D of the object 16 to be inspected is generated by the data creation editor 22 based on the LSI circuit data D1, the additional circuit data D2 and the data under test DIN.
OUT is automatically generated, and the test data DOUT necessary for the logical failure inspection of the inspection object 16 is stored in the test data memory 21C (see FIG. 7B).

As described above, according to the test data creating method of the first embodiment of the present invention, as shown in the flow chart of FIG. In the part where the hypothetical failure has occurred, the hypothetical failure is set in step P4, and then the data under test DIN is supplied to the object 16 to be inspected for which the hypothetical failure has been set in step P5.

For example, in step P2, the RAM included in the object 16 to be inspected is time-expanded at two times, and the step P3 is performed between the two storage elements RAM1 and RAM2 that have been expanded.
Then, the signal passing line GL is connected.

Therefore, the test data D of the test object 16 is based on the same address value ADD designated in the RAM expansion circuit reconfigured as one circuit data as a whole.
IN supply processing and detection processing for the presence or absence of assumed failure are performed. Two storage elements RAM
For 1 and RAM2, the peripheral position where the contingencies simultaneously occur is selected.

From this, in step P6, for example,
The presence / absence of a hypothetical failure is detected based on the processing of determining the validity of the address value ADD designated in the two storage elements RAM1 and RAM2. Therefore, the data under test DIN is RA once
By supplying the data to the expansion circuit to the expansion circuit, the writing process of the data to be tested DIN to the expansion circuit and the data to be tested D are performed.
It is possible to simulate a continuous operation related to IN read processing on a logic simulation.

The two processing operations are performed by the signal passing line G.
L makes them equivalent on the logic simulation,
It is possible to simultaneously generate a test pattern for writing and a test pattern for reading (see FIG. 7B).

As a result, it becomes possible to automatically create the test data DOUT for testing the peripheral circuit to be inspected, which includes the memory elements that can be read / written at any time. (2) Description of Second Embodiment FIG. 8 is a flowchart for creating test data according to the second embodiment of the present invention, and FIGS. 9 and 10 show supplementary explanatory views thereof, respectively.

For example, when the test data DOUT of the inspection object 26 including the ROM as shown in FIG. 9A is automatically created based on the test data DIN, as shown in the flow chart of FIG. At P1, the LSI circuit pattern of the inspection target 26 including the ROM is input (see FIG. 9A).

At this time, the LSI circuit data D1 such as the combination circuit data D11 and the ROM data D4 related to the inspection object 26 are read from the circuit data memory 21A. The ROM is a model MP that outputs data based on the read enable signal (enable signal) and the address ADD, for example, 0 to 15 (see FIG. 9B).

Further, as in the first embodiment, the circuit pattern and the additional circuit of the inspection object 26 are displayed on the display device 26B based on the display data D7 as needed. Further, the ROM included in the inspection target 26 in step P2
Internal conversion processing of. At this time, the ROM included in the inspection object 26 as the failure processing ROM by the data conversion editor 24 via the CPU 25 is the ROM input converter (normal value) 22A, the ROM input converter (failure value) 22B, and the normal input value. It is converted into the ROM 22C, the fault input value ROM 22D and the ROM output converter 22E (internal conversion processing).

After that, in step P3, connection processing of the additional circuit to the failure processing ROM is performed. At this time, the additional circuit data D2 such as the assumed fault inserter data D21, the input searcher data D22, the output checker data D23, and the synchronization controller data D24 are read from the simulation data memory 21B via the CPU 25. In addition, the data conversion editor 24
The input searcher 23B, the output inspector 23C, and the synchronization controller 23D are connected to the failure handling ROM via (see FIG. 10 (a)).

Next, in step P4, a process of setting a hypothetical fault is performed on an arbitrary part of the hypothetical fault where the inspected object 26 includes the fault processing ROM. At this time, the hypothetical failure occurrence portion selects the peripheral circuit of the failure processing ROM. Here, based on the fault point setting data D51, the hypothetical fault is inserted by the hypothetical fault inserter 23A into the test pattern generation circuit including the fault processing ROM.

Then, in step P5, the data to be tested DIN is supplied to the object to be tested 26 for which the assumed failure is set. At this time, in the process of supplying the data under test DIN, for example, when the data under test DIN based on the failure simulation program is supplied by the input searcher 23B through the synchronous controller 23D, the data under test DIN is returned to a normal value. And the fault value are separated and processed by the ROM input converter (normal value) 22A on the logic simulation under test data D.
The normal value of IN is input, and the ROM input converter (fault value) 22B inputs the fault value of the data under test DIN.

As a result, the normal value of the data under test DIN is stored in the normal input value ROM 22C, and the failure input value ROM 22
The failure value of the data under test DIN is stored in D. Also, R
The comparison result of the normal value and the failure value of the data under test DIN is output from the OM output converter 22E to the output inspector 23C (FIG. 9).
(See (c)).

Thereafter, in step P6, the test data DOUT is detected based on the detection processing of the presence or absence of a hypothetical failure of the inspection object 26.
Create the process. At this time, the output inspector 23C detects the presence or absence of a hypothetical failure of the inspection object 26.

As a result, the data creation editor 22 causes the test data D of the object 26 to be inspected based on the LSI circuit data D1, the additional circuit data D2 and the data under test DIN.
OUT is automatically generated, and the test data DOUT necessary for the logical failure inspection of the inspection object 26 is stored in the test data memory 21C (see FIG. 10 (b)).

As described above, according to the test data creating method of the second embodiment of the present invention, as shown in the flow chart of FIG. In step P4, the hypothetical fault is set in the hypothetical fault occurrence part of
The data under test DIN is supplied to the device under test 16 for which the assumed failure is set in step 5.

Therefore, as in the conventional example, a ROM pattern for the fault input value is created based on the ROM pattern for the normal input value (contents of the ROM of 0 or 1), and the fault output value for the fault input value is created. RO that outputs
Compared to the M model, the test data DOUT can be automatically created in a short time based on the detection process of the presence or absence of the assumed failure of the inspection object 26 in step P6.

At this time, for example, in the failure processing ROM internally converted in step P2 of the flowchart of FIG. 8, the data DIN under test is separated into a normal value and a failure value in step P5, and then the separation is performed. Based on the processing, the normal value of the data under test DIN is stored in the normal input value ROM 22C, and the fault value of the data under test DIN is stored in the fault input value ROM.
The data is stored in 22D and the comparison result of both data is output from the ROM output converter 22D (see FIG. 9C).

As a result, the test data DOUT can be automatically generated based on the ROM-containing test pattern generating circuit with only a slight change in the circuit data. Further, there is no need to create a ROM pattern for the ROM failure input value for each product type, and the data processing is simplified. Furthermore, it is possible to significantly reduce the time required for creating the test pattern.

[0116]

As described above, according to the test data creation apparatus of the present invention, the storage means, the data creation means, the data processing means, the control means and the data input / output means are provided, and the control means is read-only. Storage element or read at any time /
The test data creation control is performed based on the hypothetical failure set for the inspection target including the writable storage element.

Therefore, the readable / writable storage element is expanded into two storage elements at any time, the signal passing line is connected between the storage elements, and the input means to be inspected is set with the assumed failure. When the data to be tested is supplied through the control means and the synchronization control means, the presence or absence of a hypothetical failure of the test object is detected by the output means including the address condition determination means. From this, it becomes possible to automatically create the test data by the data creating means based on the assumed failure that is set in the object to be inspected including the storage element that can be read / written at any time.

Further, the read-only memory element is converted into the first and second input means, the first and second memory elements and the output means, and the normal value of the data under test is transferred to the first input means and the failure thereof occurs. When the values are respectively input to the second input means, both values are stored in the first and second storage elements respectively, and as a result, the normal value or the failure value of the data under test is output from the output means. It As a result, the test data can be automatically created by the data creating means on the basis of the assumed failure set in the inspection target including the read-only storage element.

Further, according to the first test data generation method of the present invention, a hypothetical fault is set in an arbitrary hypothetical fault occurrence portion of the inspection object in which the readable / writable storage element is internally developed. , And the data under test is supplied to it.

Therefore, based on the same address value designated in the RAM expansion circuit reconfigured as one circuit data as a whole, the process for supplying the data under test to be inspected and the process for detecting the presence or absence of a hypothetical failure are performed. Be seen.

From this fact, one test data is RA
By supplying the data to the M expansion circuit, it is possible to simulate the continuous operation related to the writing process of the data under test to the expansion circuit and the reading process of the data under test on the logic simulation. This makes it possible to simultaneously generate a test pattern for writing and a test pattern for reading.

Further, according to the second test data generating method of the present invention, the hypothetical fault is set in an arbitrary hypothetical fault occurrence portion of the subject to be inspected in which the read-only storage element is internally converted, and then the subject to be tested is set. The data is being processed.

Therefore, in the memory element subjected to the internal conversion processing, the data under test is separated into the normal value and the failure value,
Since the normal value and the failure value of the data under test are stored based on the separation processing, the time is shorter than that of the conventional ROM model based on the detection processing of the presence or absence of a hypothetical failure of the inspection object. In addition, it becomes possible to automatically create test data.

As a result, it is possible to simplify the process of creating the test data and significantly reduce the time required for creating the test data. This largely contributes to early commercialization of the newly developed LSI.

[Brief description of drawings]

FIG. 1 is a principle diagram of a test data creation device according to the present invention.

FIG. 2 is a principle diagram (1) of a test data creating method according to the present invention.

FIG. 3 is a principle diagram (part 2) of the test data creating method according to the present invention.

FIG. 4 is a configuration diagram of a test data creation device according to each embodiment of the present invention.

FIG. 5 is a flowchart for creating test data according to the first embodiment of the present invention.

FIG. 6 is a supplementary explanatory diagram (part 1) of the flowchart according to the first embodiment of the present invention.

FIG. 7 is a supplementary explanatory diagram (part 2) of the flowchart according to the first embodiment of the present invention.

FIG. 8 is a flowchart for creating test data according to the second embodiment of the present invention.

FIG. 9 is a supplementary explanatory diagram (part 1) of the flowchart according to the second embodiment of the present invention.

FIG. 10 is a supplementary explanatory diagram (part 2) of the flowchart according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram of a test data creating method according to a conventional example.

FIG. 12 is a supplementary explanatory diagram of a test data creating method according to a conventional example.

[Explanation of symbols]

 11 ... Storage means, 12 ... Data creating means, 13 ... Addition means, 14 ... Data processing means, 15 ... Control means, 13A ... Assumed fault insertion means, 13B ... Input means, 13C ... Output means, 13D ... Synchronous control means, RAM ... Readable / writable storage element, ROM ... Read-only storage element, DIN ... Data under test, D1 ... LSI circuit data, D2 ... Simulation data, D3 ... Other control data, DOUT ... Test data.

Claims (13)

[Claims] 1. An apparatus for automatically creating test data (DOUT) for logical failure inspection of a semiconductor integrated circuit device to be inspected (16), at least the test data of the inspected object (16). Storage means (11) for storing various data (DIN, D1, D2 to D5, DOUT) relating to the creation of (DOUT), and data creation means (DOUT) for creating test data (DOUT) of the inspected object (16) ( 12) and additional means (1) for inputting / outputting signals to / from the inspection object (16).
And a control means (15) for controlling the input / output of the storage means (11), the data creation means (12) and the data processing means (14). The control means (15) controls the read-only storage element (R
OM) or a storage element (RA that can be read / written at any time)
A test data creating device characterized by controlling creation of test data (DOUT) based on a hypothetical failure set in an object to be inspected (16) including M). 2. The test data generating apparatus according to claim 1, wherein the control means (15) has two storage elements (RAM1) that can be read / written at any time.
2) Expand to 2 storage elements (RAM1, RAM2)
A test data creation device characterized in that connection control of a signal passing line (GL) is performed therebetween. 3. The test data generating device according to claim 1, wherein the control means (15) includes the two storage elements (R).
A test data creating device characterized by controlling connection of an address condition judging means (13E) for judging validity of an address value (ADD) designated by AM1 and RAM2). 4. The test data generating apparatus according to claim 1, wherein the control means (15) inputs a normal value of the data under test (DIN), and the data under test (12A). Second input means (12B) for inputting a failure value of DIN), a first storage element (ROM1) for storing a normal value of the data under test (DIN), and a failure of the data under test (DIN) Second storage element (ROM2) for storing values
And a read-only memory element (ROM) for outputting a normal value or a failure value of the data under test (12C).
A test data creation device characterized by controlling the conversion of the test data. 5. The test data generating apparatus according to claim 1, wherein the control means (15) includes the inspection target (16).
Hypothetical fault insertion means (13A) for inserting a hypothetical fault into any of the hypothetical fault occurrence parts, an input means (13B) for supplying the data under test (DIN), and an output means (for detecting the presence or absence of the hypothetical fault). 13C) and the assumed fault insertion means (13C)
A), a test data creating apparatus characterized by controlling connection with a synchronous control means (13D) for controlling input / output of an input means (13B) and an output means (13C). 6. The test data creation device according to claim 1, wherein the storage means (1), the data creation means (12),
A test data creating apparatus, characterized in that a data input / output means (17) for assisting input / output of the data processing means (14) and the control means (15) is provided. 7. A method for automatically creating test data (DOUT) for performing a logic failure test of a semiconductor integrated circuit device, comprising at least a readable / writable memory included in the object to be tested (16). Internal expansion processing of the element (RAM), and the storage element (RAM) subjected to the internal expansion processing
The setting process of the hypothetical fault is performed on an arbitrary hypothetical fault occurrence part of the test target (16) including the test target data (DIN) is supplied to the test target (16) to which the hypothetical fault is set, A test data creation method, characterized in that a test data (DOUT) creation process is performed based on a detection process of the presence or absence of a hypothetical failure of the inspection object (16). 8. The test data generation method according to claim 7, wherein the internal expansion processing is performed by using a memory element (RAM) which can be read / written at any time and which is included in the inspection target (16).
A test data creating method characterized by performing expansion processing on one storage element (RAM1, RAM2) and connecting processing of a signal passing line (GL) between the two storage elements (RAM1, RAM2) subjected to the expansion processing. . 9. The test data creating method according to claim 7, wherein the test data (DIN) of the test object (16) is provided.
The test data generating method is characterized in that the supply process and the process of detecting the presence or absence of a hypothetical fault are performed based on the same address value (ADD) designated in the two storage elements (RAM1, RAM2). 10. The test data creating method according to claim 7, wherein the storage device having two storage elements (R
A test data generating method characterized by always selecting a peripheral position at which simultaneous faults occur simultaneously for AM1 and RAM2). 11. The test data generating method according to claim 7, wherein the detection process of the presence or absence of the assumed fault includes address values (AD) specified in two storage elements (RAM1, RAM2).
A method for preparing test data, characterized by including the processing for determining the effectiveness of D). 12. A method for automatically creating test data (DOUT) for performing a logical failure test of a semiconductor integrated circuit device, comprising at least a read-only memory element (ROM) included in the object to be tested (16). Internal conversion processing is performed, and setting processing of a hypothetical fault is performed on an arbitrary hypothetical fault occurrence portion of the inspection target (16) including the storage element (ROM) subjected to the internal conversion processing. Inspection target (1
6) The test data (DIN) is supplied to 6), and the test data (DOUT) is created based on the detection process of the presence or absence of the assumed failure of the test object (16). How to make. 13. The test data generating method according to claim 13, wherein the memory element (ROM) subjected to the internal conversion process separates the data under test (DIN) into a normal value and a failure value, and performs the separation. Data under test (DIN) based on processing
2. A method for creating test data, characterized in that the normal value storage process and the failure value storage process of the data under test (DIN) are stored.