JPH0574211B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a mask alignment device that aligns the relative positional relationship between a semiconductor wafer and a mask, and particularly relates to a mask alignment device that aligns the relative positional relationship between a semiconductor wafer and a mask, and particularly relates to a mask alignment device that aligns the relative positions of a semiconductor wafer and a mask. This relates to a mark detection method.

[Background of the invention]

First, a stepper, which is a typical reduction projection aligner, will be explained with reference to FIG. The stepper normally uses a master reticle 1 with a magnification of 10 times, projects a fine pattern onto a wafer 3 with a reduction lens 2, and performs intermittent exposure for each chip. As shown in FIG. 2, the wafer 3 has a 1.
An alignment mark 5 is formed on the master reticle, and the position of the wafer 3 is measured by a detection optical system 7 and a signal processing circuit 8 through the alignment mark 6 on the master reticle. When the relative position of the wafer 3 with respect to the master reticle 1 is calculated, the servo mechanism 9 moves the wafer 3
Each chip is moved to a predetermined position and exposed.

In Fig. 2, the width of the scribe line 10 is generally 100 to 200 μm, and the width of the scribe line 10 is generally 100 to 200 μm.
13 are adjacent to each other, and in order to detect the alignment mark 5, it is essential to distinguish it from the IC pattern 13. The above technology is also necessary for 1:1 projection type aligners in order to achieve hybrid use with steppers. In addition, the alignment marks of contact type aligners are also becoming increasingly miniaturized.

The shape of the alignment mark differs depending on the manufacturer, but in order to detect the position in _the Scan and detect in _two directions. The scanning of the alignment mark 5 in the 45° direction optically emphasizes the pattern in the 45° direction, and the 90°, which occupies most of the IC pattern 13.
This is to attenuate the 180° pattern image. Here, in order to avoid including the IC pattern 13 in the scanning range, it is sufficient to set the scanning range to the extent shown by A, but pre-alignment (wafer orientation flat before alignment mark detection) It is difficult to initially position the alignment mark (wafer) within this scanning range due to the accuracy of the rough positioning operation (using the wafer). That is, in consideration of pre-alignment accuracy, a scanning range as shown in B is required, and the IC pattern 13 is also included in the scanning range. If scanning detection is performed in such a state, it is possible to attenuate patterns other than 45°, but it is impossible to eliminate them, so a signal waveform as shown in FIG. 3a is obtained. In one-dimensional detection, a binarization method using a threshold value is common. Here, the third
In Figure a, when threshold value b is set to detect the alignment mark detection signal 11, the IC pattern 12 is also binarized as shown in Figure c.
It becomes difficult to distinguish.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an alignment mark detection method that eliminates the drawbacks of the above-mentioned conventional techniques, accurately recognizes alignment marks on a wafer, shortens alignment time, and improves throughput. It is in.

[Summary of the invention]

The alignment mark detection method according to the present invention stores the detection waveform of the alignment mark on the wafer in advance, and sequentially superimposes the detected waveform on the waveform to be detected. The idea is to recognize the alignment mark on the wafer by detecting its position.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings. FIG. 4 is a block diagram of one embodiment, and FIG. 5 is a supplementary explanatory diagram showing the operation.

In FIG. 4, 14 is a wafer, 15 is an optical system including an objective lens, 16 is a half mirror, and 17 is a wafer.
18 is an illumination light, 18 is a projected image, 19 is a cylindrical lens, 20 is a linear image sensor, 21 is an A/D converter, 22, 24, 28 are storage circuits, 2
3 is an extraction circuit, 25 is an arithmetic circuit, 26 is an absolute value circuit, 27 is an adder, 29 is a comparison circuit, 30 is a decoder circuit, and 31 is a timing circuit.

An optical system 15 including illumination light 17, a half mirror 16, and an objective lens shows a general principle configuration of a pattern detection optical system. The light is enlarged (or reduced) by an optical system 15 and detected by an optical element. Here, an image 18 of a minute target at 45° with respect to the scribe line on the wafer 14 is shown.
In order to strengthen the image 18, a cylindrical lens 19 is provided in a direction perpendicular to the image 18, and a linear image sensor 20 is placed as a photoelectric element at the imaging position of the cylindrical lens 19.

First, the wafer 14 is manually positioned so that the alignment mark 18 is at a predetermined position on the linear image sensor 20 . This fixes the relative positional relationship between the optical system 15, the cylindrical lens 19, and the image sensor 20, and installs a reference mark indicating the predetermined position in a microscope for observing the alignment mark. This is possible if it corresponds to the position of the pixel. In this state, the scanning detection signal obtained from the linear image sensor 20 is digitized for each pixel by the A/D converter 21 and stored in the storage circuit 22. Here, since the position of the image 18 of the alignment mark is clear on the pixels of the image sensor 20, the extraction circuit 23 extracts the detection signal of the alignment mark 18 from the information of all the pixels stored in the storage circuit 22. This is taken out and newly stored in the storage circuit 24 as reference data for the alignment mark 18. Figure 5 a, 35
indicates reference data, and alignment mark 1
The range of m pixels left and right from the center is of 8 is defined as the storage range of the reference data. Here, m is determined from the pattern width of the alignment mark 18 and the magnification of the optical system 15, and may be set at the first pixel forming the base of the pattern. If the pixel is i and the scanning signal when storing the reference data (that is, data of all pixels stored in the storage circuit 22) is Vs(i), the reference data 35 is Vs(i) (i=is-m,..., is,...is+m)
It can be expressed as The above reference data storage operation is performed for each wafer process, and the reference data 14 is stored in the storage circuit 24 for each process.

Similarly, the A/D converter 21 detects alignment marks during alignment using the linear image sensor 2.
The output of 0 is digitized across all pixels and stored in the storage circuit 22. 5a shows the output (V(i)) of this linear image sensor 20. If the number of pixels for one scan is g and the number of digital bits per pixel is b, then g×
b bits of data will be stored. When data V(i) for one scan is stored in this way,
The timing circuit 31 reads the reference data Vs(i) from the memory circuit 24 and the memory circuit 22, and the same number (2m+1) of consecutive detected data V(i) as shown in 37 shown in FIG. 5a. , the following calculations are performed in the subsequent circuits.

M(i)= _n Σ Σ ^k=-m |Vs(is+k)−{V(i+k)+C(i)}|...
...(1) C(i)=Vs(is-m)-V(i-m) M(i) is exactly the first pixel V(i-m) of the detected pattern V(i) is the reference data Vs( The entire detected pattern V(i) is shifted up and down by C(i) so that the first pixel V(is-m) of i) matches the reference data Vs(i) as shown in 38 in FIG. 5b. This represents the area of the mismatched portion when the detected pattern V(i) and V(i) are overlapped. Arithmetic circuit 25
is V(s)(is+k)−{V(i+k) in equation (1)
)
+C(i)}, the absolute value circuit 26 converts the above equation into an absolute value, and the adder circuit 27 adds the above absolute values to obtain the area M(i). The timing circuit 31 also has the function of updating i in equation (1), and advances the movement of the detected pattern 40 in the direction shown by 39 shown in FIG. At i, the area M(i) obtained from the arithmetic circuit 25, absolute value circuit 26, and addition circuit 27 is stored in the storage circuit 28.
Here, the movement interval of the section 40 does not necessarily have to be one pixel, but may be every several pixels as long as it is sufficient to know the approximate position of the alignment mark.
When the area M(i) between each position i in the scanning signal 36 and the reference data 35 is determined in the storage circuit 28 in this way, the comparison circuit 29 calculates the area
Compare the size of Mi and detect the minimum value MIN [M(i)] from the area M(i). Here, if the address for storing the area M(i) in the storage circuit 28 is associated with the position i of the detected pattern 37, then the position it( MIN[M(i)]=M(it)) is calculated as follows when the comparator circuit 29 detects MIN[M(i)].
This can be detected by interpreting the address in the storage circuit 28 where the data is stored using the decoder circuit 30. In this way, finding the minimum value of the area M(i) as shown at 41 in FIG. By obtaining it to the decoder circuit 30, the desired center position of the alignment mark 18 can be known.

In FIG. 4, the circuit after the A/D converter 36 may be replaced with a computer, and software processing corresponding to the above operation may be performed.

〔Effect of the invention〕

As explained above, according to the present invention, a mask alignment apparatus can accurately recognize the position of a minute alignment mark on a wafer without being bothered by surrounding circuit patterns, thereby shortening alignment time and improving the efficiency of the apparatus. Throughput can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a stepper to explain the conventional technique, FIG. 2 is an explanatory diagram showing a scanning detection method for minute alignment marks, FIG. 3 is an explanatory diagram showing a conventional detection method, and FIG. The figure is a block diagram of one embodiment of the present invention, and FIG. 5 is a supplementary explanatory diagram of the operation related to FIG. 4. 19... Cylindrical lens, 20... Linear image sensor, 21... A/D converter, 2
2, 24, 28...Storage circuit, 26...Absolute value circuit, 27...Adder, 29...Comparison circuit, 30...
...Decoder circuit, 31...Timing circuit.

Claims (1)

[Claims] 1 In a mask alignment device that has the function of aligning the relative positional relationship between the wafer and the mask by scanning and detecting minute alignment marks provided on the semiconductor wafer and the mask using an image sensor, The alignment marks on the wafer are manually positioned, only the detected waveforms of the alignment marks are memorized, and these are sequentially superimposed over the entire scanning waveform during alignment.
Find the area of the mismatched portion of the two waveforms caused by superimposition as the sum of the absolute values of the differences in the peak values of opposing pixels, and find the position on the scanning waveform that gives this area a minimum value. An alignment mark detection method characterized by detecting the position of a minute alignment mark on a wafer.