JPH0574219B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method for manufacturing a layered structure having non-nested vias, for example, for manufacturing a layered structure used for forming electrical connections in an integrated circuit. It's about how to do it.

B. Problems to be Solved by the Prior Art and the Invention In an integrated circuit, it is necessary to form a layered structure having metals at various level heights, and the metals have vias between them, that is, metal-to-metal connections. It defines the division.

There are three factors that determine how the metal layers at each level are defined. These three factors are:

(1) Metal-to-metal spacing (m) (2) Via dimensions (v) (3) Metal enclosure width around the via (s) The metal pitch, which is related to the overall packing density, is equal to (m + v + 2s).

Typically, there are two conditions that require the via to be surrounded by metal on both the first level metallization and the second level metallization. First, if vias are not included within the first level metallization, there will usually be a gap around the first level metal, so that the second
Difficulties arise in encasing level metal steps within vias. These difficulties severely reduce the metal thickness connecting between the first and second levels of metal, resulting in premature failure of the layered structure during use. Second, if the via surround is omitted, problems arise if the second level metallization does not completely cover the via due to alignment errors. If coverage is not complete, the first level metal may be exposed within the via and etched away during the etching process used to define the second level metal. In this case, the thickness of the first level metal may be reduced too much, again resulting in premature failure of the structure during use.

It is an object of the present invention to eliminate the need for surrounds for vias, removing this factor from the above equation, and thus greatly improving metallization packing density.

C. Means for Solving the Problems The present invention is a method for manufacturing a layered structure having non-nested vias, which comprises: forming a spacer layer on a substrate; forming a separation layer on the spacer layer; forming a first masking pattern on the separation layer, the pattern defining a field region in a first metal layer; and etching the spacer layer and the separation layer according to the first masking pattern. forming an opening in the spacer layer; depositing a first sputtered metal layer in the etched spacer layer and the formed opening; and over the first sputtered metal layer. depositing an etch barrier layer on the first masking pattern in the field region, the first sputtered metal layer, and dissolving the separation layer to remove the etch barrier layer; forming a structure having a first metallization pattern of a layer and a first metallization pattern of the etch barrier layer, wherein depositing the first sputtered metal layer and dissolving the separation layer form a substantially planar metallization pattern. applying a passivation layer over the spacer layer and the first metallization pattern, the step being adapted to provide a structure with a surface to facilitate subsequent layer deposition; depositing an insulating layer on the passivation layer; forming a second masking pattern on the insulating layer; and depositing the first metallization pattern in accordance with the second masking pattern. exposing an etch barrier layer of the insulating layer, the passivation layer being adapted to protect the spacer layer in the field region; and a second sputtered metal layer on the insulating layer. depositing a second sputtered metal layer in contact with the etch barrier layer of the first metallization pattern exposed by etching according to the second masking pattern; forming a third masking pattern on the second sputtered metal layer; etching the second sputtered metal layer in accordance with the third masking pattern;
creating a second metallization pattern on the insulating layer having non-nested vias extending into contact with the first metallization pattern.

Preferably, the metal layer is deposited by magnetron sputtering.

The separation layer and spacer layer can be etched by plasma etching.

Preferably, the plasma etch is an oxygen plasma etch.

Via formation and second level metallization formation can be performed by the methods described in our patent application Ser. No. 8,309,341 (Integrated Circuit Processing Methods). The disclosure in this patent application is incorporated herein by reference.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

D Example Referring to Figures 1 and 2, for nested and non-nested vias, the spacing between metal to metal (m), via dimensions (v), metal surround around vias (s), minimum metal Width (w) and gap between vias
(g) is exemplified. In the case of the nested vias illustrated in Figure 1, the metal pitch associated with the overall packing density within the integrated circuit is (m+
v+2s). In the case of non-nested vias as illustrated in FIG. 2, the metal pitch is equal to the greater of (m+w) or (v+g).

Comparing FIG. 1 and FIG. 2, it can be seen that the via pitch in the case of non-nested vias is smaller than the pitch in the case of nested vias. however,
Due to alignment errors present in current via forming methods, non-nested vias are more prone to defects in the resulting layered structure, as discussed above.

FIG. 3 illustrates the problem that can occur if the vias are not included within the first level metallization. A gap 2 is formed around the first level of metal, which creates a steep and deep via, making it extremely difficult to deposit a second metal layer into this via. Often the second metal layer contains areas of extremely reduced metal thickness, and the presence of microcracks is not uncommon.

Referring now to FIG. 4, this figure is divided into five parts: FIG. 4a, FIG. 4b, FIG. 4c, FIG. 4d, and FIG. 4e.

Referring to Figure 4a, polyimide is coated onto a suitable substrate such as silicon and imidized to provide a spacer layer 4 for the first metal raised layer. A thin organic film in the form of a photoresist film is stretched over the spacer layer 4 and acts as a separating layer 6 for the uplift process. An aluminum masking layer 8 is then deposited over the isolation layer 6 in the areas where it is desired to remove metal within the first layer metal.
The field areas of the first layer metal are contoured in this masking layer 8, ie the masking layer 8 is etched where the first layer metal is required to form a masking pattern.

Referring to FIG. 4b, vias are formed in the spacer layer 4 by etching the isolation layer 6 and the spacer layer 4 through the masking pattern in the masking layer 8 using oxygen plasma etching. A first layer metal 10 is then deposited by magnetron sputtering. The first layer metal is essentially pure or doped aluminum coated with a thin chrome layer to create the etch barrier layer 12. As can be seen in FIG. 4b, at this stage of the process, the via includes a first metal layer 10 covered by an etch barrier layer 12.

Referring now to FIG. 4c, elevation is performed by dissolving the separation layer 6 in a suitable solvent and floating the masking layer 8 and first layer metal 10 and etch barrier layer 12 over the field area. is applied, resulting in a first level of metallization and exposing the surface of the spacer layer 4 (this is the structure with the first metallization pattern). A thin silicon passivation layer 14 can then be deposited over the spacer layer 4 and the remaining first layer metal 10 and etch barrier layer 12. Said passivation layer 14 serves to protect the spacer layer 4 in later stages of the process. The passivation layer 14 can be 25 angstroms thick and can also be composed of other materials, such as titanium.

An insulating layer 16 is then deposited on the passivation layer 14 and imidized. The insulating layer 16 may be comprised of any suitable insulating material, such as polyimide. When the insulating layer is imidized,
The silicon passivation layer is usually converted to silicon oxide. A masking pattern is then formed on the insulating layer 16, and the insulating layer 16 and the underlying passivation layer 14 are etched according to the masking pattern, such that the etch barrier layer 12 in the vias is removed from the passivation layer 14. and exposed through the insulating layer 16. The passivation layer 14 can be removed from within the via by wet etching or back sputtering. Through the above steps, the structure shown in FIG. 4d of the accompanying drawings is obtained.

A second level metal layer 18 is then deposited over the structure shown in FIG. 4d, and a chrome etch barrier layer 12 connects the second level metal 18 with the first level metal, as shown in FIG. 4e. Connections with 10 are made in vias.

A masking pattern is then formed on the second level metallization 18, and the second level metal is etched through the masking pattern to remove unwanted metal in the field areas of the second level metallization layer. This is the step to create the second metallization pattern). The purpose of the chrome etch barrier layer 12 will become clear below. Due to alignment errors, the masking pattern used to enable selective etching of the second level metal 18 may not precisely align with the vias. If this inconsistency occurs,
When the second level metal 18 is etched, it appears as shown in Figure 4e.

The presence of the etch barrier layer 12 prevents the first level metal 10 from being etched in the region 20, thus preventing undue reduction in the thickness of the first level metal as experienced in current methods. To prevent this from occurring.

E. Effects of the Invention The method of the present invention provides a reliable method of achieving high density multi-level metallization layers by using non-nested vias. Since the metallization pitch equation does not include any factors for via enclosure, metallization pack density is significantly improved. The method also provides a solution to the first level metal damage and via step covering problems commonly experienced when manufacturing non-nested vias with current processing methods.

The method of the present invention is particularly applicable to providing oxide-blocked ^12L integrated circuits, where in current technology metallization pack density limits circuit density. However, the present invention can also be used in most dual level metallization applications to obtain similar benefits. The method of the invention can also be used with more than one level of metal.

It should be understood that the embodiments of the invention described above with reference to the accompanying drawings have been given by way of example only and that various modifications are possible. Thus, for example, the masking layer 8 can be made of a metal other than aluminum, and the plasma etching of the separation layer 6 and the spacer layer 4 can be a plasma etching other than an oxygen plasma etching. The first layer metal is preferably aluminum or doped aluminum, but other metals can also be employed. Furthermore, although the first layer metal is preferably covered with chrome, other metals may be used in this case as well.

[Brief explanation of the drawing]

FIG. 1 illustrates nested vias and is used to illustrate metallization layout regulations. FIG. 2 illustrates non-nested vias and is used to illustrate metallization layout regulations. FIG. 3 illustrates problems that can occur in the second level metal deposit if the vias are not included within the first level metallization.
FIG. 4 illustrates a method of forming a via according to the present invention. 4... Spacer layer, 6... Separation layer, 8... Masking layer, 10... First level metal, 12... Etch barrier layer, 14... Passivation layer, 16... Insulating layer, 18... Third layer 2nd level metal.

Claims (1)

[Claims] 1. A method for manufacturing a layered structure having non-nested vias, comprising: forming a spacer layer on a substrate; forming a separation layer on the spacer layer; and a first metal layer. forming a first masking pattern on the separation layer, the first masking pattern defining a field region; etching the spacer layer and the separation layer according to the first masking pattern to form a first masking pattern on the separation layer; forming an opening; depositing a first sputtered metal layer over the etched spacer layer and the formed opening; and depositing an etch barrier layer over the first sputtered metal layer. depositing the first masking pattern in the field region, the first sputtered metal layer, and the etch barrier layer by dissolving the separation layer to remove the first metal layer and the etch barrier layer; creating a structure having a first metallization pattern of layers, wherein depositing the first sputtered metal layer and dissolving the separation layer have a substantially planar surface; depositing a passivation layer over the spacer layer and the first metallization pattern, the step being adapted to provide structure to facilitate subsequent layer deposition; , depositing an insulating layer on the passivation layer; forming a second masking pattern on the insulating layer; and depositing an etch barrier layer of the first metallization pattern in accordance with the second masking pattern. exposing, the passivation layer being adapted to protect the spacer layer in the field region; and depositing a second sputtered metal layer on the insulating layer. the second sputtered metal layer extends into contact with the etch barrier layer of the first metallization pattern exposed by etching according to the second masking pattern; forming a third masking pattern on the second sputtered metal layer; etching the second sputtered metal layer according to the third masking pattern;
creating a second metallization pattern on the insulating layer having non-nested vias extending into contact with the first metallization pattern.