JPH0574331A - Semiconductor electron emitter - Google Patents

Abstract

(57) [Summary] [Purpose] With the simplification of the device structure and manufacturing process,
Enables high-speed device operation. [Structure] A high concentration P-type semiconductor substrate 101 is provided with a high concentration P
The type semiconductor region 105 and the P-type semiconductor region 104 which supplies carriers to the high-concentration P-type semiconductor region 105 are arranged in contact with each other, and the high-concentration P-type semiconductor regions 105 and P
The P-type semiconductor region 103 and the low-concentration P-type semiconductor region 102 are arranged outwardly around the type semiconductor region 104, and the high-concentration P-type semiconductor region 105 is formed on the element surface.
A Schottky electrode 108 which is a metal film forming a Schottky barrier junction with is arranged. The relationship between the carrier concentrations of the respective semiconductor regions is high-concentration P-type semiconductor region 105>
P-type semiconductor region 104> P-type semiconductor region 103> low-concentration P-type semiconductor region 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor electron-emitting device, and more particularly to a semiconductor electron-emitting device which causes avalanche breakdown to emit hot electrons.

[0002]

2. Description of the Related Art Among conventional semiconductor electron-emitting devices, devices using an avalanche breakdown mechanism include, for example, US Pat. No. 4,259,678 and US Pat. No. 4,303,930.
What is described in the issue is known. In these semiconductor electron-emitting devices, a P-type semiconductor layer and an N-type semiconductor layer are formed on a semiconductor substrate, and cesium or the like is attached to the surface of the N-type semiconductor layer to lower the work function of the surface, thereby reducing electrons. The discharge part is formed. Then, a reverse bias voltage is applied to both ends of the PN junction formed by the P-type semiconductor layer and the N-type semiconductor layer to cause avalanche breakdown, so that electrons are hotened and the electrons are emitted from the electron emission portion and are perpendicular to the surface of the semiconductor substrate. The electron is emitted in the direction.

Separately, as disclosed in JP-A-01-220328, a P-type semiconductor and a metal material, or a P-type semiconductor and a metal compound form a Schottky barrier junction, and both ends of the Schottky barrier junction are formed. There is a method in which a reverse bias voltage is applied to cause avalanche breakdown, so that electrons are hotened and electrons are emitted from an electron emission portion in a direction perpendicular to the semiconductor substrate surface.

The conventional semiconductor electron-emitting device described above has a P
When a reverse bias voltage is applied across the N-junction or the Schottky barrier junction, avalanche breakdown occurs in the high-concentration P-type semiconductor region where the depletion layer width is thinnest, and electrons with high energy generated there are generated from the solid surface. It is to be released to the outside. However, PN
Since the shape of the depletion layer around the junction or the Schottky barrier junction has a radius of curvature determined by the carrier concentration of the semiconductor and the applied voltage, the electric field concentrates more than other portions of the depletion layer. Therefore, at an applied voltage lower than the avalanche breakdown that is originally required in the high-concentration P-type semiconductor region, breakdown or current leakage occurs around the depletion layer, deteriorating the device characteristics.

In the electron-emitting device having the PN junction or the Schottky barrier junction, the carrier concentration of the P-type semiconductor around the high-concentration P-type semiconductor region that causes avalanche breakdown is reduced to increase the radius of curvature around the depletion layer. Although it is possible to prevent breakdown at a low voltage there, the electric resistance value between the electrode for supplying carriers and the high-concentration P-type semiconductor region causing avalanche breakdown is increased, and the operation of the device is increased. Not only the voltage rises,
The problem of deterioration of element characteristics due to generation of Joule heat occurs.

Therefore, in the conventional device, it is inconvenient to extremely reduce the carrier concentration in the P-type semiconductor region around the high-concentration P-type semiconductor region. The high-concentration N-type semiconductor guard ring structure is formed so as to be concentric with the region. As a result, a depletion layer is formed continuously from the high-concentration P-type semiconductor region to the outside with the P-type semiconductor region and the high-concentration N-type semiconductor region, and the outermost radius of curvature is formed to be large, so that the depletion layer is surrounded. The breakdown and current leakage were prevented.

[0007]

In the device structure of the conventional semiconductor electron-emitting device described above, ion implantation or thermal diffusion for forming the ring-shaped N-type semiconductor region (guard ring structure) at a high concentration is performed. Manufacturing process and its high concentration N
A step of forming an ohmic junction electrode for applying a voltage to the guard ring of the type semiconductor is required, and there is a problem that the manufacturing process becomes complicated.

Further, a large area is required for forming the guard ring and its ohmic contact electrode, and it has been difficult to miniaturize the element.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and provides a small-sized semiconductor electron-emitting device which enables the device structure and manufacturing process to be simplified and the device operation to be speeded up. The purpose is to do.

[0010]

The semiconductor electron-emitting device of the present invention has a semiconductor electron-emitting device that has an electron-emitting portion composed of a Schottky barrier junction of a metal material or a metal compound material and a semiconductor and emits electrons from a solid surface. In the device, the electron emission portion includes a first P-type semiconductor region that forms the Schottky barrier junction and causes avalanche breakdown.
Furthermore, a second P-type semiconductor region located around the first P-type semiconductor region, a third P-type semiconductor region located around the second P-type semiconductor region, and the first P-type semiconductor region located around the second P-type semiconductor region. A fourth P-type semiconductor region for supplying carriers to the P-type semiconductor region, and the carrier concentration relationship between the first to fourth P-type semiconductor regions is (first P-type semiconductor region)> (Fourth P-type semiconductor region)
> (Second P-type semiconductor region)> (third P-type semiconductor region) or (fourth P-type semiconductor region) ≧ (first P-type semiconductor region)
> (Second P-type semiconductor region)> (third P-type semiconductor region)

Further, the semiconductor electron-emitting device of the present invention is N
In a semiconductor electron-emitting device that has an electron-emitting portion formed of a PN junction between a p-type semiconductor and a p-type semiconductor and emits electrons from a solid surface, the electron-emitting portion includes an n-type semiconductor region located on the solid surface. A first P-type semiconductor region that forms a PN junction with the N-type semiconductor region to cause avalanche breakdown, and further, a second P-type semiconductor region located around the first P-type semiconductor region. A third P-type semiconductor region located around the second P-type semiconductor region, and a fourth P-type semiconductor region for supplying carriers to the first P-type semiconductor region. , The first to fourth P
The relationship between the carrier concentrations of the n-type semiconductor region and the n-type semiconductor region is (N-type semiconductor region)> (first P-type semiconductor region)> (fourth P-type semiconductor region)> (second P-type semiconductor) Area)>
(Third P-type semiconductor region) or (N-type semiconductor region)> (Fourth P-type semiconductor region) ≧ (First P-type semiconductor region)> (Second P-type semiconductor region)>
(Third P-type semiconductor region).

[0012]

The present invention takes the following means in order to solve the above problems.

In a semiconductor electron-emitting device, a second P-type semiconductor region having a low carrier concentration and a third P-type semiconductor having a lower carrier concentration are provided around a high-concentration first P-type semiconductor region which causes avalanche breakdown. And a region. As a result, the depletion layer can be formed to have the thinnest shape in the first P-type semiconductor region where the electric field can be easily concentrated. Therefore, it becomes possible to efficiently cause the avalanche breakdown only in the first P-type semiconductor region. Further, the series resistance value of the semiconductor electron-emitting device is set by setting the path for supplying carriers to the first P-type semiconductor region to the fourth P-type semiconductor region having a carrier concentration higher than that of the second P-type semiconductor region. Is reduced.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a Schottky barrier junction type semiconductor emitting device according to a first embodiment of the present invention.

The semiconductor electron-emitting device of this embodiment has a cylindrical first, substantially central portion on a high-concentration P-type semiconductor substrate 101.
The high-concentration P-type semiconductor region 105, which is the P-type semiconductor region, and the P-type semiconductor region 104, which is the fourth P-type semiconductor region that supplies carriers to the high-concentration P-type semiconductor region 105, are arranged in contact with each other, Furthermore, the high-concentration P-type semiconductor region 10
5 and the P-type semiconductor region 104, the P-type semiconductor region 103 that is the second P-type semiconductor region and the low-concentration P-type semiconductor region 102 that is the third P-type semiconductor region are formed concentrically toward the outside. And a Schottky electrode 108, which is a metal film that forms a Schottky barrier junction with the high-concentration P-type semiconductor region 105, on the element surface.

Further, in the semiconductor electron-emitting device of this embodiment, the ohmic junction electrode 106 for the high-concentration P-type semiconductor substrate 101 and the electrode wiring 109 for the Schottky electrode 108 for applying a reverse voltage to the Schottky barrier junction. And the reverse voltage is applied to the power source 1
It is applied from 10.

The electrode wiring 109 has the above-mentioned P
In order to prevent a short circuit with each semiconductor region of the mold, the Schottky electrode 108 is in contact with the insulating film 107 formed on the low concentration P-type semiconductor region 102. In addition, 111 in the figure
Shows the shape of the edge of the depletion layer when the reverse voltage is applied, and 112 shows the region where avalanche breakdown occurs when the reverse voltage is applied.

The electron emission process in the semiconductor electron emission device using the Schottky barrier junction will be described with reference to FIG.

By applying a reverse bias voltage to the Schottky diode formed by forming a Schottky barrier junction with the P-type semiconductor, the bottom E _C of the conduction band of the P-type semiconductor has a vacuum level E of the metal electrode forming the Schottky barrier. _The energy level becomes higher than _VAC and avalanche breakdown occurs.
The electrons generated by the avalanche breakdown are semiconductor-
Energy higher than the lattice temperature is obtained by the electric field in the depletion layer generated at the metal electrode interface, and the energy is injected from the P-type semiconductor to the metal electrode forming the Schottky barrier junction. Electrons having an energy larger than the work function of the surface of the metal electrode forming the Schottky barrier junction are emitted into the vacuum. Therefore, as described above, treating the metal electrode surface with a low work function leads to an increase in electron emission amount.

An example of a specific manufacturing process of the semiconductor electron-emitting device shown in FIG. 1 will be described below.

(1) Zinc (Zn) -doped high-concentration P-type semiconductor substrate 101 (G) having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³
A low-concentration P-type GaAs semiconductor layer having a beryllium (Be) concentration of 1 × 10 ¹⁵ cm ⁻³ or less was grown to a thickness of 0.6 μm on aAs) by the molecular beam epitaxial growth (MBE) method. This low-concentration P-type GaAs semiconductor layer will later become the low-concentration P-type semiconductor region 102.

(2) In the region corresponding to the P-type semiconductor region 103, the Be concentration is approximately 2 × 10 ¹⁷ cm ⁻³ from the surface of the low-concentration P-type GaAs semiconductor layer to the high-concentration P-type semiconductor substrate 101. Focused ion beam (F
Be ions accelerated to 160 keV and 40 keV by the IB) implantation method were sequentially implanted. Further, in the regions corresponding to the P-type semiconductor region 104 and the high-concentration P-type semiconductor region 105, the Be concentration is 1 by the FIB implantation method.
B so as to be × 10 ¹⁸ cm ^-3 and 2 × 10 ¹⁸ cm ^-3
e ions were implanted.

(3) On the surface of the low-concentration P-type GaAs semiconductor layer implanted with Be ions as described above, SiO ₂ as a cap material is sputtered to a thickness of about 0.1 μm.
After the deposition, the injection part was activated by heat treatment at 850 ° C. for 10 seconds.

By the above implantation step (2) and one heat treatment step (3), the high-concentration P-type semiconductor region 105 and the P-type semiconductor region 10 which are the first to fourth P-type semiconductor regions are formed.
3, 104 and the low-concentration P-type semiconductor region 102 can be formed, and the manufacturing process can be simplified as compared with a conventional element having a high-concentration N-type guard ring and its ohmic junction electrode. It was

The high-concentration P-type semiconductor region 105, the P-type semiconductor regions 103 and 104, and the low-concentration P-type semiconductor region 1
The carrier concentration relationship of 02 is high-concentration P-type semiconductor region 105 (first P-type semiconductor region).
> P-type semiconductor region 104 (fourth P-type semiconductor region)> P
Type semiconductor region 103 (second P-type semiconductor region)> low-concentration P-type semiconductor region 102 (third P-type semiconductor region).

[0027] (4) Next, after removing the SiO ₂ film for the heat treatment described above, the thickness of SiO ₂ as the insulating film 107 is 0.
A film having a thickness of 5 μm is formed. In addition, the high-concentration P-type semiconductor substrate 10
Gold (Au) / chromium (Cr) is vacuum-deposited on the back surface of No. 1 and heat-treated at 350 ° C. for 5 minutes to form the ohmic bonding electrode 106.
Formed.

(5) After forming the opening of the electrode wiring 107 to form the Schottky barrier junction by ordinary photolithography, the P-type semiconductor region 103 and the high-concentration P-type semiconductor region 105 made of a P-type GaAs semiconductor are formed. And tungsten (W) is selected as a material for forming a Schottky barrier junction, and a thickness of 8 n is formed in the opening by electron beam evaporation and ordinary photolithography.
m Schottky electrode 108 was formed.

(6) Aluminum was vacuum-deposited on the junction between the insulating film 107 and the Schottky electrode 108, and the electrode wiring 109 was formed by the usual photolithography method.

[0030] Such a semiconductor electron emitting device manufactured by the established degree of vacuum of about 1 × vacuum chamber was maintained at 10 ^{over 7} Torr, ohmic junction electrode 1 by the power source 110
When 7V was applied between 06 and the electrode wiring 109,
Schottky electrode 1 above the high-concentration P-type semiconductor region 105
An electron emission of about 15 pA was observed from the 08 surface. When the applied voltage (device voltage) was sequentially increased to 10 V, the electron emission amount (emission current) was also gradually increased to about 100 pA as shown in FIG. It is considered that the depletion layer 111 at the time of applying the device voltage is expanded by about 0.04 μm from the Schottky barrier interface with the Schottky electrode 108 in the high concentration P-type semiconductor region 105. The electric field is most concentrated in the avalanche region 112 of the high concentration P-type semiconductor region 105, and avalanche breakdown occurs efficiently in this region.

Under the above manufacturing conditions, only the Be concentration of the P-type semiconductor region 104, which is the fourth P-type semiconductor region for supplying carriers to the high-concentration P-type semiconductor region 105, which is the first P-type semiconductor region, is changed. FIG. 4 shows the electric characteristics when a semiconductor electron-emitting device manufactured by changing the size to 3 × 10 ¹⁸ cm ⁻³ was installed in the same vacuum chamber. A device voltage 5 is applied to the semiconductor electron-emitting device by the power supply 110.
When V was applied, about 20 pA (emission current) of electron emission was observed from the surface of the Schottky electrode 108 above the high-concentration P-type semiconductor region 105. Further, when the device voltage was sequentially increased to 7 V, the emission current was also sequentially increased to about 100 pA.

Further, in the present embodiment, the electrode wiring 109
It is possible to regulate the flight direction and kinetic energy of the electrons emitted from the electron emission portion by providing another electrode on the top with an insulating film and setting a potential difference between the electrode and the electrode wiring 109. Becomes

As described above, by changing the carrier concentration of the P-type semiconductor region 104, it is possible to define the current-voltage characteristics of the semiconductor emitting device. Further, by decreasing the resistance value of the P-type semiconductor region 104, the series resistance value of the element can be decreased and the operation speed can be increased.

In the above-mentioned embodiment, GaA is used as the semiconductor.
Although an example using s is shown, in principle, other semiconductor materials such as Si, Ge, GaP, AlAs, and GaAs can be used.
P, AlGaAs, SiC, BP, AlN, diamond, etc. are applicable, and in particular, indirect transition type material having a large band gap is suitable. Further, in order to form the semi-insulating region, various intrinsic defects and residual impurities inside the crystal and intentionally added compensation impurities can be used. When forming this semi-insulating region, an undoped crystal containing no dopant is also applicable because it has semi-insulating properties.

As a material of the ohmic bonding electrode 106,
Other than tungsten (W), Al, Au, LaB ₆ or any other material that is commonly known and that forms a Schottky barrier junction with the P-type semiconductor may be used. However, as described above, the smaller the work function of the electrode surface, the higher the electron emission efficiency. Therefore, when the work function of the material is large, the surface of the electrode is thinly coated with a low work function material such as Cs to emit electrons. Efficiency is improved.

(Embodiment 2) FIG. 5 is a sectional view showing a PN junction type semiconductor electron-emitting device which is a second embodiment of the present invention.

The semiconductor electron-emitting device according to the present embodiment has a cylindrical first, substantially central portion on a high-concentration P-type semiconductor substrate 501.
A high-concentration P-type semiconductor region 505 which is a P-type semiconductor region and a P-type semiconductor region 504 which is a fourth P-type semiconductor region supplying carriers to the high-concentration P-type semiconductor region 505 are arranged in contact with each other, Further, the high-concentration P-type semiconductor region 50
5 and the P-type semiconductor region 504, the P-type semiconductor region 503, which is the second P-type semiconductor region, and the low-concentration P-type semiconductor region 502, which is the third P-type semiconductor region, are formed concentrically toward the outside. And a high-concentration N-type semiconductor region 506, which is an N-type semiconductor region forming a PN junction with the high-concentration P-type semiconductor region 505, and a PN junction type element. ..

Further, in the semiconductor electron-emitting device of this embodiment, the ohmic junction electrode 5 for the high-concentration P-type semiconductor substrate 501 for applying a reverse voltage to the PN junction portion.
07, an ohmic contact electrode 509 for the high-concentration N-type semiconductor region 506, and a low work function coating 510 formed on the surface of the high-concentration N-type semiconductor region 506, the reverse voltage from the power supply 511. Is applied.

The ohmic junction electrode 509 has an insulating film 508 formed along the surface edge of the low concentration P-type semiconductor region 502 in order to prevent a short circuit with the low concentration P-type semiconductor region 502. The high concentration N-type semiconductor region 506
Have been touched. In addition, reference numeral 512 in the figure denotes the shape of the depletion layer end in the state where the reverse voltage is applied.
Reference numeral 13 indicates a region where avalanche breakdown occurs by applying the reverse voltage.

An example of a specific manufacturing process of the PN junction type semiconductor electron-emitting device of this embodiment will be described below.

(1) Zn-doped high-concentration P-type semiconductor substrate 501 (GaAs) having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³
A low-concentration P-type GaAs semiconductor layer having a Si concentration of 5 × 10 ¹⁶ cm ⁻³ or less was grown to a thickness of 0.6 μm by the MBE method. This low-concentration P-type GaAs semiconductor layer will later become the low-concentration P-type semiconductor region 502.

(2) In the region corresponding to the P-type semiconductor region 503, the Be concentration is approximately 2 × 10 ¹⁷ cm ⁻³ from the surface of the low-concentration P-type GaAs semiconductor layer to the high-concentration P-type semiconductor substrate 501. 1 by the FIB injection method so that
Be ions accelerated to 60 keV and 40 keV were sequentially implanted. Further, FIB implantation was performed also in regions corresponding to the P-type semiconductor region 504 and the high-concentration P-type semiconductor region 505 so that the Be concentrations were 1 × 10 ¹⁸ cm ⁻³ and 2 × 10 ¹⁸ cm ⁻³ , respectively.

(3) A region corresponding to the high-concentration N-type semiconductor region 506 was ion-implanted so that the Si concentration was about 1 × 10 ¹⁹ cm ⁻³ . If the high-concentration N-type semiconductor region 506 is formed thick, the electrons generated by the avalanche breakdown are scattered and lose energy, which deteriorates the electron emission efficiency. Therefore, it is desirable that the ion implantation is performed at a low acceleration voltage or the surface is etched to form a thickness of 20 nm or less. This high concentration N
By forming the type semiconductor region 506, an electron emitting portion including a PN junction with the high concentration P-type semiconductor region is formed.

(4) On the surface of the low-concentration P-type GaAs semiconductor layer that has been ion-implanted as described above, SiO ₂ is sputtered as a cap material to a thickness of about 0.1 μm.
After the deposition, the injection part was activated by heat treatment at 850 ° C. for 10 seconds.

By the above implantation steps (2) and (3) and one heat treatment step (4), the high-concentration P-type semiconductor region 505 and the P-type semiconductor region 503 which are the first to fourth P-type semiconductor regions are formed. , 504 and lightly doped P-type semiconductor region 502
And the high-concentration N-type semiconductor region 506 which is the N-type semiconductor region can be formed, and the manufacturing process can be simplified as compared with the conventional element having the high-concentration N-type guard ring.

The high-concentration P-type semiconductor region 505, the P-type semiconductor regions 503 and 504, and the low-concentration P-type semiconductor region 502.
And the relationship between the carrier concentrations of the high-concentration N-type semiconductor region 506 and the high-concentration N-type semiconductor region 506 (N-type semiconductor region)> high-concentration P-type semiconductor region 505 (first P-type semiconductor region)> P
Type semiconductor region 504 (fourth P-type semiconductor region)> P-type semiconductor region 503 (second P-type semiconductor region)> low concentration P-type semiconductor region 502 (third P-type semiconductor region).

(5) Next, SiO for heat treatment described above.
After removing the _two films, a SiO ₂ film having a thickness of 0.5 μm is formed as an insulating film 508, and the insulating film 508 is formed in a range corresponding to the high-concentration N-type semiconductor region 506 by a normal photolithography method. An opening was formed to expose the high concentration N-type semiconductor region 506. Then, Au / Cr is used as the ohmic contact electrode 507 for the high-concentration P-type semiconductor substrate 501, and A is used as the ohmic contact electrode 509 for the high-concentration N-type semiconductor region 506 which is an N-type semiconductor.
After vacuum-depositing u / Ge, alloying heat treatment was performed at 350 ° C. for 5 minutes.

(6) Next, the high-concentration N-type semiconductor region 5
Cesium (Cs), which is a low work function material, was vapor-deposited in an ultra-high vacuum in the region where 06 was exposed to form a low work function film 510 by vapor deposition of about a monoatomic layer.

The semiconductor electron-emitting device thus manufactured is placed in a vacuum chamber maintained at about 1 × 10 ^-11 Torr or less, and the ohmic bonding electrode 50 is supplied by the power supply 511.
When a device voltage of 6 V was applied between Nos. 7 and 509, the low work function film 510 on the high concentration P-type semiconductor region 505 was obtained.
An electron emission of about 0.1 μA was observed from the (Cs) surface. As described above, according to this example, it is possible to form a PN junction type semiconductor electron-emitting device having electron emission characteristics equivalent to those of the conventional semiconductor electron-emitting device and having a simple manufacturing process.

Also in the case of the present embodiment, as in the case of the above-mentioned first embodiment, by setting a potential difference between the ohmic junction electrode 509 and another electrode, the flight direction and movement of the electrons are controlled. It is possible to regulate energy.

(Embodiment 3) FIG. 6 is a view showing a Schottky barrier type multi-semiconductor electron-emitting device provided with a plurality of electron-emitting portions, which is a third embodiment of the present invention.
Is a plan view thereof, and (b) is a sectional view taken along line AA ′ of (a).

The multi-semiconductor electron-emitting device of this embodiment is
High-concentration P-type semiconductor region 60 formed on semiconductor substrate 601
Two electron emitting parts 600A, 600B, 600
C and 600D are provided in a matrix.

The electron emitting portions 600A, 600B, 60
Since 0C and 600D have the same configuration, the electron emitting portion 600A will be described as an example.

The electron-emitting portion 600A is disposed in contact with the high-concentration P-type semiconductor region 606A which is the first P-type semiconductor region and the high-concentration P-type semiconductor region 606A, and the high-concentration P-type semiconductor region 606A. Fourth P to supply carriers to
Type semiconductor region 605A which is a type semiconductor region, and the high-concentration P type semiconductor region 606A and P type semiconductor region 60.
A P-type semiconductor region 604A which is a second P-type semiconductor region located around 5A, and a low concentration P-type semiconductor region 603 which is a third P-type semiconductor region located around the P-type semiconductor region 604A. The high-concentration P-type semiconductor region 606A
Schottky electrode 61 forming a Schottky barrier junction with
1A and has the same configuration as that of the first embodiment described above.

Further, the high-concentration P-type semiconductor region 60 for applying a reverse voltage to the Schottky barrier junction.
Ohmic junction electrode 609 and Schottky electrode 6 for 2
Electrode wiring 610A for 11A is provided.
The electrode wiring 610A has the Schottky electrode 611 formed on the insulating film 608 formed on the low-concentration P-type semiconductor region 603 in order to prevent a short circuit with the P-type semiconductor regions.
It is in contact with A.

The ohmic contact electrode 609 has a high concentration of P
It is connected to the high-concentration P-type semiconductor region 602 through the type semiconductor region 607, and in the case of the present embodiment, it is provided at two places as shown in FIG. The ohmic junction electrode 609 is formed by using the four electron emitting portions 600.
It is a common electrode for A, 600B, 600C and 600D.

Further, the Schottky electrode 611A is the Schottky electrode 611B, 611C, 611D (611C, 61) of the other electron emitting portions 600B, 600C, 600D.
1D may be connected in common with (not shown), but in that case,
Since the ohmic junction electrode 609 is common, the four electron emitting portions 600A, 600B, 600C, and 600D simultaneously control the electron emitting operation.
On the other hand, each of the electron emitting portions 600A, 600B, 600C, 6
00D Schottky electrodes 611A, 611B, 611
When C and 611D are independent, each electron emission unit 600
It is possible to control each of A, 600B, 600C, and 600D.

Further, the element surface on which the four electron-emitting portions 600A, 600B, 600C and 600D having the above-mentioned structure are formed is provided on the insulating film 608.
A portion other than the ohmic contact electrode 609 is covered with a gate 613 made of a metal film through a support 612 made of an insulating material. In the gate 613, openings 614A, 614B, and 614B, 614B, and 614B are provided at positions corresponding to above the electron emission portions 600A, 600B, 600C, 600D, respectively.
614C and 614D are formed, and each electron emission portion 6 is formed.
Electrons emitted from 00A, 600B, 600C and 600D are emitted from the openings 614A, 614B, 614C and 614D.
It will jump out through.

An example of a specific manufacturing process of the multi-semiconductor electron-emitting device of this embodiment will be described below.

(1) An undoped semi-insulating semiconductor substrate 601 (Ga) with an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less
A reverse pattern was formed on As) by a normal photolithography method, and then a normal ion implantation was performed so that the Be concentration became 3 × 10 ¹⁸ cm ⁻³ .

Then, by heat treatment at 850 ° C. for 10 seconds, a stripe-shaped high concentration P-type semiconductor region 602 long in the X direction was formed.

(2) Be concentration of 5 × 10 by MBE method
GaAs as a low concentration P-type semiconductor region 603 of ¹⁵ cm ^-3
Was grown to a thickness of 0.6 μm.

(3) P-type semiconductor regions 604A and 604
B, 604C, so that Be concentration and 2 × 10 ¹⁷ cm ^-3 in a region corresponding to 604D, also, P-type semiconductor regions 605A, 605B, 605C, 3 × the Be concentration in a region corresponding to 605D such that the 10 ¹⁸ cm ^-3, further high-concentration P-type semiconductor regions 606A, 606B, 606
In the region corresponding to C and 606D, the Be concentration is 2 × 10 ^18.
Be ^-3 by FIB injection method so that it becomes cm ^-3.
Ions were implanted. In addition, the high concentration P-type semiconductor region 607
Be ions were implanted into the region corresponding to 1 by the FIB implantation method so that the Be concentration was 3 × 10 ¹⁸ cm ⁻³ .

The MBE growth step and the FIB injection step in (1) to (3) above were carried out without being exposed to the atmosphere because the respective devices were connected by a vacuum tunnel.

(4) Further, by heat treatment at 850 ° C. for 10 seconds, P-type semiconductor regions 604A, 604B, 604.
C, 604D, 605A, 605B, 605C, 605
D and high-concentration P-type semiconductor regions 606A, 606B, 606
C, 606D, 607 were activated.

(5) On the low-concentration P-type semiconductor region 603 which has been ion-implanted as described above, as the insulating film 608, SiO ₂ having a thickness of 0.
After depositing 2 μm, in order to form the Schottky barrier junction, each opening is formed by a normal photolithography etching method to form the high concentration P-type semiconductor region 607 and P
Type semiconductor regions 604A, 604B, 604C, 604D
And high-concentration P-type semiconductor regions 606A, 606B, 60
6C and 606D were exposed. Au / Cr is vacuum-deposited on the high-concentration P-type semiconductor region 607 at 350 ° C.
The ohmic bonding electrode 609 was formed by heat treatment for 5 minutes.

(6) Aluminum (Al) is used as the electrode wiring 610, and the high-concentration P-type semiconductor regions 606A and 606 are used.
Tungsten (W) as a material for forming a Schottky barrier junction with respect to 06B, 606C, and 606D is evaporated by electron beam evaporation to a thickness of 0.5 μm and 8 nm, respectively, and the electrode wiring 6 is formed by a normal photolithographic etching method.
10A, 610B, 610C, 610D and Schottky electrodes 611A, 611B, 611C, 611D were formed.

(7) As the support 612 and the gate 613 made of an insulating material, SiO ₂ and tungsten (W) are sequentially deposited by a vacuum vapor deposition method, and openings 614A and 614 are formed by a normal photolithographic etching method.
B, 614C and 614D were formed.

Through the above steps (1) to (7), a multi-semiconductor electron-emitting device having four electron-emitting portions 600A, 600B, 600C and 600D is completed.

Similarly, 20 electron-emitting portions are provided in the X direction,
To prepare a multi-semiconductor electron-emitting devices arranged in ten matrix in the Y direction, the degree of vacuum is established in about 1 × 10 ^{over 7} Torr in the vacuum chamber, the reverse voltage to all the electron-emitting portion 7
When V was applied, a total electron emission of about 20 nA was confirmed. It was also confirmed that by applying a reverse voltage only between the arbitrary ohmic junction electrode 609 and the arbitrary electrode wiring 610, only the element at the intersection emits electrons. As described above, according to this embodiment, it is possible to form an electron-emitting device which has the same electron-emitting characteristics as those of the conventional multi-semiconductor electron-emitting device and which is easy to manufacture.

[0071]

Since the present invention is constructed as described above, it has the following effects.

(1) By forming a low-concentration second P-type semiconductor region and a further low-concentration third P-type semiconductor region outside the first P-type semiconductor region having a high carrier concentration,
The depletion layer can be shaped so that the electric field is most likely to be concentrated in the first P-type semiconductor region. As a result, avalanche breakdown occurs efficiently only in the first P-type semiconductor region, so that the guard ring structure and its ohmic contact electrode provided in the above-described conventional technique are unnecessary, and the avalanche breakdown electrode is not necessary. The manufacturing process is simplified.

(2) The carrier concentration of the fourth P-type semiconductor region for supplying carriers to the first P-type semiconductor region is set to the second carrier concentration around the first P-type semiconductor region.
By increasing the carrier concentration in the P-type semiconductor region, the series resistance value of the device is lowered, so that a semiconductor electron-emitting device having a high operating speed can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor electron-emitting device of the present invention.

FIG. 2 is a diagram showing an example of an energy band of a semiconductor electron-emitting device having a Schottky barrier junction.

FIG. 3 is a diagram showing an example of current-voltage characteristics of the semiconductor electron-emitting device of the present invention.

FIG. 4 is a diagram showing another example of current-voltage characteristics of the semiconductor electron-emitting device of the present invention.

FIG. 5 is a sectional view showing a second embodiment of the semiconductor electron-emitting device of the present invention.

FIG. 6 is a sectional view showing a third embodiment of the semiconductor electron-emitting device of the present invention.

[Explanation of symbols]

101, 501 High-concentration P-type semiconductor substrate 102, 502, 603 Low-concentration P-type semiconductor region 103, 104, 503, 504, 604, 605
P-type semiconductor region 105, 505, 602, 606, 607 High concentration P
Type semiconductor region 106, 507, 509, 609 ohmic junction electrode 107, 508, 608 insulating film 108, 611 Schottky electrode 109, 610 electrode wiring 110, 511 power supply 111, 512 depletion layer 112, 513 avalanche region 506 high concentration N type Semiconductor region 510 Low work function film 600 Electron emission part 601 Semiconductor substrate 612 Support 613 Gate 614 Opening

Claims (40)

[Claims] 1. A semiconductor electron-emitting device which has an electron-emitting portion formed of a Schottky barrier junction of a metal material or a metal compound material and a semiconductor and emits electrons from a solid surface, wherein the electron-emitting portion has the Schottky barrier junction. And a second P-type semiconductor region located around the first P-type semiconductor region, and a second P-type semiconductor region that forms avalanche breakdown. A third P-type semiconductor region located around the periphery of the first P-type semiconductor region, and a fourth P-type semiconductor region supplying carriers to the first P-type semiconductor region, and the first to fourth P-type semiconductor regions. Of the carrier concentration of (first P-type semiconductor region)> (fourth P-type semiconductor region)
> (Second P-type semiconductor region)> (Third P-type semiconductor region) 2. The semiconductor electron-emitting device according to claim 1, wherein the electron-emitting portion has a structure in which the first P-type semiconductor region and the fourth P-type semiconductor region are in contact with each other. 3. The semiconductor electron-emitting device according to claim 1, wherein an electrode for defining a flight direction of electrons emitted from the electron-emitting portion is provided in the vicinity of the solid surface. 4. The semiconductor electron-emitting device according to claim 1, wherein an electrode for defining kinetic energy of electrons emitted from the electron-emitting portion is provided near the surface of the solid. 5. A material having a work function different from that of the metal material or the metal compound material is deposited on the surface of the metal material or the metal compound material forming the Schottky barrier junction of the electron emitting portion. The semiconductor electron-emitting device according to 1, 2, 3 or 4. 6. The semiconductor electron emitting device according to claim 1, wherein the electron emitting portion is formed on a semiconductor substrate. 7. The semiconductor electron emitting device according to claim 1, wherein a plurality of electron emitting portions are provided on the same substrate. 8. The semiconductor electron-emitting device according to claim 7, wherein the substrate is a semiconductor substrate. 9. The semiconductor electron-emitting device according to claim 7, wherein the plurality of electron-emitting portions are electrically independent of each other and can emit electrons individually. 10. The first to fourth P-type semiconductor regions of the electron-emitting portion are formed by an ion implantation method, which is one of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth aspects. The semiconductor electron-emitting device described. 11. A semiconductor electron-emitting device that has an electron-emitting portion formed of a Schottky barrier junction of a metal material or a metal compound material and a semiconductor and emits electrons from a solid surface, wherein the electron-emitting portion has the Schottky barrier junction. And a second P-type semiconductor region located around the first P-type semiconductor region, and a second P-type semiconductor region that forms avalanche breakdown. And a fourth P-type semiconductor region for supplying carriers to the first P-type semiconductor region, the first to fourth P-type semiconductor regions being provided around the first P-type semiconductor region. The magnitude relation of the carrier concentration in the semiconductor region is (the fourth P-type semiconductor region) ≧ (the first P-type semiconductor region)
> (Second P-type semiconductor region)> (Third P-type semiconductor region) 12. The semiconductor electron-emitting device according to claim 11, wherein the electron-emitting portion has a structure in which the first P-type semiconductor region and the fourth P-type semiconductor region are in contact with each other. 13. The semiconductor electron-emitting device according to claim 11, wherein an electrode for defining a flight direction of electrons emitted from the electron-emitting portion is provided near the device surface. 14. The semiconductor electron-emitting device according to claim 11, wherein an electrode for defining kinetic energy of electrons emitted from the electron-emitting portion is provided near the device surface. 15. A material having a work function different from that of the metal material or the metal compound material is deposited on the surface of the metal material or the metal compound material forming the Schottky barrier junction of the electron emitting portion. 11, 12, 1
The semiconductor electron-emitting device according to 3 or 14. 16. The semiconductor electron emitting device according to claim 11, 12, 13, 14 or 15, wherein the electron emitting portion is formed on a semiconductor substrate. 17. A plurality of electron emission parts are provided on the same substrate, 11, 12, 1 and 1.
The semiconductor electron-emitting device according to 3, 14, or 15. 18. The semiconductor electron-emitting device according to claim 17, wherein the substrate is a semiconductor substrate. 19. The semiconductor electron-emitting device according to claim 17, wherein the plurality of electron-emitting portions are electrically independent of each other and can emit electrons individually. 20. The first to fourth P-type semiconductor regions of the electron emitting portion are formed by an ion implantation method.
A semiconductor electron-emitting device according to item 7, 18 or 19. 21. A semiconductor electron-emitting device which has an electron-emitting portion composed of a PN junction of an N-type semiconductor and a P-type semiconductor and emits electrons from a solid surface, wherein the electron-emitting portion is located on the solid surface. An N-type semiconductor region and a first P-type semiconductor region that forms a PN junction with the N-type semiconductor region to cause avalanche breakdown, and further includes a second P-type semiconductor region located around the first P-type semiconductor region. P-type semiconductor region, a third P-type semiconductor region located around the second P-type semiconductor region, and a fourth P-type semiconductor for supplying carriers to the first P-type semiconductor region. The first to fourth P-type semiconductor regions and the N-type semiconductor region have a carrier concentration relationship of (N-type semiconductor region)> (first P-type semiconductor region)> (fourth region). P-type semiconductor region)> (second P-type semiconductor Area)>
(Third P-type semiconductor region). 22. The semiconductor electron-emitting device according to claim 21, wherein the electron-emitting portion has a structure in which the first P-type semiconductor region and the fourth P-type semiconductor region are in contact with each other. 23. The semiconductor electron-emitting device according to claim 21, wherein an electrode for defining a flight direction of electrons emitted from the electron-emitting portion is provided near a solid surface. 24. The semiconductor electron-emitting device according to claim 21, 22 or 23, wherein an electrode for defining kinetic energy of electrons emitted from the electron-emitting portion is provided in the vicinity of the solid surface. 25. The semiconductor electron-emitting device according to claim 21, 22, 23 or 24, wherein materials having different work functions are deposited on the surface of the N-type semiconductor region of the electron-emitting portion. 26. The semiconductor electron-emitting device according to claim 21, 22, 23, 24 or 25, wherein the electron-emitting portion is formed on a semiconductor substrate. 27. A plurality of electron-emitting portions are provided on the same substrate, 21, 22, 22.
The semiconductor electron-emitting device according to 3, 24 or 25. 28. The semiconductor electron-emitting device according to claim 27, wherein the substrate is a semiconductor substrate. 29. The semiconductor electron-emitting device according to claim 27 or 28, wherein the plurality of electron-emitting portions are electrically independent of each other and can emit electrons individually. 30. The first to fourth P-type semiconductor regions and N-type semiconductor regions are formed by an ion implantation method, 21, 22, 23, 24, 25 and 2.
The semiconductor electron-emitting device according to 6, 27, 28 or 29. 31. A semiconductor electron-emitting device which has an electron-emitting portion composed of a PN junction of an N-type semiconductor and a P-type semiconductor and emits electrons from a solid surface, wherein the electron-emitting portion is located on the solid surface. And an N-type semiconductor region forming the PN junction, and the N-type semiconductor region and P
A first P-type semiconductor region that forms an N-junction to cause avalanche breakdown, and further includes a second P-type semiconductor region located around the first P-type semiconductor region and the second P-type semiconductor region. A third P-type semiconductor region located around the P-type semiconductor region, and a fourth P-type semiconductor region for supplying carriers to the first P-type semiconductor region. The relationship between the carrier concentrations of the P-type semiconductor region and the N-type semiconductor region is (N-type semiconductor region)> (fourth P-type semiconductor region) ≧ (first P-type semiconductor region)> (second P-type semiconductor region) Type semiconductor region)>
(Third P-type semiconductor region). 32. The semiconductor electron-emitting device according to claim 31, wherein the electron-emitting portion has a structure in which the first P-type semiconductor region and the fourth P-type semiconductor region are in contact with each other. 33. The semiconductor electron-emitting device according to claim 31, wherein an electrode for defining a flight direction of electrons emitted from the electron-emitting portion is provided near the surface of the solid. 34. The semiconductor electron-emitting device according to claim 31, 32 or 33, wherein an electrode for defining kinetic energy of electrons emitted from the electron-emitting portion is provided near the surface of the solid. 35. The semiconductor electron-emitting device according to claim 31, 32, 33 or 34, wherein materials having different work functions are deposited on the surface of the N-type semiconductor region of the electron-emitting portion. 36. The semiconductor electron emitting device according to claim 31, 32, 33, 34 or 35, wherein the electron emitting portion is formed on a semiconductor substrate. 37. The semiconductor electron-emitting device according to claim 31, 32, 33, 34, 35 or 36, wherein a plurality of electron-emitting portions are provided. 38. The semiconductor electron-emitting device according to claim 37, wherein the substrate is a semiconductor substrate. 39. The semiconductor electron-emitting device according to claim 37 or 38, wherein the plurality of electron-emitting portions are electrically independent of each other and can emit electrons individually. 40. The first to fourth P-type semiconductor regions and the N-type semiconductor regions are formed by an ion implantation method, 31, 32, 33, 34, 35 and 3.
The semiconductor electron-emitting device according to 6, 37, 38 or 39.