JPH0574776A - Mounting structure of semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To simplify the mounting structure of the semiconductor chip,
A mounting structure that can reduce manufacturing and assembling steps, improve yield, and reduce production cost, has high reliability, and is downsized. [Structure] An upper surface 1A of a semiconductor (Si) chip 1 and a coating 3 made of silicon oxide (or silicon nitride) containing the same element (Si) as the chip 1 are formed on a lower surface 1B and a side surface 1C of the chip. In addition, an insertion hole 3a is provided at a predetermined position of the covering portion 3A formed on the side of the chip upper surface 1A so as to correspond to the electrode 11 of the semiconductor chip, and the solder bump 2 is mounted in the insertion hole 3a and the semiconductor device 10
The extraction electrode of is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly to a technology that is particularly effective when applied to a semiconductor mounting technology, for example, a technology useful when applied to a wireless bonding mounting technology.

[0002]

2. Description of the Related Art Conventionally, various techniques for mounting a semiconductor chip have been proposed (for example, latest illustrated semiconductor guide, Seibundo Shinkosha, June 12, 1984, page 93). In particular, when mounting an LSI in which a large voltage is applied to heat a semiconductor chip to a high temperature in order to increase the processing speed,
A mounting structure by a wireless bonding method as shown in FIG. 8 is generally used. Specifically, in the mounting structure described above, the package body 80 is formed of, for example, ceramic, and the wiring structure is formed therein with tungsten, a polycide thin film, copper, or the like. The pads 72, 72 ... Of the semiconductor chip 71 are connected to the solder bumps 7.
3, 73 ..., The electrode 8 of the wiring structure of the package 80
, Which are once connected to the solder bumps 8 via the internal wiring structure of the package 80 and the electrodes 82, 82.
, 83 ... are drawn out of the package.
The wiring structure thus drawn out is the semiconductor device 70.
The electrode 91 on the side of the wiring board 90 on which the is mounted is contacted and heated to be welded (FIG. 8).

[0003]

However, in the above mounting structure, as described above, it is necessary to form the wiring structure for connecting the semiconductor chip and the wiring board in the package on which the semiconductor chip is mounted. The structure is complicated, moreover, the number of manufacturing and assembling steps is increased, resulting in a decrease in yield and an increase in cost.

Further, the above-mentioned conventional mounting structure has a package 8
Although 0 is usually formed of ceramic, since the ceramic package and the semiconductor chip 70 have different coefficients of thermal expansion, the semiconductor chip is heated when the operation of the LSI is turned on / off, so that the joint between the chip 70 and the package 80 is heated. Thermal distortion occurs in the (solder bumps 73, 73 ... Portions), and fatigue fracture occurs in this portion. Such fatigue fracture of the joint in the mounting structure reduces the reliability of the semiconductor device as a whole.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device mounting structure having a simple structure, high reliability, and miniaturization. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the mounting structure according to claim 1 of the present application, the upper surface of the semiconductor chip in which the activation region is formed, and the lower surface and the side surface of the chip include the package coating portion made of the compound containing the same element as the semiconductor chip. An insertion hole is formed at a predetermined position of the covering portion formed and formed on the upper surface of the chip so as to correspond to the electrode of the semiconductor chip, and a solder bump is attached to the insertion hole to form an extraction electrode. In the mounting structure according to claim 2, a package cover made of a compound containing the same element as that of the semiconductor chip is formed on the upper surface of the semiconductor chip in which the activation region is formed and the side surface of the chip, and the lower surface thereof. A thin metal plate is formed on the upper surface of the chip, and an insertion hole is provided at a predetermined position of the covering portion formed on the upper surface of the chip so as to correspond to the electrode of the semiconductor chip, and a solder bump is attached to the insertion hole to form an extraction electrode. ing. Further, in the mounting structure according to claim 3, the upper surface of the semiconductor chip on which the activation region is formed, and the lower surface and the side surface of the chip are formed with a plastic covering portion, and the plastic covering is formed on the upper surface of the chip. An insertion hole is provided at a predetermined position of the portion corresponding to the electrode of the semiconductor chip, and a solder bump is attached to the insertion hole to form a lead electrode.

[0007]

According to the above-mentioned means of claim 1, it is possible to form a coating portion of the same material as the chip (Si) (for example, SiO2) on the upper surface, the lower surface and the side surface of the semiconductor chip.
It can be packaged, and the wiring structure from the semiconductor chip to the external wiring substrate can be extremely simply configured by inserting solder bumps into the insertion holes provided in the covering portion. Further, according to the means of claim 2, the same material (for example, silicon) as the chip is used for the upper surface and the side surface of the semiconductor chip.
It is possible to form a package by simply forming the covering part of the above and further forming a metal thin plate on the lower surface of the chip, and the wiring structure is very simple like the above-mentioned means, and moreover, the heat radiation fin is bonded to the metal thin plate. Only by itself, it is possible to obtain a structure that reduces excellent thermal resistance. According to the third aspect of the present invention, an extremely simple and inexpensive package structure can be obtained by applying plastic to the entire surface of the semiconductor chip, providing through holes for the electrodes therein, and inserting solder bumps into the through holes. Be done.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of a semiconductor device to which the present invention is applied will be described below with reference to FIGS. FIG. 1 is a vertical cross-sectional view of a semiconductor device 10 in which the mounting structure of the present invention is used, and FIG. 2 is an enlarged view of a main part showing a bump structure formed in the semiconductor device 10. 1 and 2
Shows the semiconductor device 10 mounted upside down on a wiring board (printed circuit board) 90.

As shown in FIG. 1, the mounting structure of this embodiment is
The solder bumps 2, 2 ... Connected to the electrodes 11, 11 ... Of the silicon (Si) chip 1 and the covering portion 3. Of these, the covering portion 3 is the upper surface 1 of the Si chip 1.
A, the lower surface 1B and the side surface 1C are entirely covered, and are formed of a silicon compound (for example, SiO2) having a thickness of about 500 μm and excellent in water resistance.

A semiconductor device 10 having the above-mentioned mounting structure.
Is the upper surface of the Si chip 1, that is, the activation region (not shown)
A bump structure (FIG. 2) is formed on the chip surface 1A (lower surface in the figure) side on which is formed. Solder bump 2
Is inserted into a window portion 3a formed in the covering portion 3A of the upper surface 1A of the Si chip 1, and the lower end portion of the metal thin film (Pb -S
n) connected via 12. Here, the Si chip 1 and the covering portion 3 are both formed to have a thickness of about 500 μm so that the mechanical strength of the semiconductor device 10 is maintained. The thickness of the metal thin film 1b is about 2 to 3 μm.

The semiconductor device 10 thus formed is
The solder bumps 2 are aligned so that they correspond to the electrode pads 91, 91 ... On the side of the wiring board 90 on which the semiconductor device 10 is mounted. Then, in this state, the semiconductor device 10 and the wiring substrate 9 are passed through a heat treatment furnace.
Bonding with 0 is performed. As described above, in the mounting structure of the present embodiment, since the semiconductor chip 1 is directly formed with the silicon oxide as the covering portion, the package can be downsized without the need for a plastic mold for the package, which has been required before. In addition, it has excellent airtightness, water resistance, and pressure resistance. Such a mounting structure is effective for a high-density mounting structure. Moreover, since the structure is simple, the number of manufacturing steps is small, and the production cost is significantly reduced.

By the way, as described above, the coating portion 3 is made of a silicon compound (SiO2) because the material is substantially equal to the thermal expansion coefficient of Si, and therefore the Si chip 1 is subjected to high-speed operation processing of the LSI. This is because the possibility that thermal strain will occur between the main body of the Si chip 1 and the covering portion 3 that covers the Si chip 1 even when the material expands due to heat generation is significantly lower than when other materials are used. Therefore, heating of the Si chip 1 does not cause cutting stress due to thermal strain in the wiring structure between the chip 1 and the covering portion 3 and further the solder bumps 2, and a mounting structure excellent in heat resistance is achieved. It When the semiconductor device 10 is mounted on the highly flexible plastic wiring substrate 90, a chip and a ceramic package are provided between the electrodes of the semiconductor device 10 and the wiring substrate 90 in the conventional mounting structure. There is no thermal strain that would otherwise occur.

FIG. 3 is an explanatory view showing an example of a method of forming the covering portion 3 on the Si chip 1. In forming the covering portion 3, the Si chip 1 after dicing is performed,
1 ... is placed on a pedestal portion (pedestal seal), and isotropic CVD SiO2 is deposited. In this case, first, the coating portion 3 having a predetermined width (thickness of about 500 μm) is formed on the entire surface (in the illustrated example, the upper surface 1A and the side surface 1C) other than the joint surface with the pedestal seal. Then, after that, the semiconductor device 10 is once removed from the pedestal seal and cut into individual pieces, and then the upper surface 1
The semiconductor device 10 is again placed on the pedestal part with A facing down, and CVD is performed on this. By such an operation, the covering portion 3 made of SiO2 is formed on the entire surface of the Si chip 1.

In order to insert the solder ball 2 into the covering portion 3A (lower side in FIG. 1) on the upper surface side (the surface 1A side of the Si chip) of the semiconductor device 10 among the covering portions 3 thus formed. Window portion 3a is provided by, for example, dry etching using a mask pattern. The mask pattern used to form the window 3a is created corresponding to the arrangement pattern of the electrodes 11 formed on the Si chip surface 1A.

(Second Embodiment) FIG. 4 shows that the upper surface 21A and the side surface 21C of the Si chip 21 are covered with a coating portion 23 made of the same material (SiO2) as in the first embodiment, and the other surface (lower surface 21B). FIG. 8 is a cross-sectional view showing a mounting structure of a second embodiment in which (1) is covered with a thin metal plate (Au) 24. Note that FIG. 4 shows a state in which the semiconductor device 20 is mounted on the wiring board 90 with the top and the bottom reversed.

In this mounting structure, the lower surface 21 of the Si chip is used.
The metal thin plate 24 formed on B has a film thickness of about 5 μm,
The lower surface 21B is made airtight to achieve a water resistant structure. As described above, the reason why sufficient water resistance can be achieved at about 5 μm is that the lower surface 21B of the Si chip 21 is flat,
This is because high adhesion with the thin metal plate 24 can be obtained.
In addition, a metal thin plate (Au) 2 is formed on the lower surface 21B of the Si chip 21.
Vapor deposition sputtering or the like is used for forming 4. Regarding the pressure resistance, the upper surface 2 of the Si chip
Increase the thickness of the coating 23A formed on 1A (500μ
m)). If the withstand voltage is to be further improved, the thickness of the Si chip 31 itself may be made thicker than the normal thickness (about 500 μm) as in the semiconductor device 30 shown in FIG. 5 (for example, about 1000 μm). ).

Further, the above-mentioned thin metal plate 24 is grounded,
Alternatively, by applying a bias voltage, the semiconductor chip 21 can be easily grounded or a bias voltage can be applied.

FIG. 6 shows a thin metal film 4 forming a coating on the lower surface 41B of the semiconductor device having the structure shown in the second embodiment.
4 (upper side in the figure) radiating fin (metal (Al) fin)
It shows a modified example of the semiconductor device to which 45 is adhered. The semiconductor device 40 of this modification has a lower surface (a surface opposite to the surface on which the activation region is formed) 41B of the Si chip 41B.
Since a metal thin plate (Au) 44 having a high heat conductivity is connected to the lower side surface of the covering portion, by directly soldering the heat radiation fins 45 to the metal plate 44, the structure is simple and the heat resistance is high. It is possible to obtain a semiconductor device cooling structure with reduced cooling efficiency and high cooling efficiency. Further, such a structure has a smaller number of parts and a smaller manufacturing process than the conventional structure, and the production cost is significantly reduced.

(Third Embodiment) FIG. 7 is a sectional view showing the mounting structure of the third embodiment in which the upper surface 51A, the lower surface 51B and the side surface 51C of the Si chip 51 are covered with a plastic covering portion 53 ( FIG. 7 shows a state in which the semiconductor device 50 is mounted upside down on the wiring board 90). In forming such a mounting structure, a plastic solvent is applied to the entire surface of the diced Si chip 51, and thereafter, the contact holes 55, 55 ... Are etched at positions corresponding to the electrodes 54 of the Si chip 51. Open and open the solder bumps 52, 52 ... Since the semiconductor chip mounting structure is achieved by such an extremely simple process of coating plastic on the entire surface of the Si chip 51, the production cost is reduced, and the yield is improved due to the simplification of the manufacturing process and the phenomenon of the number of parts. ..

Incidentally, in this way, the covering portion 5 is made of plastic.
In the case of forming No. 3, since the plastic easily expands and contracts in response to the heat change, the chip and the ceramic in the conventional mounting structure are provided between the semiconductor chip and the plastic covering portion 53 even when the temperature cycle occurs. The thermal strain that occurs between the package and the package does not occur.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in forming the covering portion, not only the silicon oxide film but also other silicon compounds such as Si3N4 may be used. In addition, the thin metal plate that adheres to the lower surface of the Si chip is
Not limited to the gold (Au) thin plate, a thin plate of other metal may be formed.

[0022]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. In other words, with a simple mounting structure,
It is possible to eliminate the fatigue fracture of the joint portion of the wiring structure due to the thermal strain generated due to the temperature cycle, and to achieve a highly reliable mounting structure with reduced thermal resistance. Also,
Since the mounting structure of the present invention has a small number of parts, the failure rate is also reduced.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a semiconductor device 10 showing a mounting structure of a first embodiment in which a top surface, a bottom surface and a side surface of a semiconductor chip are covered with a covering portion made of silicon oxide.

FIG. 2 is an enlarged sectional view of an essential part showing a bump structure formed in a semiconductor device 10.

FIG. 3 is a cross-sectional view showing a method of forming a covering portion 3.

FIG. 4 is a vertical cross-sectional view of a semiconductor device 20 showing a mounting structure of a second embodiment in which the upper and side surfaces of a semiconductor chip are covered with silicon oxide and the lower surface is covered with a thin metal plate.

FIG. 5 is a vertical cross-sectional view of a semiconductor device 30 showing a modified example in which the semiconductor chip itself is thicker than a normal thickness to further improve pressure resistance.

FIG. 6 is a vertical cross-sectional view of a semiconductor device 40 showing a modified example in which a radiation fin is bonded to a thin metal plate formed on the lower surface of a semiconductor chip.

FIG. 7 is a vertical cross-sectional view of a semiconductor device 50 showing a mounting structure according to a third embodiment in which the upper surface, lower surface and side surfaces of a semiconductor chip are covered with plastic.

FIG. 8 is a longitudinal sectional view of a semiconductor device 80 showing a conventional semiconductor chip mounting structure using a ceramic package.

[Explanation of symbols]

 1, 21, 51 Semiconductor chip (Si chip) 1A, 21A, 51A Semiconductor chip upper surface 1B, 21B, 51B Semiconductor chip lower surface 1C, 21C, 51C Semiconductor chip side surface 2, 22, 52 Solder bump 3, 23, 53 Cover portion 3a Insertion Hole 10, 20, 50 Semiconductor device 11 Chip electrode 24 Metal thin plate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 23/29 23/31 8617-4M H01L 23/30 Z (72) Inventor Koji Fukumoto Kodaira, Tokyo 5-20-1 Jitsumizu Honcho, Ichi, Japan, within Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor Masayasu Oizumi 5-20-1, Kamimizuhoncho, Kodaira, Tokyo Metropolitan Government I Engineering Co., Ltd. (72) Inventor Norikatsu Asari 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor, Hiroshi Ichikawa Kodaira, Tokyo 5-20-1 Joumizu-honcho, Ichi, Hitate Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor chip on which an activation region is formed, and a package cover made of a compound containing the same element as that of the semiconductor chip is formed on the lower surface and side surfaces of the semiconductor chip and on the upper surface of the chip. A mounting structure of a semiconductor device, wherein an insertion hole is provided at a predetermined position of the covered portion corresponding to an electrode of a semiconductor chip, and a solder bump is attached to the insertion hole to form a lead electrode. 2. A package cover made of a compound containing the same element as that of the semiconductor chip is formed on the upper surface of the semiconductor chip on which the activation region is formed and the side surface of the chip,
A thin metal plate is formed on the lower surface of the chip, and an insertion hole corresponding to the electrode of the semiconductor chip is provided at a predetermined position of the covering portion formed on the upper surface of the chip, and a solder bump is attached to the insertion hole to form the extraction electrode. A mounting structure of a semiconductor device, which is formed. 3. A semiconductor chip having an upper surface of the semiconductor chip on which an activation region is formed and a lower surface and a side surface of the chip, and a semiconductor chip formed at a predetermined position of the plastic cover formed on the upper surface of the chip. An insertion hole is provided corresponding to the electrode, and a lead-out electrode is formed by mounting a solder bump on the insertion hole.