JPH0574792A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the operating speed of a vertical bipolar transistor mounted in a semiconductor integrated circuit device and prevent malfunction. In a semiconductor integrated circuit device having a vertical bipolar transistor, a peak value of impurity concentration is set on a protruding island region 7A formed on the main surface of a semiconductor substrate on the upper surface side of the protruding island region 7A. And a protruding island region 7 on the main surface of the semiconductor substrate.
Under A, a base region in which a peak value of the impurity concentration is set is provided in the junction with the emitter region (7) or in the vicinity of the junction in each of the regions outside the periphery of the protruding island region 7A. In this bipolar transistor, the emitter extraction electrode 8 is connected to the emitter region (7) on the upper surface of the protruding island region 7A, and the bipolar transistor is formed in a region outside the periphery of the protruding island region 7A. The base lead electrode 12 is connected to the base region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a vertical structure bipolar transistor.

[0002]

2. Description of the Related Art A general high-speed and high-performance bipolar transistor mounted on a semiconductor integrated circuit device has a so-called vertical structure. This vertical-type bipolar transistor has a semiconductor substrate formed by growing an n-type epitaxial layer on a main surface of a p-type semiconductor substrate made of, for example, single crystal silicon, in a direction perpendicular to the main surface. Each of the emitter region, the base region, and the collector region is sequentially arranged and configured. This vertical structure bipolar transistor is provided in an active region of a semiconductor substrate in a semiconductor integrated circuit device, and the active region is electrically isolated from other surrounding active regions by an element isolation region.

In the vertical bipolar transistor, for example, the emitter region is composed of an n-type semiconductor region having a high impurity concentration, the base region is composed of a p-type semiconductor region, and the collector region is connected to the base region. The n-type epitaxial layer having a low impurity concentration is provided and the buried n-type semiconductor region having a high impurity concentration is provided below the n-type epitaxial layer. In this type of vertical structure bipolar transistor, the emitter region and the base region are formed with shallow junction depths (depths in the depth direction from the surface of the semiconductor substrate) for the purpose of shallowing. There is.

The emitter region is formed, for example, after the base region is formed. The emitter region is a base region formed on the main surface of the semiconductor substrate with n-type impurities introduced from the emitter extraction electrode (polycrystalline silicon film) formed on the main surface of the semiconductor substrate to the emitter extraction electrode. Spread on the main surface
It is formed shallowly by (solid phase diffusion). This emitter region is connected to the emitter extraction electrode from the surface side of the semiconductor substrate. In the base region, a p-type impurity introduced from a base extraction electrode (polycrystalline silicon film) formed on the main surface of the semiconductor substrate into the base extraction electrode is diffused or p-type impurities are introduced into the main surface of the semiconductor substrate. Is formed on the main surface of the semiconductor substrate by ion implantation. In this base region, a peak value of the impurity concentration, that is, a region having a high impurity concentration is formed on the surface side of the semiconductor substrate due to shallowing, so that the impurity concentration is higher than that of the direct or intrinsic base region (substantially operating region). It is connected to the base lead-out electrode from the front surface side of the semiconductor substrate via the graft base region formed with a high impurity concentration.

In the vertical bipolar transistor having such a structure, the emitter region and the base region are formed with shallow junction depths, respectively, and the emitter-base and base-base junctions are formed.
The respective junction areas between the collectors are reduced to reduce the junction capacitances between the emitter-base and the base-collector.

[0006]

However, as a result of examining the above-mentioned semiconductor integrated circuit device, the present inventor has found the following problems.

In the vertical bipolar transistor mounted on the semiconductor integrated circuit device, the junction depth of each of the emitter region and the base region becomes shallower as the shallower junction is formed, and the junction depth of each of the emitter region and the base region is reduced. A region having a high impurity concentration is formed on the front surface side (the front surface side of the semiconductor substrate). Therefore, each of the emitter region and the base region forms a pn junction with a high impurity concentration in the side wall portion around the emitter region, and the junction capacitance (Cte) between the emitter and the base increases at this junction. , The emitter-base junction breakdown voltage at this junction is lowered. This phenomenon lowers the operating speed of the vertical bipolar transistor and causes a malfunction.

An object of the present invention is to provide a technique capable of increasing the operating speed and preventing malfunctions in a semiconductor integrated circuit device having a vertical bipolar transistor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) An emitter region and a base region are arranged on a main surface of a semiconductor substrate in a direction perpendicular to the main surface. An emitter electrode is provided in the emitter region and a base electrode is provided in the base region. In a semiconductor integrated circuit device having connected vertical bipolar transistors, a peak value of the impurity concentration is set in the protruding island region formed on the main surface of the semiconductor substrate on the upper surface side of the protruding island region. An emitter region is provided, and impurities are formed in the junction with the emitter region or in the vicinity of the junction, below the projecting island region on the main surface of the semiconductor substrate and in each region outside the periphery of the projecting island region. A bipolar transistor having a base region in which a peak concentration value is set is formed, and the bipolar transistor is formed on the upper surface of the protruding island region in the emitter region. Connect the emitter electrode, for connecting the base electrode to the base region in a region outside the periphery of the protruded island region.

(2) An emitter region and a base region are arranged on the main surface of the semiconductor substrate in a direction perpendicular to the main surface, and an emitter electrode is provided in the emitter region and a base electrode is provided in the base region. In a method for manufacturing a semiconductor integrated circuit device having a connected vertical bipolar transistor, a step of forming an emitter region and a base region on a main surface of the semiconductor substrate in a depth direction from the surface, A step of forming an emitter electrode in the central portion on the surface of the emitter region, and using the emitter electrode as a mask to remove the emitter region outside the periphery of the emitter electrode to form a protruding island region, The method includes exposing a surface of the base region and forming a base electrode on the exposed surface of the base region.

[0013]

According to the above-mentioned means (1), there are the following effects.

(A) In the vertical bipolar transistor, the periphery of the high impurity concentration of the emitter region and the high impurity concentration region of the base region are separated from each other in the depth direction of the semiconductor substrate, and the high impurity concentration between them is high. Since the junction between the two is abolished, the emitter-base junction capacitance (Cte) can be reduced and the emitter-base junction breakdown voltage can be improved.

(B) Since the base electrode is connected to the surface side of the region having a high impurity concentration in the base region, the connection resistance between the base region and the base electrode can be reduced and the ohmic contact characteristics can be improved.

(C) As a result, the operation speed of the bipolar transistor having the vertical structure can be increased and malfunction can be prevented.

According to the above-mentioned means (2), the emitter region and a part of the base region (substantially operating intrinsic base region) can be processed by using the emitter electrode as a mask, and the emitter has a size corresponding to the size of the emitter electrode. Region and the intrinsic base region can be formed (if the size of the emitter electrode is the minimum processing size, the size of the emitter region and the intrinsic base region can be formed to be the same as the minimum processing size). The intrinsic base region can be self-aligned.

As a result, the vertical type bipolar transistor can be miniaturized, and the integration degree of the semiconductor integrated circuit device can be improved.

The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a vertical structure bipolar transistor.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals and their repeated description will be omitted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A schematic structure of a vertical bipolar transistor mounted on a semiconductor integrated circuit device according to an embodiment of the present invention is shown in FIG. 1 (a cross-sectional view of an essential part) and FIG. 2 (AA in FIG. 1). 1 is a diagram in which the impurity concentration distribution chart cut along the cutting plane is overlapped with the impurity concentration distribution chart cut along the BB cutting plane shown in FIG.

As shown in FIG. 1, a vertical type bipolar transistor mounted on a semiconductor integrated circuit device has an n-type epitaxial layer 3 on a main surface of a p-type semiconductor substrate 1 made of single crystal silicon. It is formed on the main surface of the active region of the semiconductor substrate formed by growth. The periphery of this active region is defined by an element isolation region and is electrically isolated from other active regions. The element isolation region is mainly composed of the p − type semiconductor substrate 1, the p + type semiconductor region (not shown), and the field insulating film 4.

The vertical type bipolar transistor has a semiconductor substrate having a main surface with n in a direction perpendicular to the main surface.
The npn type is formed by sequentially arranging each of the type emitter region, the p type base region, and the n type collector region.

As shown in FIGS. 1 and 2, the n-type collector region is composed of an intrinsic collector region, a graft collector region, and an n + type semiconductor region 5 for raising collector potential. The intrinsic collector region is composed of the n − type semiconductor region 3A which is a part of the n − type epitaxial layer 3 in the active region of the n − type epitaxial layer 3. The n-type semiconductor region 3A is formed with an impurity concentration of about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ³ ], for example. The graft collector region is composed of a buried n + type semiconductor region 2 provided between the p − type semiconductor substrate 1 and the n − type epitaxial layer 3. The buried n + type semiconductor region 2 has a thickness of, for example, 10 ¹⁹ to 10 ²⁰ [at
It is formed with an impurity concentration of about oms / cm ³ ]. The n + type semiconductor region 5 for raising the collector potential is formed in the active region of the n − type epitaxial layer 3 surrounded by the field insulating film 4 in another region close to the intrinsic collector region. The n + type semiconductor region 5 for raising the collector potential is electrically connected to one end of the n + type semiconductor region which is the graft collector region. The n + type semiconductor region 5 for raising the collector potential is provided for the purpose of drawing the collector current from the surface of the semiconductor substrate and reducing the resistance value in the collector current path.

The p-type base region is an intrinsic base region.
(Substantially operating region) and the graft base region. The intrinsic base region is composed of the p-type semiconductor region 6. The p-type semiconductor region 6 is an intrinsic collector region under the protruding island region 7A formed on the main surface of the semiconductor substrate.
It is formed on the main surface of the type semiconductor region 3A. Protruding island area 7
In A, in the active region, the emitter extraction electrode 8 formed on the main surface (surface) of the semiconductor substrate is used as an etching mask, and the surface of the semiconductor substrate outside the periphery of the emitter extraction electrode 8 is It is formed by etching away from the surface in the depth direction. The p-type semiconductor region 6 which is an intrinsic base region is formed of, for example, 10 ¹⁶ to 10 ¹⁷
It is formed with an impurity concentration of about [atoms / cm ³ ] and has a depth of about 0.3 [μm] from the surface of the semiconductor substrate (n-type epitaxial layer 3), that is, the surface of the protruding island region 7A. It has a peak value at the position.

The graft base region is composed of the p + type semiconductor region 11. The p + type semiconductor region 11 is formed on the main surface of the n − type semiconductor region 3A around the p type semiconductor region 6 which is an intrinsic base region, and has a depth from the surface of the semiconductor substrate (the surface of the protruding island region 7A). The p-type semiconductor region 6 is formed at substantially the same position (depth) as the direction. The p + type semiconductor region 11 is in contact with and electrically connected to the periphery of the p type semiconductor region 6. That is, the p + type semiconductor region 11 that is the graft base region is formed on the main surface of the semiconductor substrate outside the periphery of the protruding island region 7A, and is located deeper in the depth direction of the semiconductor substrate than the protruding island region 7A. Is composed of. This p +
The type semiconductor region 11 is, for example, 10 ²⁰ to 10 ²¹ [atoms / c
m ³ ], and has a peak at a position of about 0.3 μm in the depth direction from the surface of the semiconductor substrate (n − type epitaxial layer 3), that is, the surface of the protruding island region 7 A. Has a value. The p + type semiconductor region 11 is provided for the purpose of reducing the connection resistance with the base lead electrode 12 that supplies a base current to the base region (improving ohmic contact characteristics).

The n-type emitter region is composed of the n + -type semiconductor region 7 and the above-mentioned protruding island region 7A.
The n + type semiconductor region 7 which is the emitter region is, for example, 1
It is formed with an impurity concentration of about 0 ²⁰ to 10 ²¹ [atoms / cm ³ ] and has a peak value on the surface side of the semiconductor substrate (n − type epitaxial layer 3), that is, on the upper surface side of the protruding island region 7A. The thickness is about 0.3 [μm] in the depth direction from the surface of the protruding island region 7A. That is, the n + type semiconductor region 7 forms a pn junction with the p type semiconductor region 6 which is the intrinsic base region in which the peak value of the impurity concentration is set on the bottom face of the protruding island region 7A. In addition, the n + type semiconductor region 7 and the p + type semiconductor region 11 which is a graft base region in which the peak value of the impurity concentration is set in a region outside the periphery of the protruding island region 7A (the main surface of the semiconductor substrate) and the semiconductor It is separated in the depth direction of the substrate. That is, in the vertical bipolar transistor, the n + type semiconductor region 7 serving as the emitter region has a high impurity concentration surrounding region and the base region has a high impurity concentration region (p + type semiconductor region 1).
The positions 1) and 1) are separated from each other in the depth direction of the semiconductor substrate, and the junction of high impurity concentration between them is abolished.

N + type semiconductor region 7 which is the emitter region
Are electrically connected to the emitter extraction electrode 8 formed on the surface thereof. That is, the emitter extraction electrode 8 is
The upper surface of the protruding island region 7A is connected to the n + type semiconductor region 7. The emitter extraction electrode 8 is electrically connected to the wiring 15 through the connection hole 13b formed in the insulating film 13. The n + type semiconductor region 7 and emitter extraction electrode 8
Each side wall of the is covered with an insulating film 10.

The p + type semiconductor region 11, which is the graft base region, is electrically connected to the base lead electrode 12 formed on the surface thereof. This base extraction electrode 12
Is formed outside the periphery of the protruding island region 7A, and n +
The type semiconductor region 7 and the emitter extraction electrode 8 are insulated from each other by an insulating film 10. The base extraction electrode 12 is connected to the p + type semiconductor region 11 in a region outside the periphery of the protruding island region 7A. That is, in the vertical bipolar transistor, the base extraction electrode 12 is connected to the surface side of the region (n + type semiconductor region 11) having a high impurity concentration in the base region, and the base extraction electrode that supplies the base current to the base region is connected. The connection resistance with 12 is reduced. The base extraction electrode 12 is electrically connected to the wiring 15 through a connection hole 13 a formed in the insulating film 13.

The n + type semiconductor region 5 for raising the collector potential is electrically connected to the wiring 15 through the connection hole 14a formed in the insulating film 14.

As described above, in the semiconductor integrated circuit device having the vertical type bipolar transistor, the protruding island region 7A formed on the main surface of the semiconductor substrate has the impurity concentration on the upper surface side of the protruding island region 7A. An emitter region (7) having a peak value is provided, and an intrinsic base region (6) having a peak impurity concentration value is set at a pn junction with the emitter region (7) below the protruding island region 7A. A vertical structure bipolar transistor is provided in which each of the graft base regions (11) in which the peak value of the impurity concentration is set is provided outside the protruding island region 7A, and the vertical structure bipolar transistor is formed. Is the protruding island region 7
An emitter lead-out electrode 8 is connected to the emitter region (7) on the upper surface of A, and a base lead-out electrode 1 is attached to the graft base region (11) outside the periphery of the projecting island region 7A.
Connect two. With this configuration, the following operational effects can be obtained.

(A) In a vertical bipolar transistor, a region having a high impurity concentration in the emitter region (7) and a region having a high impurity concentration in the base region (p + type semiconductor region 11)
Since the positions of and are separated in the depth direction of the semiconductor substrate and the junction of high impurity concentration between them is abolished, the emitter-
It is possible to reduce the junction capacitance (Cte) between the bases and improve the breakdown voltage between the emitter and the base.

(B) High impurity concentration region (p
Since the base lead-out electrode 12 is connected to the surface side of the + type semiconductor region 11), the connection resistance with the base lead-out electrode 12 can be reduced (the ohmic contact characteristic can be improved).

(C) As a result, the operating speed of the bipolar transistor having the vertical structure can be increased and the malfunction can be prevented.

Next, a method of manufacturing a vertical type bipolar transistor mounted on the above-described semiconductor integrated circuit device will be briefly described with reference to FIGS. 3A to 3D (cross-sectional views of essential parts shown in each manufacturing process). explain.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, in the formation region (active region) of the vertical type bipolar transistor, the p-type semiconductor substrate 1 is formed.
N-type impurities are selectively introduced into the main surface of.

Next, in the element isolation region (inactive region) that electrically isolates the active region and other surrounding active regions, p-type impurities are selectively applied to the main surface of the p-type semiconductor substrate 1. To introduce.

Next, an n-type epitaxial layer 3 is grown on the entire surface of the p-type semiconductor substrate 1. By the growth of the n-type epitaxial layer 3, the introduced n-type impurities are diffused into the main surface of the active region of the p-type semiconductor substrate 1 and the n-type epitaxial layer 3, respectively. The p-type impurity is the main surface of the inactive region of the p-type semiconductor substrate 1, n-
Each of the epitaxial layers 3 is diffused to form an embedded n + type semiconductor region 2 which is a graft collector region and an embedded p + type semiconductor region (not shown) which is an element isolation region. Further, by growing the n − type epitaxial layer 3 on the p − type semiconductor substrate 1, the semiconductor base body that constitutes the semiconductor integrated circuit device is completed.

Next, a well-known selective oxidation method is used to form a field insulating film 4 on the main surface of the n--type epitaxial layer 3 in the inactive region. This field insulation film 4
Is formed, the n − type semiconductor region 3A formed of a part of the n − type epitaxial layer 3 is formed in the active region. The n-type semiconductor region 3A constitutes an intrinsic collector region. Then, in another region of the active region adjacent to the n-type semiconductor region 3A, n-type impurities are selectively introduced into the main surface of the n-type epitaxial layer 3 surrounded by the field insulating film 4. Then, the n + type semiconductor region 5 for pulling up the collector potential is formed.

Next, p-type impurities are selectively introduced into the main surface of the n--type semiconductor region 3A which is the collector region to form the p-type semiconductor region 6. The p-type semiconductor region 6 is formed by introducing, for example, boron (B) from the surface side of the semiconductor substrate by the ion implantation method. p-type semiconductor region 6
Form the intrinsic base region in the manufacturing process described later. After that, an n-type impurity is selectively introduced into the main surface of the p-type semiconductor region 6 to form an n + type semiconductor region 7. this
The n + type semiconductor region 7 is formed by introducing, for example, arsenic (As) from the surface side of the semiconductor substrate by an ion implantation method. The n + type semiconductor region 7 constitutes an emitter region in a manufacturing process described later.

Next, a polycrystalline silicon film deposited by, eg, CVD method is formed on the entire surface of the semiconductor substrate. An n-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film during or after the deposition. After that, a silicon nitride film deposited by, for example, the CVD method is formed on the entire surface of the polycrystalline silicon film.

Next, the silicon nitride film and the polycrystalline silicon film are sequentially patterned to form an emitter extraction electrode 8 at the central portion on the surface of the n + type semiconductor region 7, as shown in FIG. 3A. Each mask 9 is formed on the surface of the emitter extraction electrode 8.

Next, using the mask 9 as a heat-resistant oxidation mask, the n + type semiconductor region 7 outside the side wall around the emitter extraction electrode 8 and the periphery of the emitter extraction electrode 8 is formed.
Is subjected to a thermal acid treatment to form an insulating film 10 made of a silicon oxide film as shown in FIG. 3B. At this time, an insulating film 5A made of a silicon oxide film is formed on the surface of the n + type semiconductor region 5 for raising the collector potential.

Next, using the mask 9 and the electrode 8 for extracting the emitter as an etching mask, the insulating film 10 on the surface of the p-type semiconductor region 6 is exposed by anisotropic etching. Until it is removed by etching, a protruding island region 7A is formed in the central portion on the surface of the p-type semiconductor region 6. That is, the protruding island region 7A is formed by removing the n + type semiconductor region 7 outside the periphery of the emitter extraction electrode 8. At this time, the insulating film 5A on the surface of the n + type semiconductor region 5 for pulling up the collector potential is also removed. As a result, an emitter region made of the n + type semiconductor region 7 is formed in the protruding island region 7A, and an intrinsic region made of the p type semiconductor region 6 forming a pn junction with the n + type semiconductor region 7 under the protruding island region 7A. A base region is formed. That is, the emitter region and the intrinsic base region are processed by using the emitter extraction electrode 8 as a mask and are formed in a size corresponding to the size of the emitter extraction electrode 8 (if the size of the emitter extraction electrode 8 is the minimum processing size). The size of the emitter region and the intrinsic base region is also formed to be equal to the minimum processing size), and is formed in self-alignment with the emitter extraction electrode 8.

Next, using the mask 9 and the emitter extraction electrode 8 as an impurity introduction mask, p type impurities are selectively introduced into the main surfaces of the n--type semiconductor region 3A and the p type semiconductor region 6. As shown in FIG. 3C, a p + type semiconductor region 11 which is a graft base region is formed. The p + type semiconductor region 11 is formed by introducing, for example, (B) from the surface side of the semiconductor substrate by the ion implantation method.

Next, the exposed p + type semiconductor region 1
1. Polycrystalline silicon is deposited on the entire main surface of the semiconductor substrate including the upper surface by CVD, for example, and then planarized. Then, the polycrystalline silicon film is entirely etched until the surface of the mask 9 is exposed. .. Thereafter, the polycrystalline silicon is subjected to a predetermined patterning to form a base lead electrode 12 on the surface of the p + type semiconductor region 11, as shown in FIG. 3D. An n-type impurity (for example, phosphorus (P)) that reduces the resistance value is introduced into the polycrystalline silicon film during or after the deposition. After that, the mask 9 on the electrode 8 for extracting the emitter is removed.

Next, a thermal oxidation process is performed to form an insulating film 13 on the surface of each of the base extraction electrode 12 and the emitter extraction electrode 8, and the surface of the n + type semiconductor region 5 for increasing the collector potential. An insulating film 14 is formed on top. Each of the insulating film 13 and the insulating film 14 is formed of a silicon oxide film. After that, connection holes 13a and 13b are formed in the insulating film 13 and connection holes 14a are formed in the insulating film 14, respectively, and through these,
A wiring 15 formed of, for example, an aluminum film or an aluminum alloy film in each of the base leading electrode 12, the emitter leading electrode 8, and the collector potential raising n + type semiconductor region 5.
1 is electrically connected, a bipolar transistor having a vertical structure mounted on the semiconductor integrated circuit device is almost completed as shown in FIG.

As described above, in the method of manufacturing the semiconductor integrated circuit device having the vertical type bipolar transistor, the main surface of the semiconductor substrate extends from the surface in the depth direction.
The step of forming each of the n + type semiconductor region 7 and the p type semiconductor region 6, the step of forming the emitter extraction electrode 8 in the central portion on the surface of the n + type semiconductor region 7, and the step of forming the emitter extraction electrode 8 are performed. A step of removing the n + -type semiconductor region 7 outside the periphery of the emitter extraction electrode 8 to form a protruding island region 7A and exposing the surface of the p-type semiconductor region 6 while using it as a mask; And a step of forming a base lead electrode 12 on the exposed surface of the p-type semiconductor region 6. As a result, the emitter region and the intrinsic base region can be processed using the emitter extraction electrode 8 as a mask, and the emitter region and the intrinsic base region can be formed in a size corresponding to the size of the emitter extraction electrode 8 (the size of the emitter extraction electrode is With the minimum processing size, the size of the emitter region and the intrinsic base region can be formed to be equal to the minimum processing size), and furthermore, the emitter region and the intrinsic base region can be formed in self alignment with respect to the emitter extraction electrode 8.

As a result, the bipolar transistor having the vertical structure can be miniaturized, and the integration degree of the semiconductor integrated circuit device can be improved.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

[0052]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

It is possible to increase the operating speed of the vertical type bipolar transistor mounted on the semiconductor integrated circuit device and prevent malfunction.

Further, the degree of integration of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a schematic configuration of a vertical bipolar transistor mounted in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an impurity concentration distribution diagram of a vertical-type bipolar transistor cut along the AA cut surface and the BB cut surface shown in FIG.

FIG. 3A is a cross-sectional view of a principal part showing the manufacturing method of the vertical bipolar transistor at each manufacturing step.

FIG. 3B is a main-portion cross-sectional view illustrating the manufacturing method of the vertical-type bipolar transistor in each manufacturing step.

FIG. 3C is a sectional view of a key portion showing the manufacturing method of the vertical bipolar transistor at each manufacturing step.

FIG. 3D is a sectional view of a key portion showing the manufacturing method for the vertical bipolar transistor at each manufacturing step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Graft collector region n + type semiconductor region, 3 ... n- type epitaxial layer, 3A ... Intrinsic collector region n- type semiconductor region, 4 ... Field insulating film, 6 ... Intrinsic base region A certain p-type semiconductor region, 7 ... an n + type semiconductor region which is an emitter region, 7A ... a protruding island region, 8 ... an emitter extraction electrode, 10 ... an insulating film, 11 ... a p + type semiconductor region which is a graft base region, 12 ... Base extraction electrodes, 13, 14 ... Insulating film, 15 ... Wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsuneo Mitani 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (2)

[Claims] 1. An emitter region and a base region are arranged on a main surface of a semiconductor substrate in a direction perpendicular to the main surface,
In a semiconductor integrated circuit device having a vertical type bipolar transistor in which an emitter electrode is connected to the emitter region and a base electrode is connected to the base region, the projecting island region formed on the main surface of the semiconductor substrate is provided with the projecting island region. An emitter region in which the peak value of the impurity concentration is set is provided on the upper surface side of the island-shaped island region, below the projecting island region on the main surface of the semiconductor substrate, and in each region outside the periphery of the projecting island region. A bipolar transistor having a base region in which a peak value of the impurity concentration is set in the junction with the emitter region or in the vicinity of the junction, and the bipolar transistor is formed on the upper surface side of the protruding island region. Is characterized in that the emitter electrode is connected to the emitter region and the base electrode is connected to the base region in a region outside the periphery of the protruding island region. The semiconductor integrated circuit device according to. 2. An emitter region and a base region are arranged on a main surface of a semiconductor substrate in a direction perpendicular to the main surface,
In a method of manufacturing a semiconductor integrated circuit device having a vertical bipolar transistor in which an emitter electrode is connected to the emitter region and a base electrode is connected to the base region,
A step of forming an emitter region and a base region on the main surface of the semiconductor substrate in a depth direction from the surface thereof;
Forming an emitter electrode in the central portion on the surface of the emitter region, and using the emitter electrode as a mask to remove an emitter region outside the periphery of the emitter electrode to form a protruding island region and A method of manufacturing a semiconductor integrated circuit device, comprising: exposing the surface of the base region; and forming a base electrode on the exposed surface of the base region.