JPH0574816A - Field effect transistor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a FET that achieves low noise, high speed operation, and further high output. Constitution: Between the first and second electron supply layers (31) and (32) made of GaAs doped with n-type impurities, I
First and second non _- doped Ga _{1 -X} with varying n composition x
In _X As graded layers (41) and (42) are provided in a stacked manner. First undoped Ga _1-x In _x
The As graded layer (41) is formed by gradually increasing the In composition x from GaAs and forming a second non-doped Ga layer.
_{The 1-X} In _X As graded layer (42) is made of GaAs on the upper surface by gradually lowering the In composition x from the first graded layer (41) described above. Therefore, most of the carrier electrons are present in the region where the In composition x is maximum, and most of the carrier electrons are the impurities and the spaces doped in the first and second electron supply layers (31) and (32). Will be separated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) which operates at low speed with low noise.

[0002]

2. Description of the Related Art F using n-type GaInAs as a channel
As a conventional technique of ET, for example, JP-A-63-9086
No. 1, JP-A-63-272080, JP-A-6
There is a publication such as 4-2371.

[0003]

In these techniques, G
Since Si is uniformly doped in the aInAs channel layer, electrons serving as carriers are scattered by this Si,
Sufficient velocity overshoot effect was not obtained and sufficient characteristics were not obtained. Further, Japanese Patent Laid-Open No. 63-90861 also discloses a technique of planarly doping Si in a GaInAs channel layer. However, it is difficult to form an FET having a deep gate threshold voltage Vth only with the planar doped layer. Therefore, there are problems that an FET having a high output cannot be manufactured and that there is a small margin in circuit design.

Therefore, the present invention provides a FET that uses GaInAs as a channel, operates at a higher speed with less noise than a conventional FET, and has a high output.

[0005]

In order to achieve the above object, the FET according to the present invention is provided with an I-channel between the first and second electron supply layers made of GaAs doped with an n-type impurity.
First and second non-doped Ga having different n composition x
_1-X In _X As graded layers are provided in a stacked manner. The first non _- doped Ga _1-x In _x As graded layer is formed by gradually increasing the In composition x from GaAs, and the second non _- doped Ga _1-x In _x As graded layer is formed from the above-mentioned first The In composition x is gradually lowered from the graded layer to be GaAs on the upper surface.

In the structure of the FET according to the present invention, the aforementioned first and second electron supply layers may be delta-doped with n-type impurities.

[0007]

The non _- doped Ga _1-X In is provided between the first and second electron supply layers made of GaAs doped with impurities.
_{An X} As graded layer is provided. The In composition x of the graded layer gradually increases from above the first electron supply layer, and gradually decreases as it approaches the second electron supply layer. Therefore, the most carrier electrons are present in the region where the In composition x is maximum, and most of the carrier electrons are spatially separated from the impurities doped in the electron supply layer. Therefore, the influence of the scattering on the carrier electrons by the impurities is reduced, and a sufficient velocity overshoot can be obtained.

By delta-doping the impurities, the positions where the impurities are present and the positions where the carrier electrons are present can be further separated.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a FET according to a first embodiment of the present invention.
FIG. 6 is a process sectional view showing a manufacturing process of. A GaAs substrate 1 is used as a semiconductor substrate, and a non-doped GaAs buffer layer 2 (background p type, on the GaAs substrate 1 is formed by, for example, a metal organic chemical vapor deposition method (OMVPE method).
p = 3 × 10 ¹⁵ cm ⁻³ ) is epitaxially grown to a thickness of 5000 Å (see FIG. 1A).
Next, Ga uniformly doped with Si as an n-type impurity
The first electron supply layer 31 made of As (carrier density n =
4 × 10 ¹⁸ cm ⁻³ ) is grown to a thickness of 50 Å (see FIG. 1 (b)). The first electron supply layer 3
1. The first non _- doped Ga _{1 -X} In _X As graded layer 41 having a thickness of 50 angstroms is formed by gradually increasing the In composition x from GaAs, and the x value is 0.15 in the uppermost layer. Let it grow. Next, x is 0.15
It is gradually lowered from the second layer, and the uppermost layer is GaAs.
Undoped Ga _1-x In _x As graded layer 42
To a thickness of 50 Å. The second
On the graded layer 42 of Si as an n-type impurity.
A second electron supply layer 32 (n = 4 × 10 ¹⁸ cm ⁻³ ) made of GaAs uniformly doped with is grown to a thickness of 50 Å (see FIG. 1C). On the second electron supply layer 32, a cap layer 5 made of non-doped GaAs is grown to a thickness of 400 Å. Finally, the gate electrode 6, the source electrode 7, and the drain electrode 8 are formed on the cap layer 5 to form the FET of this embodiment.

Next, the operation of the FET thus manufactured will be described with reference to the energy band diagram of FIG. FIG. 2A is an energy band diagram in which a channel portion of a conventional n-type GaInAs channel FET uniformly doped with Si is enlarged. In the figure, reference numeral 21
Indicates a GaAs channel layer, reference numeral 22 indicates a GaAs buffer layer, reference numeral 23 indicates a cap layer, reference numeral 24 indicates a conduction band level, and reference numeral 25 indicates a valence band level. On the other hand, FIG. 2B is an enlarged energy band diagram of the channel portion of the FET of the present invention. In this figure, portions corresponding to the respective epitaxial layers 2 to 5 in FIG. 1 are indicated by the same reference numerals, reference numeral 26 indicates a conduction band level, and reference numeral 27 indicates a valence band level. Note that in FIGS. 2A and 2B, E ₀ , E
₁ and E _F represent the quantized energy levels, and the curves 91 and 92 shown by the alternate long and short dash lines represent the existence probabilities of electrons at the energy levels E ₀ and E ₁ , respectively.

As can be seen from these two figures, the conventional F
In ET (see FIG. 2A), the region where electrons exist is almost in the quantum well of the n-type GaInAs channel layer 21, and the electrons are scattered by Si in GaInAs, so that sufficient velocity overshoot cannot be obtained. .. Therefore, increase of source resistance and transconductance (gm)
Result in a decrease. On the other hand, in the FET of the present invention (see FIG.
(See (b)) shows that most of the region where carrier electrons are present is the undoped Ga _{1 -X} In _X As graded layer 4.
The electron existence probability 91 becomes maximum at the bottom of the quantum well corresponding to the boundary region between the graded layers 41 and 42 having the maximum In composition. Since Si, which is an impurity, hardly exists in the graded layers 41 and 42, carrier electrons are hardly affected by scattering by Si. Therefore, it has a higher velocity overshoot than conventional FETs, and therefore has a lower source resistance, higher transconductance (g
m) can be obtained.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be explained.

FIG. 1A shows an FET according to the second embodiment.
3 is a structural cross-sectional view of FIG. The manufacturing method of the FET of this embodiment is basically the same as that of the first embodiment, but Si in the first and second GaAs electron supply layers 33 and 34 is due to delta doping (broken line in the figure). part). That is, for the first and second electron supply layers 33 and 34, after non-doped GaAs is epitaxially grown, Si is doped in a sheet shape with an atomic layer thickness of Si to an intermediate depth of each layer by an ion implantation method. It is a thing.

FIG. 3B shows the FET of the second embodiment.
FIG. 4 is an energy band diagram in which a channel portion of FIG.
In this band diagram, each epitaxial layer 2 of FIG.
Parts corresponding to 5 are indicated by the same reference numerals, and other parts are indicated by the same reference numerals in the same portions as those in the first embodiment. As can be seen from the figure (b), most of the region where carrier electrons are present is undoped Ga.
_{The 1-X} In _X As graded layers 41 and 42 have the highest electron existence probability 91 at the bottom of the quantum well corresponding to the boundary region between the graded layers 41 and 42 having the highest In composition. .. In addition, since the impurities are delta-doped in a sheet shape, the presence position of Si 9
The distance between 2 and the carrier electron existence position 91 is farther than in the structure of the first embodiment, and the scattering of carrier electrons due to the influence of Si can be further reduced. Therefore, it is possible to effectively obtain an FET having a low source resistance and a high transconductance (gm), which has a velocity overshoot higher than that shown in the first embodiment.

[0015]

As described above, according to the FET of the present invention, scattering due to impurities is significantly reduced as compared with the conventional FET using GaInAs as the channel layer, so that the low source resistance and the high transconductance ( gm) can be obtained. Therefore, low noise and high speed operation can be achieved, and a high output FET can be obtained.

Further, G which is not lattice-matched to GaAs
Since the aInAs channel is formed of the GaInAs graded layer, it has the effect of alleviating the strain due to lattice matching, and the effect of improving the electron transport characteristics can also be expected.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing an FET, which is a first embodiment of the present invention.

FIG. 2 is an energy band diagram for explaining the operation of the first embodiment.

FIG. 3 is a diagram showing a FET structure according to a second embodiment of the present invention and its energy state.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate, 2 ... Buffer layer, 31 ... 1st channel layer, 32 ... 2nd channel layer, 41 ... 1st graded layer, 42 ... 2nd graded layer, 5 ... Cap layer, 6 ... gate electrode, 7 ... source electrode, 8 ... drain electrode

Claims (2)

[Claims] 1. A semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate and made of a high-resistance semiconductor lattice-matched to GaAs, and an n-type impurity formed on the buffer layer. And a first non _- doped Ga _1-X In layer formed on the first electron supply layer by gradually increasing the In composition x from GaAs.
_{An X} As graded layer, and a second non _- doped Ga _{1 -X} formed on the first graded layer, in which the In composition x is gradually reduced from the first graded layer to be GaAs on the upper surface. In _X
An As graded layer, a second electron supply layer formed on the second graded layer and made of GaAs doped with an n-type impurity, and a second electron supply layer formed on the second electron supply layer. A
A field effect transistor comprising: a cap layer made of 1GaAs; and source, drain, and gate electrodes formed on the cap layer. 2. The field effect transistor according to claim 1, wherein the first and second electron supply layers are delta-doped with n-type impurities.