JPH0574865B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an interface auxiliary device that connects a computer and a terminal device. The present invention relates to an interface auxiliary device for connecting a terminal device with a terminal device.

[Background of the invention]

Some computers have a direct memory access (DMA) function on the interface, while others do not, and the terminal device also has a direct memory access (DMA) function.
Some have DMA functionality and others do not.
The DMA function is a function in which the computer's central processing unit (CPU) sets the data necessary for the transfer, such as the transfer start address and the number of data to be transferred, to the input/output device when transferring data between the computer's memory and the terminal device. The data transfer is then performed between the memory and the terminal device via the input/output device until all data transfer is completed, and after the transfer is completed, an interrupt is placed on the CPU to perform post-transfer processing. means something that causes someone to do something. Computers and terminal devices are DMA
If the computer has this function, data transfer is performed at high speed, but many control signals related to data transfer are required between the computer and the terminal device, and some control signals exist simultaneously with input and output data. If the computer or terminal device does not have a DMA function, the CPU will be interrupted every time one unit of data is transferred, and the data transfer will be performed under the control of the CPU.
In this case, the data transfer speed is slower than when the device has a DMA function, but there are fewer control signals regarding data transfer between the computer and the terminal device.

Computers and terminal devices with DMA functionality are currently widely used due to their high speed.
There often arises a desire to connect a computer that does not have a DMA function on its interface to a terminal device that does have a DMA function. In this case, an auxiliary interface device is required between the computer and the terminal device to ensure consistency between the two, and it is necessary to create control signals related to the DMA function while preventing data transfer speed from decreasing. .

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems and to solve the problems described above, and to
An object of the present invention is to provide an auxiliary interface device for connecting a terminal device with a DMA function.

[Summary of the invention]

The interface auxiliary device according to the present invention includes an input register that receives computer output data as input and whose output is connected to a terminal device input data terminal, receives state information and transfer data from the terminal device as input, and outputs the input register. is connected to the output register connected to the computer data input terminal, and the output of the input register to store control data from the computer, and receives input control signals related to reading and writing data from the computer and terminal device, respectively. a control signal generation circuit that generates an output control signal related to reading and writing data to be sent to each of the devices; the control signal generation circuit generates a predetermined control signal that is sent from the interface auxiliary device to each of the computer and the terminal device;
between the computer and the interface auxiliary equipment;
and controls data transmission and reception between the interface auxiliary device and the terminal device.

For terminal devices with DMA function, commands such as data block read or write start or end commands are required.
There is a control signal that is not present in the interface of a computer that does not have a DMA function, and this is data from the computer that sends control information to the interface auxiliary device, and the interface auxiliary device uses this control data to control the interface with the terminal device. It converts it into a signal and sends it to the terminal device. For interface control signals that require a reset immediately after the transfer is completed in order to perform high-speed data transfer processing with the terminal device, such as the data transfer possible display requested by the terminal device during data transfer, the interface control signal is Sending is started by control data from the computer, and controlled using control signals sent and received each time data is transferred between the computer and the terminal device via an interface auxiliary device so that sending can be stopped immediately after the transfer is completed. ing.

[Embodiment of the Invention] An embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 1 is an embodiment of an interface auxiliary device according to the present invention, and the interface auxiliary device 1 connects a computer 2 that does not have a DMA function on the interface and a terminal device 3 that has a DMA function. placed between them to connect these devices.

Between the interface auxiliary device 1 and the computer 2, there are 16-bit output data from the computer 2, 16-bit input data to the computer 2, and a read/write request interrupt signal DC from the computer as a control signal. A read/write completion interrupt signal DF is sent and received to the computer. Information sent and received between the interface auxiliary device 1 and the terminal device 3 includes 16-bit output data to the terminal device 3, 16-bit input data from the terminal device, and control signals from the interface auxiliary device 1 to the terminal device 3. read/write command signals FNCT1 to 3, read/write status display signal ready, data block transfer start signal go, signal busy indicating input/output data register operation in progress, read/write end display signal for each unit data end cycle. Yes, as control information from the terminal device 3 to the interface auxiliary device 1, a signal ATTN indicating that the terminal device 3 is in a read/write state, and a status output from the terminal device 3 at the end of data block transfer or at the time of a failure. There are signals DSTATA to C, a data transfer direction (read/write) display signal CL control, and a read/write request signal cycle request output by the terminal device for each unit data transfer.

Before transferring data between the computer 2 and the terminal device 3, preparatory operations are first performed.
First, 16-bit data including read or write command information is sent from the computer 2, and the level of the control signal DC changes from high to low. In response to this DC level change, the interface auxiliary device 1
A signal obtained by delaying the DC signal by the monomulti 5 via the switching circuit 4 is applied as a control signal to the input register 7 via the exclusive OR circuit 6, and the signal is output from the computer 2.
Read 16-bit data into input register 7. The switching circuit 4 transfers the control signal ready sent from the ready flip-flop 8 to the terminal device 3 to the mono multi 9, and when the signal delayed by the flip flop 10 is high, it applies DC to the mono multi 5, and when the signal is low, it applies DC to the mono multi 5.
This is a circuit that performs switching so that DC is applied to the AND circuit 11. The signal from the flip-flop 10 corresponding to the ready signal is used to identify whether the data sent and received between the computer 2 and the interface auxiliary device 1 is control data or data transferred to and from the memory of the computer 2. The interface auxiliary device 1 and the computer 2 delay the ready by the monomulti 9 and flip-flop 10.
This is to prevent malfunctions from occurring even if there is a delay in response to a DC level change controlled by the computer 2 in response to a DF level change from the interface auxiliary device 1 to the computer 2 during data transmission and reception between the interface auxiliary device 1 and the computer 2. Although not shown, Mori Multi 5
A control signal for data transfer to the judgment circuit 12, register 13, etc. in the interface auxiliary device 1 is generated from the output of the control circuit 1 through a delay circuit. The data set in the input register 7 is sent to the judgment circuit 12.
is set to The determination circuit 12 is a circuit that determines the type of control data from the computer 2. If the most significant bit (MSB) of the control data is 1, it is information about the number of data to be transferred, and if it is 0, it is information other than the number of data to be transferred. judge. In the case of control data for read/write instruction information, its MSB is 0, and it is set from the input register 7 to the register 13 according to the judgment result of the judgment circuit 12, and the read or write instruction signals FNCT1 to 3 are output from the register 13. It is sent to the terminal device 3.

After identifying the change in DC from high to low, the interface auxiliary device 1 changes the read/write completion interrupt signal DF from high to low to the computer 2 via the exclusive OR circuit 14 and the delay circuit 15, and responds to this. Then, the computer 2 sends out control data including information representing the two's complement of the number of transferred data, and the interface auxiliary device 1 receives this data in the input register 7 in response to the change of DC from high to low, and sends this data to the judgment circuit. 1
2, the information is identified as transfer data number information and set in the word counter 16. The preparation for data transfer is now complete.

When the terminal device 3 receives a read or write command from FNCTs 1 to 3, the terminal device 3 sends an ATTN indicating that reading or writing is possible to the interface auxiliary device 1 along with a CI control indicating the data transfer direction. sets these information to the output register 19 via the register 17 and the switching circuit 18. The switching device 18 gates control data such as ATTN from the terminal device 3 to the output register 19 when the signal from the flip-flop 10 is high, and outputs 16-bit transfer data from the terminal device 3 when the ready signal is low. register 1
Gate to 9. Before the start of data transfer, ready is high, and control data from the terminal device 3 is set in the output register 19. The contents of the output register 19 are constantly updated by the control data from the terminal device 3, and the computer 2 repeatedly reads the contents of the output register 19, and the ATTN changes from high to low, changing from 1 to 1 of the ATTN equivalent bit in the control data. Check whether there is a change to 0.

When detecting that ATTN changes from high to low, computer 2 sends control data to start data transfer, and interface auxiliary device 1 receives this control data.
Set it in input register 7 according to the DC level change, then set it in register 13, and then set it in register 1.
A data transfer start signal Go of 200 ns is sent from the terminal device 3 to the terminal device 3 via the monomulti circuit 20.
Further, the ready flip-flop 8, which was initially reset, is set by Go, and the ready signal to the terminal device 3 changes from high to low, indicating that reading and writing are possible on the terminal device 3. Flip-flop 10 is also set by GO.

When transferring data from the computer 2 to the terminal device 3, the computer 2 sends the first data after sending data transfer start information. When the interface auxiliary device 1 receives a cycle request from the terminal device 3, it switches to the busy flip-flop 2.
1 to set the busy level to terminal device 3 to high,
Also, word counter 16 is set to 1 by cycle request.
Add one. The flip-flop 10 is set and a low signal is applied to the switching circuit 4, and the DC from the computer 2 is inverted and applied to the AND circuit 11. Since the computer 2 makes the DC low at the same time as sending data, the AND circuit 11 supplies an output because the DC is low and the busy signal is low, and the monomulti 22 generates a 100 ns pulse signal. This signal is sent as a control signal to the input register 7 via the exclusive OR circuit 6, and sets the data from the computer 2 to the input register 7.
It also resets the busy flip-flop 21 and sends an end cycle to the terminal device 3. When the terminal device 3 receives the end cycle and the busy level changes from high to low, it recognizes that the data is being sent from the interface auxiliary device 1 and reads the data. The interface auxiliary device 1 sends the end cycle to the terminal device 3 and changes the DF to the computer 2 from high to low by the output of the AND circuit 11 via the exclusive OR circuit 14 and the delay circuit 15. In response, the computer 2 sends out the next data and changes DC from high to low.

The second and subsequent data from the computer 2 are similarly sent to the terminal device 3 via the interface auxiliary device 1. When transferring the last data, when the word counter 16 is incremented by a cycle request from the terminal device 3, the word counter 16 becomes 0 and generates an output, which causes the AND circuit 23 to issue a reset signal. Exclusive
Ready flip-flop 8 via OR circuit 24
to reset this. By resetting the ready flip-flop 8, the ready signal to the terminal device 3 changes from low to high. After reading the data from the interface auxiliary device 1, the terminal device 3 identifies that the data transfer has ended since the ready signal is high, and does not send a cycle request. When the data transfer is completed, the computer 2 sends out a completion indication as control data, and the interface auxiliary device 1 receives this control information in the input register 7 and register 13
, and send a completion indication to the terminal device 3 using FNCT1-3. The terminal device 3 displays the status in DSTAT A to C according to the completion display to the interface auxiliary device 1.
The interface auxiliary device 1 sends this to the output register 1 via the register 17 and the switching device 18.
9 and send it to computer 2. When the computer 2 confirms that the terminal device 3 has received the data normally based on the status display of the terminal device 3, the computer 2 ends the data transfer process.

When reading data from the terminal device 3 into the computer 2, in the data transfer preparation stage, the computer 2 sends a read command and the number of read words as control data to the interface auxiliary device 1, and the interface auxiliary device 1 reads the data. The read command is sent to FNCT1 by the same operation as for write preparation.
-3 is sent to the terminal device 3, and the number of read words is set in the word counter 16. Next, in response to control data for starting transfer from the computer 2, a go signal is sent to the terminal device 3, and the ready flip-flop 8 is set to change the ready signal to the terminal device 3 from high to low. The computer 2 makes a read request to the interface auxiliary device 1 by changing DC from high to low. The terminal device 3 sends data and also provides cycle request pulses to the interface auxiliary device 1. In the interface auxiliary device 1, the busy flip-flop 21 is set by a cycle request as in the case of data writing, the busy level to the terminal device 3 is set high, and the word counter 16 is incremented by one. Interface auxiliary device 1 is busy because the DC from computer 2 is low.
The output of the AND circuit 11 sends a control signal to the output register 19 via the monomulti 22 and the exclusive OR circuit 25, sets the data from the terminal device 3 in the output register 19, and changes the DF to the computer 2 from high to low. and send a read request. It also sends an end cycle pulse to the terminal device 3, resets the busy flip-flop 21, and changes the busy state of the terminal device 3 from high to low. The terminal device 3 receives the end cycle and transmits the next data because the busy level is low. Thereafter, data is sequentially transferred from the terminal device 3 to the computer 2 in the same manner. The word counter 16 is incremented by the cycle request when sending the last data from the terminal device 3 to the interface auxiliary device 1, so that the content of the word counter 16 becomes 0, the ready flip-flop 8 is reset, and the terminal device Ready to 3 goes from low to high. The terminal device 3 thereby identifies the end of the data transfer and stops sending further cycle requests to the interface auxiliary device 1. Sending of the end display control data from the computer 2 and sending of the status display from the terminal device 3 are performed in the same manner as in the case of data writing, and the data reading process is completed.

If data transfer is stopped due to a transfer error occurring during data transfer, the terminal device 1 will not output a cycle request signal, and the word counter 16 will no longer operate. Therefore word counter 1
6 is not reset and the ready signal to the terminal device 3 is fixed at low, the data transfer is not completed and subsequent data exchange is disabled. In order to prevent this, the interface auxiliary device 1 allows the terminal device 3 to
The cancel information outputted to DSTAT A to C is identified by a decoder circuit in the register 17, and the ready flip-flop 8 is reset to make the ready signal high.

It is necessary for a terminal device with a DMA function to continue sending a ready signal, which indicates read/write capability, while data is being transferred, and to stop the ready signal when the data transfer is complete. If the ready continues to be sent even after the data transfer is completed, the terminal device determines that the data transfer is to be continued and sends a cycle request for data transfer request, and if no data transfer occurs, it determines that there is a failure. Put it away. In order to solve this problem, in this embodiment, at the start of data transfer, the computer sends information indicating the number of transferred words to the interface auxiliary device and sets it in the word counter in the device, and the computer sends the transfer start information to the interface auxiliary device. The data is sent to the ACE auxiliary device and starts ready sending to the terminal device, counts the word counter every time unit data is transferred, and stops ready sending when the number equal to the number of transferred words set in the word counter is counted. ing. There may be cases where the originally set number of data is not transferred due to a failure or the like, but in such cases, ready transmission is stopped using cancel information from the terminal device.

During data transfer, the terminal device sends out a cycle request, which is a data transfer request, for each piece of data, and upon receiving an end cycle, which indicates the end of the transfer, starts the next data transfer process. When the interface auxiliary device receives a data transfer request from a terminal device, it is necessary to confirm that the computer is ready for data transfer and then perform the transfer process, so in this embodiment, it receives a cycle request from the terminal device. Immediately, it sends a busy signal to the terminal device indicating that the input/output register of the interface auxiliary device is being operated, performs transfer processing with the computer, and then sends an end cycle to the terminal device.

〔Effect of the invention〕

According to the present invention, DMA can be achieved with an extremely simple configuration.
It is possible to connect a computer that does not have a function on the interface with a terminal device that has a DMA function. In particular, it is possible to properly create control signals necessary for connection with a terminal device that is not on the computer interface, and to connect the computer and the terminal device. Data transfer between the two can be performed smoothly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of an embodiment of an interface auxiliary device according to the present invention. 1... Interface auxiliary device, 2... Computer, 3... Terminal device, 5, 9, 20, 22...
...Monomulti, 8, 10, 21...Flip-flop, 7...Input register, 15...Delay circuit,
16...word counter, 18...output register.

Claims (1)

[Claims] 1. A computer that does not have a high-speed data transmission direct memory access function on its interface and a terminal device that has a direct memory access function, and uses the direct memory access function to transfer data from the computer. An interface auxiliary device for writing to a terminal device and reading data from the terminal device to a computer, which connects the computer and the terminal device and enables high-speed data transmission using a direct memory access function. An input register that receives computer output as input and whose output is connected to the terminal device input data terminal, and an output that receives status information and transmission data from the terminal device as input and whose output is connected to the computer data input terminal. A register, a word counter in which information about the number of transfer words indicating the length of a data block to be transferred at one time is set as a two's complement value, which is given as control data from the computer, and a read/write request given from the terminal device for each unit data transfer. A circuit that increments the word counter in response to a signal, and when the value of the word counter reaches a number equal to the set number of transfer words, it informs the terminal device that the transfer of the data block has ended, and is readable and writable. A circuit that stops the output of control signals that indicate the status. If data transfer is stopped due to a failure during data transfer, the terminal device outputs the A circuit that constantly monitors status information and uses that information to stop outputting a control signal indicating read/write status to a terminal device, a circuit that identifies whether computer output is control data or transfer data, and a circuit that identifies whether computer output is control data or transfer data. A circuit that responds to the read/write request interrupt signal DC and outputs a read/write completion interrupt signal DF to the computer.
A circuit that outputs a command signal that tells the terminal device whether the next data block transfer is a read from the terminal device or a write to the terminal device, a circuit that outputs a data block transfer start signal to the terminal device, a terminal device A circuit that outputs a signal indicating that the computer is operating an input/output data register to a terminal device in response to a read/write request signal given for each unit of data from the computer, and a read/write request interrupt signal from the computer. In response to this, the computer stops outputting a signal to the terminal device indicating that the input/output data register is being manipulated;
A circuit that outputs a signal indicating the end of reading/writing for each unit of data to a terminal device, and a circuit that outputs a signal input from the terminal device to the computer indicating that the terminal device is in a readable/writable state, and data A circuit that outputs a status signal output from a terminal device to a computer at the end of a block transfer or at the time of a failure, and a command signal that tells whether the data block transfer is a read from the terminal device or a write to the terminal device. An interface auxiliary device consisting of a circuit that outputs a response signal from a terminal device to a computer.