JPH0574895A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] With respect to an LSI having a built-in self-test circuit, not only the quality judgment but also the cause analysis when a defect occurs can be easily performed. [Structure] Outputs of LFSRs 5 _{1 to} 5 ₁₄ are output to pads 9 _{2 to} 9 ₄ , 9 _{6 to} 9 ₈ , 9 provided on the inner side of the peripheral portion of the element formation surface 2.
_{10 to} 9 ₁₂ , 9 _{14 to} 9 ₁₆ , 9 ₁₉ and 9 ₂₀ are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as "LSI") which incorporates a self-test circuit and employs a so-called BIST (Built In Self Test) method.

[0002]

2. Description of the Related Art Conventionally, as this type of LSI, an LSI whose plan view is shown in FIG. 3 is widely known.

In the figure, 1 is an LSI main body, 2 is an element formation surface,
Reference numeral 3 denotes an input / output circuit formed in the peripheral portion of the element formation surface 2, 4
_{1-4 8} is a functional block is a circuit under test which is formed on the inner periphery of the element forming surface 2.

[0004] 5 ₁ to 5 ₁₄ is a shift register for testing the linear feedback shift register (li
near feedback shift register. Hereinafter, referred to as LFSR), 6 is a multiplexer, and 7 is a test control circuit (BIST control circuit) that controls a test.

[0005] Here, LFSR5 ₁ ~5 ₁₄ is divided into five groups, and a shift register array 8 _{1-8 5.} The shift register train 8 ₁ is composed of a series circuit of LFSRs 5 _{1 to} 5 ₃ , and the shift register train 8 1
₂ is composed of a series circuit of LFSRs 5 _{4 to} 5 ₆ .

Further, the shift register train 8 ₃ has an LFSR.
The shift register array 8 ₄ is composed of a series circuit of 5 _{7 to} 5 _{9 and} the series circuit of LFSRs 5 _{10 to} 5 ₁₂ . In addition, the shift register train 8 ₅ has the LFSR ₅
It is composed of a series circuit of ₁₃ and 5 ₁₄ .

[0007] This LSI is
A mode designating signal designating various test modes, test data, and a scan clock necessary for the test are supplied from the outside, and the compressed test results output from the shift register trains 8 ₁ to 8 ₅ are passed through the multiplexer 6. And output it to the outside.

[0008]

In such a conventional LSI, it is possible to obtain a compressed test result for each of the shift register rows 8 ₁ to 8 ₅ , so that it is possible to easily perform a pass / fail judgment. However, if only the test result compressed for each of the shift register rows 8 ₁ to 8 ₅ is obtained, there is a problem that it is difficult to analyze the cause when a defect occurs.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide an LSI capable of easily performing not only a pass / fail judgment but also a cause analysis when a defect occurs.

[0010]

The LSI according to the present invention comprises:
The present invention is to improve a semiconductor integrated circuit device in which a plurality of test shift registers are formed together with a circuit under test inside a peripheral portion of an element formation surface of a substrate, and the element formation is performed corresponding to the plurality of test shift registers. A pad for connecting to an external circuit is provided at a desired position inside the peripheral portion of the surface, and output terminals of a plurality of test shift registers are connected to corresponding pads, respectively.

[0011]

In the present invention, the output terminals of the plurality of test shift registers are connected to the corresponding pads, respectively.
The output of multiple shift registers for testing can be observed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to FIGS. 1 and 2, those parts corresponding to those in FIG. 3 are designated by the same reference numerals, and a duplicate description thereof will be omitted.

First Embodiment FIG. 1 is a plan view showing a first embodiment of the present invention. In the first embodiment, the shift register rows 8 ₁ to 8 ₅ formed by the LFSRs 5 _{1 to} 5 ₁₄ are designed so that the test control circuit 7 can perform parallel scanning.

In the first embodiment, the pads 9 _{1 to} 9 ₂₀ for connecting to external circuits are arranged in a matrix on the inner side of the peripheral portion of the element forming surface 2 so as to correspond to the LFSRs 5 _{1 to} 5 _14. The output terminals of the LFSRs 5 _{1 to} 5 ₁₄ are provided with pads 9 _{2 to} 9 ₄ , 9 _{6 to} 9 ₈ , 9 _{10 to} 9 ₁₂ , 9 _{14 respectively.}
To 9 _16, 9 _19, connected to the 9 _20, the output of LFSR5 ₁ ~5 _14, respectively, the pad 9 ₂ to 9 _4, 9 ₆ to 9 _8, 9 ₁₀ to 9
It is configured to be obtained via ₁₂ , 9 _{14 to} 9 ₁₆ , 9 ₁₉ , and 9 ₂₀ .

Therefore, in this first embodiment,
Multiplexer 6 included in the conventional LSI shown in FIG.
Is not provided. Others are the same as those of the conventional LSI shown in FIG.

According to the first embodiment, the LFSR5 ₁
〜5 ₁₄ parallel scan, LFSR during the test
Since the outputs 5 _{1 to} 5 ₁₄ can be obtained and observed, not only the quality judgment but also the cause analysis when a defect occurs can be easily performed.

Second Embodiment FIG. 2 FIG. 2 is a plan view showing a second embodiment of the present invention. In this second embodiment, LFSR5 ₁ ~5 ₁₄ are connected in series, the test control circuit 7, these LFSR
It is configured so that 5 _{1 to} 5 ₁₄ can be serially scanned.

[0018] In the second embodiment, the pad 9 ₁ to 9 ₂₀ to achieve connection to an external circuit to correspond to LFSR5 ₁ ~5 ₁₄ inside periphery of the element forming surface 2 is in a matrix It is provided.

However, in the second embodiment, the LFS is
An output terminal of R5 ₁ to 5 _14, respectively, the pads 9 ₂ ~
9 ₇ , 9 _{10 to} 9 ₁₅ , 9 ₁₉ , 9 ₂₀ connected to the LFSR 5
The outputs of _{1 to} 5 ₁₄ are output to pads 9 _{2 to} 9 ₇ and 9 ₁₀ to, respectively.
It is configured to be obtained via 9 ₁₅ , 9 ₁₉ and 9 ₂₀ . Others are similar to those of the first embodiment.

According to the second embodiment, the LFSR5 ₁
5 ₁₄ When serial scan, during the test, LFSR
5 ₁ to 5 ₁₄ to obtain an output of, it is possible to observe this, as in the first embodiment, not quality determination only, can be easily carried out can also cause analysis when a failure has occurred ..

[0021]

According to the present invention, a pad for establishing connection with an external circuit is provided at a desired position inside the peripheral portion of the element formation surface corresponding to a plurality of test shift registers, and a plurality of test registers are provided. By adopting a configuration in which the output terminals of the shift register of are connected to the corresponding pads respectively, it is possible to observe the outputs of multiple shift registers for testing during the test, so that not only the pass / fail judgment can be performed. Also, the cause analysis when a defect occurs can be easily performed.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 LSI main body 2 Element formation surface 3 Input / output circuit 4 ₁ to 4 ₈ Functional block 5 _{1 to} 5 ₁₄ Linear feedback shift register (LFSR) 7 Test control circuit (BIST control circuit) 9 _{1 to} 9 ₂₀ pads

Claims (3)

[Claims] 1. A semiconductor integrated circuit device in which a plurality of test shift registers are formed together with a circuit under test inside a peripheral portion of an element formation surface of a substrate, wherein the plurality of test shift registers are made to correspond to the test shift registers. A pad for connecting to an external circuit is provided at a desired position inside the peripheral portion of the element formation surface, and output terminals of the plurality of test shift registers are respectively connected to corresponding pads. A semiconductor integrated circuit device characterized by the above. 2. The plurality of shift registers for testing constitute a plurality of shift register trains each including one or a plurality of shift registers connected in series, and the plurality of shift register trains can be scanned in parallel. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured. 3. The semiconductor integrated circuit according to claim 1, wherein the plurality of test shift registers are connected in series so that the plurality of test shift registers can be serially scanned. apparatus.