JPH0574896A - Semiconductor devices - Google Patents
Semiconductor devicesInfo
- Publication number
- JPH0574896A JPH0574896A JP3234199A JP23419991A JPH0574896A JP H0574896 A JPH0574896 A JP H0574896A JP 3234199 A JP3234199 A JP 3234199A JP 23419991 A JP23419991 A JP 23419991A JP H0574896 A JPH0574896 A JP H0574896A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- properties
- semiconductor device
- gate electrode
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 3
- 238000005259 measurement Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000013024 troubleshooting Methods 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
ＭＯＳトランジスタの電気特性チェックトランジスタの
構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a MOS transistor electrical characteristic check transistor.
【０００２】[0002]
【従来の技術】従来の半導体装置内に形成されている電
気特性チェックトランジスタは、通常のＭＯＳトランジ
スタを形成した後、絶縁用膜を付し、その後ゲート電極
及び拡散層領域にコンタクト孔を開孔し、アルミニウム
などの電極パッドを形成した構造を有している。2. Description of the Related Art An electrical characteristic check transistor formed in a conventional semiconductor device has a normal MOS transistor formed thereon, an insulating film attached thereto, and then a contact hole formed in a gate electrode and a diffusion layer region. However, it has a structure in which electrode pads such as aluminum are formed.
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体装置
では、電気特性チェックトランジスタの電極パッドがア
ルミニウムなどで形成されているため、コンタクト開
孔、アルミニウム配線工程が終了するまでは、半導体装
置内のＭＯＳトランジスタの電気特性をチェックするこ
とが不可能であった。つまり、ＭＯＳトランジスタの特
性はゲート電極を構成し、拡散層領域を形成した後、し
かる熱処理を行う事により、トランジスタの特性が決定
されている。しかし、この場合測定用電極パッドが存在
しないため測定そのものが困難であった。電気特性チェ
ックトランジスタの目的は、トランジスタの電気的特性
をモニターする事にあるが、従来の方法による半導体装
置では、電気的特性決定工程での異常現象を発見するの
が遅れる問題があり、結果的に半導体装置の品質及び歩
留低下をもたらしていた。In this conventional semiconductor device, since the electrode pad of the electrical characteristic check transistor is formed of aluminum or the like, the semiconductor device inside the semiconductor device is kept until the contact opening process and the aluminum wiring process are completed. It was impossible to check the electrical characteristics of the MOS transistor. That is, the characteristics of the MOS transistor are determined by forming a gate electrode, forming a diffusion layer region, and then performing heat treatment accordingly. However, in this case, the measurement itself was difficult because there was no electrode pad for measurement. The purpose of the electrical characteristic check transistor is to monitor the electrical characteristic of the transistor, but in the semiconductor device by the conventional method, there is a problem that it may be delayed to find an abnormal phenomenon in the electrical characteristic determination step. In addition, the quality and yield of the semiconductor device are reduced.
【０００４】本発明の目的はＭＯＳトランジスタの電気
的特性をいち早く測定し、特性の異常現象の早期発見を
行い品質及び歩留を向上できる半導体装置を提供するこ
とにある。An object of the present invention is to provide a semiconductor device in which the electrical characteristics of a MOS transistor can be quickly measured and an abnormal phenomenon of the characteristics can be detected early to improve quality and yield.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
電気特性測定用チェックトランジスタを有する半導体装
置であって、測定用電極パッドがひとつはゲート電極の
延長として形成され、他の２つの電極パッドは、ゲート
電極と同材質で、しかもゲート電極と同時に形成され、
ゲート絶縁膜を一部開孔し、拡散層と直接的に接続され
ている電極パッドを有している。The semiconductor device of the present invention comprises:
A semiconductor device having a check transistor for measuring electrical characteristics, wherein one electrode pad for measurement is formed as an extension of the gate electrode, and the other two electrode pads are formed of the same material as the gate electrode and at the same time as the gate electrode. Was
Part of the gate insulating film is opened and the electrode pad is directly connected to the diffusion layer.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例を示す電気特性チェックト
ランジスタの平面図、及びそのＡ−Ｂ線の断面図であ
る。The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an electric characteristic check transistor showing an embodiment of the present invention and a cross-sectional view taken along the line AB.
【０００７】この実施例は、半導体基板１の表面に素子
分離用の厚い絶縁膜２を形成し、ゲート絶縁膜３を付け
る。その後、後でゲート電極となる領域の幅方向と平行
にゲート絶縁膜３を開孔した開孔部４を形成し、半導体
基板を露出させる。必要とあれば、チャネルドープを行
う事もできる。その後、ゲート電極膜を付し、所定のパ
ターン形成を行いゲート電極５，電極パッド６，７，８
を同時に形成する。さらに、トランジスタを形成するた
めのイオン注入を行い、必要であればアニールを実施し
拡散層９，１０を形成する。この時点で基本的トランジ
スタ構造が形成されているため、トランジスタの電気的
特性をチェックすることができる。この構成はさらに絶
縁膜形成，コンタクト開孔などの工程を引き続き行う事
により、半導体装置の一部を構成することができる。In this embodiment, a thick insulating film 2 for element isolation is formed on the surface of a semiconductor substrate 1 and a gate insulating film 3 is attached. After that, an opening portion 4 is formed by opening the gate insulating film 3 in parallel with the width direction of a region to be a gate electrode later, and the semiconductor substrate is exposed. If necessary, channel doping can be performed. After that, a gate electrode film is applied and a predetermined pattern is formed to form the gate electrode 5, electrode pads 6, 7, 8
Are formed at the same time. Further, ion implantation for forming a transistor is performed, and if necessary, annealing is performed to form the diffusion layers 9 and 10. Since the basic transistor structure is formed at this point, the electrical characteristics of the transistor can be checked. With this structure, a part of the semiconductor device can be formed by continuing the steps of forming an insulating film and opening a contact.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、ゲート電
極を形成し、拡散層を形成した直後に、ＭＯＳトランジ
スタの電気的特性をチェックする事ができる。よって従
来技術のアルミニウム配線形成後にチェックしていた時
より、より早くＭＯＳトランジスタの電気的特性をチェ
ックする事が可能となり、トランジスタ特性の異常現象
等の問題を早期に発見し、対策ができる事になり、結果
的に半導体装置の品質及び歩留向上に寄与することがで
きる。As described above, according to the present invention, the electrical characteristics of the MOS transistor can be checked immediately after forming the gate electrode and forming the diffusion layer. Therefore, it becomes possible to check the electrical characteristics of the MOS transistor earlier than when checking after forming the aluminum wiring of the prior art, and it is possible to detect problems such as abnormal phenomenon of transistor characteristics early and take countermeasures. As a result, the quality and yield of the semiconductor device can be improved.
【図１】本発明の一実施例の半導体素子の主要部の平面
図及びそのＡ−Ｂ線の断面図である。FIG. 1 is a plan view of a main part of a semiconductor device according to an embodiment of the present invention and a cross-sectional view taken along line AB thereof.
１ 半導体基板 ２ 厚い絶縁膜 ３ ゲート絶縁膜 ４ ゲート絶縁膜開孔部 ５ ゲート電極 ６，７，８ 電極パッド ９，１０ 拡散層 1 Semiconductor Substrate 2 Thick Insulating Film 3 Gate Insulating Film 4 Gate Insulating Film Opening Area 5 Gate Electrode 6, 7, 8 Electrode Pad 9, 10 Diffusion Layer
Claims (1)
電極を有し、ゲート電極隣接領域に拡散層を形成した電
気特性測定用チェックトランジスタを有する半導体装置
において、測定用電極パッドがひとつはゲート電極の延
長として形成され、他の２つの電極パッドは、ゲート電
極と同材質で、しかもゲート電極と同時に形成され、ゲ
ート絶縁膜を一部開孔し拡散層と直接的に接続されてい
ることを特徴とする半導体装置。1. A semiconductor device having a gate insulating film and a gate electrode on the surface of a semiconductor substrate, and a check transistor for measuring electrical characteristics in which a diffusion layer is formed in a region adjacent to the gate electrode, wherein one measurement electrode pad is a gate electrode. The other two electrode pads are formed of the same material as the gate electrode, and are formed at the same time as the gate electrode, and the gate insulating film is partially opened and is directly connected to the diffusion layer. Characteristic semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3234199A JPH0574896A (en) | 1991-09-13 | 1991-09-13 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3234199A JPH0574896A (en) | 1991-09-13 | 1991-09-13 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574896A true JPH0574896A (en) | 1993-03-26 |
Family
ID=16967244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3234199A Pending JPH0574896A (en) | 1991-09-13 | 1991-09-13 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574896A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49108985A (en) * | 1973-02-20 | 1974-10-16 |
-
1991
- 1991-09-13 JP JP3234199A patent/JPH0574896A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49108985A (en) * | 1973-02-20 | 1974-10-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980127 |