JPH03196655A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03196655A JPH03196655A JP33963289A JP33963289A JPH03196655A JP H03196655 A JPH03196655 A JP H03196655A JP 33963289 A JP33963289 A JP 33963289A JP 33963289 A JP33963289 A JP 33963289A JP H03196655 A JPH03196655 A JP H03196655A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- source
- probe pad
- equalizing
- contact holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000000523 sample Substances 0.000 claims description 14
- 238000011156 evaluation Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 abstract description 6
- 239000010937 tungsten Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に電気的特性評価専用の
素子の探針パッドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a probe pad of an element dedicated to evaluating electrical characteristics.
半導体装置の製造工程において、内部素子の電気的特性
を測定するために電気的特性評価専用の素子が設けられ
ている。In the manufacturing process of a semiconductor device, an element dedicated to electrical characteristic evaluation is provided to measure the electrical characteristics of internal elements.
アルミニウム配線工程において形成される探針バッドに
より、電気的特性を測定することができる。Electrical characteristics can be measured using the probe pad formed in the aluminum wiring process.
従来技術におけるＭＯＳ−ＦＥＴ型素子について第５図
（ａ）〜（ｄ）の平面図と、それぞれのＡ−Ｂ断面図で
ある第６図（ａ）〜（ｄ）を参照して説明する。A conventional MOS-FET type element will be described with reference to the plan views of FIGS. 5(a) to 5(d) and FIGS. 6(a) to 6(d), which are cross-sectional views taken along line A-B.
はじめに第５図（ａ）、第６図（ａ）に示すように、シ
リコン基板１の表面にＬＯＣＯ３法によりフィールド酸
化膜２が形成され、ゲート酸化膜３、ゲート電極４、ソ
ース−ドレイン層５、酸化膜６が形成され、ＰＳＧ膜７
が形成される。First, as shown in FIGS. 5(a) and 6(a), a field oxide film 2 is formed on the surface of a silicon substrate 1 by the LOCO3 method, and a gate oxide film 3, a gate electrode 4, and a source-drain layer 5 are formed. , an oxide film 6 is formed, and a PSG film 7 is formed.
is formed.
つぎに第５図（ｂ）、第６図（ｂ）に示すように、コン
タクト孔８が形成される。Next, as shown in FIGS. 5(b) and 6(b), contact holes 8 are formed.
つぎに第５図（Ｃ）、第６図（ｃ）に示すように、アル
ミニウムからなる探針パッド１０が形成されて素子部が
完成する。Next, as shown in FIGS. 5(C) and 6(c), a probe pad 10 made of aluminum is formed to complete the element section.
あるいは第５図（Ｃ）、第６図（Ｃ）の替りに第５図（
ｄ）、第６図（ｄ）に示すように、選択ＣＶＤ法により
、コンタクト孔８にタングステン９を埋め込んでからア
ルミニウムからなる探針パッド１０を形成される。Alternatively, Figure 5 (C) and Figure 6 (C) can be replaced with Figure 5 (C) and Figure 6 (C).
d) As shown in FIG. 6(d), a probe pad 10 made of aluminum is formed after tungsten 9 is buried in the contact hole 8 by selective CVD.
従来技術による電気的特性評価専用の素子は、アルミニ
ウム膜からなる探針パッドを、アルミニウム配線工程に
おいて形成するので、配線工程が終了するまで電気的測
定評価ができなかった。In the prior art device dedicated to electrical characteristic evaluation, the probe pad made of an aluminum film is formed during the aluminum wiring process, so electrical measurement and evaluation cannot be performed until the wiring process is completed.
配線工程の前でプロセスを制御したり特性不良対策を講
じたりすることができなかった。It was not possible to control the process or take measures against characteristic defects before the wiring process.
本発明の電気的特性評価専用の素子は、測定用探針パッ
ドと同等の大きさのコンタクト孔を開口し、金属を選択
埋め込みして、探針パッドを形成されたものである。In the element exclusively used for electrical characteristic evaluation of the present invention, a contact hole having the same size as a measurement probe pad is opened, and a metal is selectively filled in the contact hole to form a probe pad.
本発明の第１の実施例について、第１図（ａ）〜（ｃ）
の平面図と、それぞれのＡ−Ｂ断面図である第２図（ａ
）〜（Ｃ）を参照して説明する。Regarding the first embodiment of the present invention, FIGS. 1(a) to (c)
Figure 2 (a) is a plan view of the
) to (C).
はじめに第１図（ａ）、第２図（ａ）に示すように、シ
リコン基板１の表面にＬＯＣＯ３法によりフィールド酸
化膜２が形成され、ゲート酸化膜３が形成される。First, as shown in FIGS. 1(a) and 2(a), a field oxide film 2 is formed on the surface of a silicon substrate 1 by the LOCO3 method, and then a gate oxide film 3 is formed.
つぎにポリシリコンからなるゲート電極４の端部がソー
ス５ａおよびドレイン５ｂの探針パッドと同等の大きさ
（例えば７０μｍ×７０μｍ）に形成される。Next, the end portion of the gate electrode 4 made of polysilicon is formed to have the same size as the probe pads of the source 5a and drain 5b (for example, 70 μm×70 μm).
つぎにソース−ドレイン層５、酸化膜６が形成されたの
ち、ＰＳＧ膜７が形成される。Next, a source-drain layer 5 and an oxide film 6 are formed, and then a PSG film 7 is formed.
つぎに第１図（ｂ）、第２図（ｂ）に示すように、（例
えば５０μｍ×５０μｍ）の大きなコンタクト孔８が形
成される。Next, as shown in FIG. 1(b) and FIG. 2(b), a large contact hole 8 (for example, 50 μm×50 μm) is formed.
つぎに第１図（Ｃ）、第２図（Ｃ）に示すように、選択
ＣＶＤ法により、コンタクト孔８にタングステン９を埋
め込まれて探針用のパッド９ａが完成する。Next, as shown in FIGS. 1(C) and 2(C), tungsten 9 is embedded in the contact hole 8 by selective CVD to complete a probe pad 9a.
つぎに本発明の第２の実施例について、第３図（ａ）の
平面図と、そのＡ−Ｂ断面図である第３図（ｂ）に示す
。Next, a second embodiment of the present invention is shown in the plan view of FIG. 3(a) and FIG. 3(b), which is a cross-sectional view taken along the line AB.
ここではゲート酸化膜３の上のポリシリコン膜４ａの抵
抗を測定することができる。Here, the resistance of the polysilicon film 4a on the gate oxide film 3 can be measured.
つぎに本発明の第３の実施例について、第４図（ａ）の
平面図と、そのＡ−Ｂ断面図である第４図（ｂ）に示す
。Next, a third embodiment of the present invention is shown in a plan view in FIG. 4(a) and in FIG. 4(b), which is a sectional view taken along the line AB.
ここでは拡散層５Ｃの抵抗を測定することができる。Here, the resistance of the diffusion layer 5C can be measured.
探針用のパッドと同等の大きさのコンタクト孔を形成す
ることにより、配線工程の前に評価専用の素子で内部素
子の電気的特性を測定してプロセスを制御したり特性不
良対策を講じたりすることができるようになった。By forming a contact hole with the same size as the probe pad, it is possible to measure the electrical characteristics of internal elements with a dedicated evaluation element before the wiring process, and to control the process and take measures against characteristic defects. Now you can.
配線工程前に素子の検査を行なって、不良の素子を排除
できるので、無駄な配線工程を省くことができるという
効果がある。Since the elements can be inspected before the wiring process and defective elements can be eliminated, there is an effect that unnecessary wiring processes can be omitted.
第１図（ａ）〜（ｃ）は本発明の第１の実施例を示す平
面図、第２図（ａ）〜（Ｃ）は本発明の第１の実施例を
示す断面図、第３図（ａ）は本発明の第２の実施例を示
す平面図、第３図（ｂ）は本発明の第２の実施例を示す
断面図、第４図（ａ）は本発明の第３の実施例を示す平
面図、第４図（ｂ＞は本発明の第３の実施例を示す断面
図、第５図（ａ）〜（ｄ）は従来技術を示す平面図、第
６図（ａ）〜（ｄ）は従来技術を示す断面図である。
■・・・シリコン基板、２・・・フィールド酸化膜、３
・・・ゲート酸化膜、４・・・ゲート電極、５−・・・
ソース−ドレイン層、５ａ・・・ソース、５ｂ・・・ド
レイン、５Ｃ・・・拡散層、６・・・酸化膜、７・・・
ＰＳＧ膜、８・・・コンタクト孔、９・・・タングステ
ン、９・・・タングステン、９ａ・・・探針パッド（タ
ングステン）、１０・・・探針パッド（アルミニウム）
。FIGS. 1(a) to (c) are plan views showing the first embodiment of the present invention, FIGS. 2(a) to (C) are sectional views showing the first embodiment of the present invention, and FIGS. Figure (a) is a plan view showing the second embodiment of the present invention, Figure 3 (b) is a sectional view showing the second embodiment of the present invention, and Figure 4 (a) is the third embodiment of the present invention. 4(b) is a sectional view showing the third embodiment of the present invention, FIGS. 5(a) to (d) are plan views showing the conventional technology, and FIG. a) to (d) are cross-sectional views showing the prior art. ■...Silicon substrate, 2...Field oxide film, 3
... Gate oxide film, 4... Gate electrode, 5-...
Source-drain layer, 5a...source, 5b...drain, 5C...diffusion layer, 6...oxide film, 7...
PSG film, 8... Contact hole, 9... Tungsten, 9... Tungsten, 9a... Probe pad (tungsten), 10... Probe pad (aluminum)
.
Claims (1)
いて、測定用探針パッドと同等の大きさの前記素子のコ
ンタクト孔を開口し、金属を選択埋め込みして、探針パ
ッドが形成されていることを特徴とする半導体装置。In an element dedicated to electrical characteristic evaluation provided in a semiconductor device, a contact hole of the element of the same size as a measurement probe pad is opened and a metal is selectively filled to form a probe pad. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33963289A JPH03196655A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33963289A JPH03196655A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196655A true JPH03196655A (en) | 1991-08-28 |
Family
ID=18329335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33963289A Pending JPH03196655A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196655A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414336B2 (en) | 1999-07-26 | 2002-07-02 | Nec Corporation | Semiconductor device capable of improving manufacturing |
-
1989
- 1989-12-26 JP JP33963289A patent/JPH03196655A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414336B2 (en) | 1999-07-26 | 2002-07-02 | Nec Corporation | Semiconductor device capable of improving manufacturing |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7355201B2 (en) | Test structure for measuring electrical and dimensional characteristics | |
| JPH03196655A (en) | Semiconductor device | |
| JPH0147011B2 (en) | ||
| JPH0322916Y2 (en) | ||
| JP2943399B2 (en) | Semiconductor integrated circuit | |
| KR100333368B1 (en) | Test pattern for checking defects in semiconductor device | |
| JP2933394B2 (en) | Method for measuring characteristics of semiconductor devices | |
| JP2665075B2 (en) | Integrated circuit check pattern and check method thereof | |
| JPH05129553A (en) | Semiconductor device | |
| JP2867525B2 (en) | Contact hole electromigration test device and method of manufacturing the same | |
| JPS6333665A (en) | Contact resistance measuring pattern | |
| JPH03268441A (en) | Substrate of semiconductor integrated circuit | |
| JP3223961B2 (en) | Interlayer film flatness measuring function element and interlayer film flatness evaluation method | |
| KR100440071B1 (en) | A test pattern of semiconductor device | |
| KR20050064773A (en) | A method for analyzing out a bedness of a semiconductor device | |
| JPH04129240A (en) | Semiconductor device | |
| JPH0574896A (en) | Semiconductor devices | |
| JPS6242378B2 (en) | ||
| KR100265841B1 (en) | Semiconductor element manufacturing process monitoring method | |
| KR20000026676A (en) | Method for evaluating a gate size of a semiconductor device | |
| JPH07106391A (en) | Semiconductor device and test method therefor | |
| JPH04359534A (en) | Semiconductor device | |
| JP2745556B2 (en) | Failure analysis method for semiconductor device | |
| JPH0231465A (en) | Non-volatile memory wafer | |
| JPS635838B2 (en) |